CN103546152B - Pipeline architecture analog digital converter and offset voltage influence correction method thereof - Google Patents
Pipeline architecture analog digital converter and offset voltage influence correction method thereof Download PDFInfo
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Abstract
A kind of pipeline architecture analog digital converter and offset voltage influence correction method thereof, the method, according to the first input voltage, produces first class's code and the first output voltage；Second class's code is produced according to the first output voltage；Produce according to output voltage and confirm code；With reference to first class's code and confirmation code, determine the first correction code；When first class's code is different from the first correction code, with the first correction code, first class's code is corrected.
Description
Technical field
The present invention relates to a kind of analog-to-digital conversion circuit, and turn particularly to including multiple digital simulation
The analog-to-digital conversion circuit of parallel operation.
Background technology
Analog-digital converter (Analog digital converter；ADC), as the term suggests, it is to simulate
Data signal is converted to digital code, and analogue signal is being digitized by the action of this conversion exactly
And quantify.Analog-digital converter is to want angle in composite signal integrated circuits.Once analogue signal
Being converted to digital field, the signal processing of those complexity just can come real in the way of the most succinct
Existing, and the immunity of noise also can be elevated.In the middle of some situations, come real with deep-sub-micrometer technique
Existing analog-digital converter, can reduce power consumption.
Analog-digital converter uses several functions framework, such as integration, the most asymptotic (successive
Approximation), quick flashing, and delta-sigma framework.Recently, the simulation numeral of pipeline architecture
Transducer has become the main flow of analog-digital converter, can be used in the middle of high-speed applications, such as electricity
Lotus coupling element image processing (CCD imaging), ultrasound medical treatment photography, digitized video, Yi Jitong
Letter technology, such as, look at line modem (cable modem), and Fast Ethernet network.Owing to having height
Accuracy, high output rating, and the characteristic of low-power consumption, the analog-digital converter of pipeline architecture
It is widely used in the middle of various Circuits System.Additionally, than the analog-digital converter of other kind
Framework, pipeline architecture usually provides preferably performance and less area under set power.
By numeric error calibration function, the ratio that the analog-digital converter tolerable of pipeline architecture is bigger
Relatively device voltage deviation (comparator voltage offset).But, due to the confession in the middle of advanced technologies
Answering voltage VDD to decline, reference voltage is difficult to reach enough opereating specifications, causes comparator voltage inclined
The tolerance of shifting amount reduces.
Fig. 1 Yu Fig. 2 is to illustrate with and omit sample and hold (Sample and hold
Amplifier) conventional line framework analog-digital converter.Traditional pipeline architecture Analog-digital Converter
Device typically can use class's circuit 101 and sample and hold (sample and hold amplifier；
SHA) 113, wherein, class's circuit 101 generally includes analog-digital converter 111 and hierarchical numeral
Analog converter (multiplying digital to analog converter；MDAC) 103, this hierarchical number
Word analog converter 103 has sampling and keeps (sample and hold circuit；S/H) circuit 105, number
Word analog converter 107, and amplifier 109.In order to provide stable synchronizing signal to class's circuit
Hierarchical digital analog converter 103 and analog-digital converter 111 in 101 are sampled,
It is thus desirable to use sample and hold 113.But, sample and hold 113 can increase power
Consume and noise jamming, therefore, in the middle of lower powered pipeline architecture analog digital converter, logical
Chang Buhui uses sample and hold 113 so that omit the framework of sample and hold in the middle of Fig. 2
Become main flow.
But, due to not mating of sampling, sample-and-hold circuit 105 and digital analog converter 107
Between be usually present inevasible time sequence difference, cause increasing along with fan-in/fan-out (fin) with letter
Number relevant side-play amount increases.Consequently, it is possible to the comparator offset amount that can be tolerated will be reduced, mould
The input signal frequency range intending digital converter also can be locked.
Fig. 3 and Fig. 4 is the output electricity illustrating class's circuit in the middle of pipeline architecture analog digital converter
Corrugating schematic diagram.In the middle of Fig. 3 and Fig. 4, the side-play amount that some A represents comparator with some B surpasses
Cross the situation of normal operation range.Owing to the side-play amount of comparator can be amplified by follow-up circuit, this will
The generation of error code and the generation of other gross error can be caused.
Summary of the invention
Therefore, it is an object of the invention to provide a kind of offset voltage influence correction method, can be for comparing
Error code and off-limits output voltage that device offset voltage is caused are corrected, it is to avoid whole
The running of body circuit makes a mistake.
According to the embodiment of the present invention, the offset voltage influence correction side of pipeline architecture analog digital converter
Method, according to the first input voltage, produces first class's code and the first output voltage；According to first
Output voltage produces second class's code；Produce according to the first output voltage and confirm code；With reference to first
Class's code and confirmation code, determine the first correction code；When first class's code is different from first
During correction code, with the first correction code, first class's code is corrected.
It is a further object of the present invention to provide a kind of pipeline architecture analog digital converter, can self-correction
Error code that comparator offset voltage is caused and off-limits output voltage, it is to avoid overall electricity
The running on road makes a mistake.
According to another embodiment of the present invention, pipeline architecture analog digital converter, containing confirming that code produces
Raw device, code correcting circuit, and offset voltage correction circuit.Confirm that code generator is according to pipeline
The first output voltage that first class's circuit of framework analog-digital converter is exported, produces and confirms generation
Code；Code correcting circuit receives respectively by first class's circuit, second class's circuit, and confirms generation
First class's code, second class's code produced by code generator, and confirm code, code school
Positive circuit is also with reference to confirming code, first class's code, and second class's code corrects mistake
First class's code and second class's code；Offset voltage correction circuit according to second class's code with
Confirm code, adjust the size of the output voltage of second class's circuit.
The offset voltage influence correction method of above example and pipeline architecture analog digital converter,
Error code and the off-limits output voltage that can be caused for comparator offset voltage carry out school
Just, it is to avoid the running of integrated circuit makes a mistake.
Accompanying drawing explanation
For above and other objects of the present invention, feature, advantage can be become apparent with embodiment,
Being described as follows of accompanying drawing:
Fig. 1 Yu Fig. 2 is the conventional line framework simulation illustrating with and omitting sample and hold
Digital converter.
Fig. 3 and Fig. 4 is the output electricity illustrating class's circuit in the middle of pipeline architecture analog digital converter
Corrugating schematic diagram.
Fig. 5 is the block chart of the pipeline architecture analog digital converter illustrating embodiment of the present invention.
Fig. 6 is the circuit diagram confirming code generator illustrating embodiment of the present invention.
Fig. 7 is the circuit diagram illustrating embodiment of the present invention the first class circuit.
Fig. 8 is the circuit diagram illustrating embodiment of the present invention the second class circuit.
Fig. 9 is to illustrate embodiment of the present invention pipeline architecture analog digital converter offset voltage to affect school
The flow chart of correction method.
Figure 10 is the code truth table illustrating embodiment of the present invention pipeline architecture analog digital converter.
Figure 11 is to illustrate embodiment of the present invention pipeline architecture analog digital converter input signal and output
The conversion diagram of signal.
Figure 12 is to illustrate to represent the true of pipeline architecture analog digital converter code in embodiment of the present invention
Value table.
Figure 13 then illustrates the waveform diagram of class's circuit output voltage in embodiment of the present invention.
Detailed description of the invention
The offset voltage influence correction method of following example and pipeline architecture analog digital converter,
Error code and the off-limits output voltage that can be caused for comparator offset voltage carry out school
Just, it is to avoid the running of integrated circuit makes a mistake.
Refer to Fig. 5, it illustrates the square of pipeline architecture analog digital converter of embodiment of the present invention
Figure.Pipeline architecture analog digital converter 500 is containing several classes circuit, and namely the first class is electric
Road 503, second class's circuit the 505, the 3rd class's circuit 507, until N class circuit.Pipe
Line architecture analog-digital converter 500 contains confirmation code generator 511, offset voltage correction further
Circuit 513, and code correcting circuit 501, wherein, code correcting circuit 501 has correcting code and produces
Raw device 521 and built-in decoding logic circuit 519.
First class's circuit 503 receives input voltage vin, and produces the first rank according to input voltage vin
Level code C11, C12 and the first output voltage Vout1；Second class's circuit 505 is defeated according to first
Go out voltage Vout1 and produce second class code C22, C23.Confirm that code generator 511 is then according to the
One output voltage Vout1 produces and confirms code C21, C24.
Code correcting circuit 501 receives respectively by first class's electricity of pipeline architecture analog digital converter
Road 503, second class's circuit 505, and confirm first class's generation produced by code generator 511
Code C11, C12, second class code C22, C23, and confirm code C21, C24.Code school
Positive circuit 501, with reference to confirming code C21, C24 and first class code C11, C12, corrects
First class code C11, C12 and second class code C22, C23 of mistake.Furthermore, it is understood that
The correction code of code correcting circuit 501 produce circuit 521 can with reference to the first class code C11, C12,
Second class code C22, C23, and confirm code C21, C24, produce correction code, so
After correction code is passed to the decoding logic circuit 519 of code correcting circuit 501.Finally, code school
Positive circuit 501 can export digital code according to this.
Additionally, offset voltage correction circuit 513 is according to second class code C22, C23 and confirmation code
C21, C24, adjust the size of the output voltage Vout2 of second class's circuit 505.
Refer to Fig. 6, it illustrates the circuit diagram confirming code generator of embodiment of the present invention.
As depicted in Fig. 6, the first comparator 601 and the second comparator 607 are arranged at confirmation code and produce
In the middle of raw device, the 3rd comparator 603 and the 4th comparator 605 are then arranged at second class's circuit and work as
In.Additionally, the 5th comparator 609 and the 6th comparator 611 are then arranged in first class's circuit.
First comparator 601 has first input end and the second input, and first input end connects defeated
Inbound port receives input voltage vin, and the second input is then connected to reference voltage input and receives
Reference voltage Vref.Second comparator 607 has the 3rd input and a four-input terminal, and the 3rd
Input is connected to input port to receive input voltage vin, and four-input terminal is then connected to negative with reference to electricity
Pressure side receives negative reference voltage-Vref.
First comparator 601 compares input voltage vin, reference voltage Vref with the second comparator 607
And negative reference voltage-Vref, output confirmation code C21, C24 the most according to this.
Refer to Fig. 7, it illustrates the circuit diagram of embodiment of the present invention the first class circuit.First class
Circuit is a part of hierarchical digital analog converter (MDAC), and this first class main circuit to include
Operational amplifier 701, first switchs sw1, second switch sw2, the 3rd switch sw3, the 4th switch
Sw4, the 5th switch sw5, the first electric capacity cs1 and the second electric capacity cs2.Operational amplifier 701 just has
Input+, negative input end-, and outfan, wherein positive input terminal+be connected to earth terminal.
First switch sw1 is connected between negative input end-and earth terminal；Second switch sw2 and the 3rd
Switch sw3 has several first end points, and these first end points are connected to voltage input end to receive input
Voltage Vin.The end points of the first electric capacity cs1 and the second electric capacity cs2 is connected to operational amplifier 701
Negative input end-, another end points of the first electric capacity cs1 and the second electric capacity cs2 is then connected to second switch
Second end points of sw2 and the 3rd switch sw3；4th switch sw4 is connected to the of second switch sw2
Two ends and the outfan of operational amplifier 701.One end of 5th switch sw5 is connected to the 3rd switch
Second end of sw3, the other end of the 5th switch sw5 is then connected to reference voltage input terminal Vdac.
Second switch sw2 and the 3rd switch sw3 is controlled by the first clock signal ck1, the 4th switch
Sw4 and the 5th switch sw5 is controlled by the 3rd clock signal ck3, and the first switch sw1 is then by second
Clock signal ck2 is controlled.First clock signal ck1 is alignd with the rising edge of second clock signal ck2
Unanimously, the falling edge of the 3rd clock signal ck3 then align the first clock signal ck1 and second clock letter
The rising edge of number ck2.Furthermore, it is understood that the high levle cycle relatively second clock of the first clock signal ck1
The high levle cycle of signal ck2 is for long.
By such framework and clock signal sequential, when first class's code equal to 2 ' b00 or
During 2 ' b11, the output voltage Vout1 come from first class's circuit can directly add and subtract reference voltage.
Refer to Fig. 8, it illustrates the circuit diagram of embodiment of the present invention the second class circuit.Second class
Main circuit operational amplifier to be included 801, first switch sw1, second switch sw2, the 3rd switch sw3,
4th switch sw4, the 5th switch sw5, the 6th switch sw6, the 7th switch sw7, the first electric capacity cs1,
Second electric capacity cs2 and the 3rd electric capacity cs3.Operational amplifier 801 have positive input terminal+, negative input
End-, and outfan, wherein positive input terminal+be connected to earth terminal, the 3rd electric capacity cs3 is then connected to bear
Input--and between the outfan of operational amplifier 801.
First switch sw1 is connected between negative input end-and earth terminal；Second switch sw2 and the 3rd
Switch sw3 has several first end points, and these first end points are connected to voltage input end to receive input
Voltage Vout1.The end point of the first electric capacity cs1 and the second electric capacity cs2 is connected to operational amplifier 801
Negative input end-, another end points of the first electric capacity cs1 and the second electric capacity cs2 is then connected to second and opens
Close second end points of sw2 and the 3rd switch sw3；4th switch sw4 is connected to second switch sw2's
Second end and the first reference voltage end Vdac1.One end of 5th switch sw5 is connected to the 3rd switch
Second end of sw3, the other end of the 5th switch sw5 is then connected to the second reference voltage input terminal Vdac2.
Second switch sw2 and the 3rd switch sw3 is controlled by the first clock signal ck1, the 4th switch
Sw4, the 5th switch sw5, and the 7th switch sw7 then controlled by the 3rd clock signal ck3, the
One switch sw1 and the 6th switch are then controlled by second clock signal ck2.First clock signal ck1
Aliging consistent with the rising edge of second clock signal ck2, the falling edge of the 3rd clock signal ck3 then aligns
First clock signal ck1 and the rising edge of second clock signal ck2.Furthermore, it is understood that the first clock
The high levle cycle compared with second clock signal ck2 in the high levle cycle of signal ck1 is for long.
By such framework and clock signal sequential, when second class's code and the group confirming code
Close (C21, C22, C23, C24) and be equal to 4 ' b0000,4 ' b1000,4 ' b1110, or during 4 ' b1111,
The output voltage Vout2 come from second class's circuit can directly add and subtract reference voltage.
Refer to Fig. 9, it illustrates embodiment of the present invention pipeline architecture analog digital converter offset voltage
Affect the flow chart of bearing calibration.The method is first depending on the first input voltage, produces for first class's generation
Code and the first output voltage (step 901), and produce second class's code (step according to the first output voltage
Rapid 903).Then, produce according to the first output voltage and confirm code (step 905), and with reference to the first rank
Level code and confirmation code, determine the first correction code (step 907).
Then, can confirm whether first class's code is different from the first correction code (step 909), when
When one class's code is different from the first correction code, with the first correction code, first class's code is carried out
Correction (step 911), and adjust second with reference voltage (+Vref) or negative reference voltage (-Vref)
Second output voltage of class's circuit.For example, if the second output voltage is the highest, the second output
Voltage will deduct reference voltage, reduces the second output voltage.
Specifically, confirm the generation of code, be to the first output voltage and reference voltage (+Vref)
And negative reference voltage (-Vref) compares, as represented by the form of Figure 10 and the waveform of Figure 11
, when the first output voltage exceeds opereating specification less than-Vref (the namely some A in the middle of Figure 11),
If class's code and output voltage are not immediately corrected, it will cause error code (missing
Code) generation.In order to avoid the generation of error code, the confirmation code equal to 2 ' b00 can be produced
(c21, c24) and the first correction code (MSB1LSB1) equal to 2 ' b00 or 2 ' b01, replace
First class's code of mistake.
In the middle of other embodiments, when the first output voltage exceedes+Vref and goes beyond the scope, (Figure 11 works as
In some B), can produce confirmation code (c21c24) equal to 2 ' b11 with equal to 2 ' b01's or 2 ' b10
First correcting code (MSB1LSB1).
Figure 12 illustrates and represents in embodiment of the present invention that pipeline architecture analog digital converter is normal and mistake
The truth table of state, Figure 13 then illustrates the waveform of class's circuit output voltage in embodiment of the present invention and shows
It is intended to.In the middle of the embodiment depicted in Figure 12 Yu Figure 13, consider that input voltage is in essence further
On be higher than reference voltage or less than the situation of negative reference voltage, in the middle of these situations, voltage
Can go beyond the scope and not result from the offset voltage of comparator.In the middle of 13 figures, put A, D, E, H
Why can go beyond the scope, be because original input voltage the highest, the voltage of these points is also
Need not revise especially.
Therefore, when first class's code, confirmation code, and the combination of second class's code equal to 6 ' b001111,
6 ' b100000,6 ' b101111, and during 6 ' b110000, equal to the first correction code (MSB2 of 2 ' b01
LSB2) can be used to revise first class's code (c11c12).
On the other hand, if finding first class's code and the first correction code in the middle of step 909 also
Without different, then first class's code will remain stationary (step 913).Furthermore, it is also possible to
The second correction code is determined with reference to first class's code, second class's code and correction code, when
When second class's code is different from the second correction code, corrected for the second correction generation with the second correction code
Code.
According to above example, the wrong class code caused due to comparator offset voltage with exceed
The output voltage of scope can be revised in advance, therefore can prevent the generation of error code, avoid defeated simultaneously
Going out voltage outside range, the analog-digital converter reducing pipeline architecture operates the probability made a mistake.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any
Those skilled in the art, without departing from the spirit and scope of the present invention, when can various modifications may be made with become
Type, therefore protection scope of the present invention is when being as the criterion with claims.
Claims (14)
1. an offset voltage influence correction method for pipeline architecture analog digital converter, described method
Comprise:
According to the first input voltage, produce first class's code and the first output voltage；
Second class's code is produced according to described first output voltage；
Produce according to described first output voltage and confirm code；
With reference to described first class's code and described confirmation code, determine the first correction code；And
When described first class's code is different from described first correction code, with described first correction generation
Described first class's code is corrected by code.
2. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1
Method, also comprises:
When described first class's code is different from described first correction code, with reference voltage or negative
Reference voltage, adjusts the second output voltage of second class's circuit.
3. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1
Method, wherein enters described first output voltage and the first reference voltage and the first negative reference voltage
Row compares, and produces described confirmation code.
4. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 3
Method, described first class's code that wherein reference look-up tables is stored and described confirmation code, with
Determine described first correction code.
5. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1
Method, wherein when the combination of described first class's code and described confirmation code is corresponding to 4 ' b1000
Time, correct described first class's code with the described first correction code equal to 2 ' b00.
6. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1
Method, wherein when the combination of described first class's code and described confirmation code is corresponding to 4 ' b0011
Time, correct described first class's code with the described first correction code equal to 2 ' b01.
7. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1
Method, wherein when the combination of described first class's code and described confirmation code is corresponding to 4 ' b1011
Time, correct described first class's code with the described first correction code equal to 2 ' b10.
8. the offset voltage influence correction of pipeline architecture analog digital converter as claimed in claim 1
Method, also comprises:
With reference to described first class's code, described second class's code, and described confirmation code, certainly
Fixed second correction code；And
When described second class's code is different from described second correction code, with described second correction generation
Code corrects described second class's code.
9. a pipeline architecture analog digital converter, comprises:
Confirm code generator, with first class's electricity according to described pipeline architecture analog digital converter
The first output voltage that road is exported, produces and confirms code；
Code correcting circuit, to receive respectively by described first class's circuit, second class's circuit, with
And first class's code, second class's code produced by described confirmation code generator, and described
Confirm code, described code correcting circuit also with reference to described confirmation code, described first class's code,
And described second class's code corrects described first class's code of mistake and described second class
Code；And
Offset voltage correction circuit, according to described second class's code and described confirmation code, to adjust
The size of the output voltage of described second class's circuit.
10. pipeline architecture analog digital converter as claimed in claim 9, wherein said confirmation generation
Code generator comprises:
First comparator, has first input end and the second input, and described first input end connects
Input port receives input voltage, and described second input is then connected to reference voltage input
Receive reference voltage；And
Second comparator, has the 3rd input and four-input terminal, and described 3rd input connects
Receiving described input voltage to described input port, described four-input terminal is then connected to negative with reference to electricity
Pressure side receives negative reference voltage.
11. pipeline architecture analog digital converter as claimed in claim 9, wherein said first rank
Level circuit comprises:
Operational amplifier, has positive input terminal, negative input end, and outfan, wherein said the most defeated
Enter end and be connected to earth terminal；
First switch, is connected between described negative input end and described earth terminal；
Second switch and the 3rd switch, have multiple first end points, and the plurality of first end points connects
Input voltage is received to voltage input end；
First electric capacity and the second electric capacity, the end point of described first electric capacity and described second electric capacity is even
It is connected to the described negative input end of described operational amplifier, described first electric capacity and described second electric capacity
Another end points is then connected to multiple second end points of described second switch and described 3rd switch；
4th switch, is connected to described second end of described second switch and described operational amplifier
Described outfan；And
5th switch, one end of described 5th switch is connected to described second end of described 3rd switch,
The other end of described 5th switch is then connected to reference voltage input terminal.
12. pipeline architecture analog digital converter as claimed in claim 11, wherein said second opens
Close and controlled by the first clock signal with described 3rd switch, described 4th switch and described 5th switch
Being controlled by the 3rd clock signal, described first switch is then controlled by second clock signal.
13. pipeline architecture analog digital converter as claimed in claim 12, when wherein said first
Clock signal aligns consistent with the rising edge of described second clock signal, the decline of described 3rd clock signal
Edge then aligns described first clock signal and the plurality of rising edge of described second clock signal.
14. pipeline architecture analog digital converter as claimed in claim 13, when wherein said first
The high levle cycle of the high levle cycle more described second clock signal of clock signal is for long.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861969B1 (en) * | 2004-03-03 | 2005-03-01 | Analog Devices, Inc. | Methods and structures that reduce memory effects in analog-to-digital converters |
| CN1647388A (en) * | 2002-04-02 | 2005-07-27 | 艾利森电话股份有限公司 | Comparator offset calibration for A/D converters |
| CN101355362A (en) * | 2007-07-23 | 2009-01-28 | 联发科技股份有限公司 | Analog-to-digital converter and method of gain error calibration thereof |
| CN101854174A (en) * | 2010-05-18 | 2010-10-06 | 上海萌芯电子科技有限公司 | Streamline analog-digital converter and sub conversion stage circuit thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6606042B2 (en) * | 2001-05-23 | 2003-08-12 | Texas Instruments Incorporated | True background calibration of pipelined analog digital converters |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1647388A (en) * | 2002-04-02 | 2005-07-27 | 艾利森电话股份有限公司 | Comparator offset calibration for A/D converters |
| US6861969B1 (en) * | 2004-03-03 | 2005-03-01 | Analog Devices, Inc. | Methods and structures that reduce memory effects in analog-to-digital converters |
| CN101355362A (en) * | 2007-07-23 | 2009-01-28 | 联发科技股份有限公司 | Analog-to-digital converter and method of gain error calibration thereof |
| CN101854174A (en) * | 2010-05-18 | 2010-10-06 | 上海萌芯电子科技有限公司 | Streamline analog-digital converter and sub conversion stage circuit thereof |
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