TWI481200B - Pipelined analog to digital converter and method for correcting voltage offset influence thereof - Google Patents

Description

Pipeline architecture analog digital converter and its offset voltage influence correction method

The present invention relates to an analog-to-digital conversion circuit, and more particularly to an analog-to-digital conversion circuit incorporating a multi-digit analog converter.

Analog digital converter (ADC), as its name implies, converts a class of data signals into a digit code. The action of this conversion is to digitize and quantize the analog signal. Analog-to-digital converters are the corners of mixed-signal integrated circuits. Once the analog signal is converted to the digital domain, those complex signal processing can be implemented in a more concise manner, and the immunity of the noise is also improved. In some cases, implementing analog-to-digital converters in deep sub-micron processes will reduce power consumption.

Analog-to-digital converters employ a variety of functional architectures such as integration, successive approximation, flash, and delta-sigma architecture. Recently, analog-to-digital converters in pipeline architectures have become the mainstream of analog-to-digital converters, and can be used in high-speed applications such as CCD imaging, ultrasonic medical photography, digital imaging, and communication technologies, such as Cable modem, and high-speed Ethernet. Due to its high accuracy, high output rate, and low power loss, the analog digital converter of the pipeline architecture has been widely used in various circuit systems. In addition, pipeline architectures typically provide better performance and smaller area at a given power than other types of analog-to-digital converter architectures.

With the digital error correction function, the pipeline architecture's analog digital converter can tolerate a large comparator voltage offset. However, due to the drop in the supply voltage VDD in the advanced process, it is difficult to achieve a sufficient operating range for the reference voltage, resulting in a decrease in the tolerance of the comparator voltage offset.

Figures 1 and 2 show a conventional pipeline architecture analog-to-digital converter with and without a sample and hold amplifier. Conventional pipeline architecture analog-to-digital converters typically employ a class circuit 101 and a sample and hold amplifier (SHA) 113, wherein the class circuit 101 typically includes an analog-to-digital converter 111 and a one-stage digital analog converter. A multiplying digital to analog converter (MDAC) 103 having a sample and hold circuit (S/H) circuit 105, a digital analog converter 107, and an amplifier 109. In order to provide a stable synchronization signal to the class digital analog converter 103 and the analog digital converter 111 in the class circuit 101 for sampling, it is necessary to employ the sample and hold amplifier 113. However, the sample-and-hold amplifier 113 increases power consumption and noise interference. Therefore, in a low-power pipeline architecture analog-to-digital converter, the sample-and-hold amplifier 113 is usually not used, so that the architecture of the sample-and-hold amplifier is omitted in FIG. Mainstream.

However, due to sampling mismatch, there is often an inevitable timing difference between the sample-and-hold circuit 105 and the digital analog converter 107, resulting in a signal-related offset that increases with fan-in/fan-fin. increase. As a result, the tolerable comparator offset will be reduced and the input signal bandwidth of the analog digital converter will be limited.

3 and 4 are schematic diagrams showing the output voltage waveforms of the class circuits among the pipeline architecture analog-to-digital converters. In FIGS. 3 and 4, point A and point B represent conditions in which the offset of the comparator exceeds the normal operating range. Since the offset of the comparator is amplified by subsequent circuits, this will result in the generation of error codes and other serious errors.

Therefore, an aspect of the present invention provides an offset voltage influence correction method that corrects an error code caused by a comparator offset voltage and an output voltage that is out of range, thereby avoiding an error in the operation of the overall circuit.

According to an embodiment of the present invention, an offset voltage influence correction method of a pipeline architecture analog digital converter generates a first class code and a first output voltage according to a first input voltage; generating a first according to the first output voltage a second class code; generating a confirmation code according to the first output voltage; determining a first correction code by referring to the first class code and the confirmation code; and when the first class code is different from the first correction code, the first correction code is The first class code is corrected.

Another aspect of the present invention provides a pipeline architecture analog-to-digital converter that can correct the error code caused by the comparator offset voltage and the out-of-range output voltage to avoid errors in the operation of the overall circuit.

In accordance with another embodiment of the present invention, a pipeline architecture analog to digital converter includes a acknowledgment code generator, a code correction circuit, and an offset voltage correction circuit. Confirming that the code generator generates one of the first output voltages according to one of the first-stage circuits of the pipeline architecture analog digital converter a code correction circuit receives a first class code, a second class code, and a confirmation code generated by the first class circuit, a second class circuit, and the confirmation code generator, respectively, and the code correction circuit also refers to the confirmation a code, a first class code, and a second class code to correct the wrong first class code and the second class code; the offset voltage correction circuit adjusts an output voltage of one of the second class circuits according to the second class code and the confirmation code size.

The offset voltage influence correction method and the pipeline architecture analog digital converter of the above embodiment can correct the error code caused by the comparator offset voltage and the out-of-range output voltage to avoid an error in the operation of the overall circuit.

The offset voltage influence correction method and the pipeline architecture analog digital converter of the following embodiments can correct the error code caused by the comparator offset voltage and the out-of-range output voltage to avoid an error in the operation of the overall circuit.

Please refer to FIG. 5, which is a block diagram of a pipeline architecture analog-to-digital converter according to an embodiment of the present invention. The pipeline architecture analog to digital converter 500 contains a number of class circuits, namely a first stage circuit 503, a second stage circuit 505, and a third stage circuit 507, up to the Nth stage circuit. The pipeline architecture analog to digital converter 500 further includes a confirmation code generator 511, an offset voltage correction circuit 513, and a code correction circuit 501 having a correction code generator 521 and built-in decoding logic circuit 519.

The first stage circuit 503 receives the input voltage Vin and generates first class codes C11, C12 and a first output voltage Vout1 in accordance with the input voltage Vin; the second stage circuit 505 generates second class codes C22, C23 in accordance with the first output voltage Vout1. The confirmation code generator 511 generates the confirmation codes C21, C24 in accordance with the first output voltage Vout1.

The code correction circuit 501 receives the first class circuit 503, the second class circuit 505, and the confirmation code generator 511 generated by the pipeline architecture analog-to-digital converter, respectively, the first class codes C11, C12, the second class codes C22, C23. , and confirm the codes C21, C24. The code correction circuit 501 corrects the erroneous first class codes C11 and C12 and the second class codes C22 and C23 with reference to the confirmation codes C21 and C24 and the first class codes C11 and C12. Further, the correction code generation circuit 521 of the code correction circuit 501 refers to the first class codes C11, C12, the second class codes C22, C23, and the confirmation codes C21, C24 to generate a correction code, and then passes the correction code to The decoding logic circuit 519 of the code correction circuit 501. Finally, the code correction circuit 501 outputs a digital code.

Further, the offset voltage correction circuit 513 adjusts the magnitude of the output voltage Vout2 of the second-stage circuit 505 in accordance with the second class codes C22, C23 and the confirmation codes C21, C24.

Please refer to FIG. 6, which is a circuit diagram of a confirmation code generator according to an embodiment of the present invention. As shown in FIG. 6, the first comparator 601 and the second comparator 607 are disposed in the confirmation code generator, and the third comparator 603 and the fourth comparator 605 are disposed in the second class circuit. Further, the fifth comparator 609 and the sixth comparator 611 are disposed in the first stage circuit.

The first comparator 601 has a first input terminal connected to the input port to receive the input voltage Vin, and a second input terminal connected to the positive reference voltage input terminal to receive the positive reference voltage Vref. The second comparator 607 has a third input connected to the input port to receive the input voltage Vin, and a fourth input connected to the negative reference voltage terminal to receive the negative reference voltage -Vref.

The first comparator 601 compares the input voltage Vin, the positive reference voltage Vref, and the negative reference voltage -Vref with the second comparator 607, and then outputs confirmation codes C21, C24.

Please refer to FIG. 7, which is a circuit diagram of a first stage circuit according to an embodiment of the present invention. The first-stage circuit is a part of a class-type digital analog converter (MDAC). The first-stage circuit mainly includes an operational amplifier 701, a first switch sw1, a first switch sw2, a third switch sw3, and a fourth switch sw4. The five switch sw5, the first capacitor cs1 and the first capacitor cs2. The operational amplifier 701 has a positive input terminal +, a negative input terminal -, and an output terminal, wherein the positive input terminal + is connected to a ground terminal.

The first switch sw1 is connected between the negative input terminal and the ground terminal; the second switch sw2 and the third switch sw3 have a plurality of first terminals, and the first terminals are connected to the voltage input terminal to receive the input voltage Vin. One end of the first capacitor cs1 and the second capacitor cs2 is connected to the negative input terminal of the operational amplifier 701, and the other end of the first capacitor cs1 and the second capacitor cs2 is connected to the second switch sw2 and the third switch sw3. The second terminal; the fourth switch sw4 is coupled to the second terminal of the second switch sw2 and the output of the operational amplifier 701. One end of the fifth switch sw5 is connected to the second end of the third switch sw3, and the other end of the fifth switch sw5 is connected to the reference voltage input terminal Vdac.

The second switch sw2 and the third switch sw3 are controlled by the first clock signal ck1, the fourth switch sw4 and the fifth switch sw5 are controlled by the third clock signal ck3, and the first switch sw1 is controlled by the second clock signal Controlled by ck2. The rising edge of the first clock signal ck1 and the second clock signal ck2 are aligned, and the falling edge of the third clock signal ck3 is aligned with the rising edge of the first clock signal ck1 and the second clock signal ck2. Further, the high-level period of the first clock signal ck1 is longer than the high-level period of the second clock signal ck2.

With such an architecture and clock signal timing, when the first class code is equal to 2'b00 or 2'b11, the output voltage Vout1 from the first-stage circuit directly adds or subtracts the reference voltage.

Please refer to FIG. 8, which is a circuit diagram of a second stage circuit according to an embodiment of the present invention. The second-stage circuit mainly includes an operational amplifier 801, a first switch sw1, a first switch sw2, a third switch sw3, a fourth switch sw4, a fifth switch sw5, a sixth switch sw6, a seventh switch sw7, and a first capacitor cs1. The first capacitor cs2 and the third capacitor cs3. The operational amplifier 801 has a positive input terminal +, a negative input terminal -, and an output terminal, wherein the positive input terminal + is connected to a ground terminal, and the third capacitor cs3 is connected to the negative input terminal - and the output terminal of the operational amplifier 801 between.

The first switch sw1 is connected between the negative input terminal and the ground terminal; the second switch sw2 and the third switch sw3 have a plurality of first terminals, and the first terminals are connected to the voltage input terminal to receive the input voltage Vout1. One end of the first capacitor cs1 and the second capacitor cs2 is connected to the negative input terminal of the operational amplifier 801, and the other end of the first capacitor cs1 and the second capacitor cs2 is connected to the second switch sw2 and the third switch sw3. Second end point; fourth switch Sw4 is connected to the second end of the second switch sw2 and the first reference voltage terminal Vdac1. One end of the fifth switch sw5 is connected to the second end of the third switch sw3, and the other end of the fifth switch sw5 is connected to the second reference voltage input terminal Vdac2.

The second switch sw2 and the third switch sw3 are controlled by the first clock signal ck1, and the fourth switch sw4, the fifth switch sw5, and the seventh switch sw7 are controlled by the third clock signal ck3, the first switch sw1 The sixth switch is controlled by the first clock signal ck1. The rising edge of the first clock signal ck1 and the second clock signal ck2 are aligned, and the falling edge of the third clock signal ck3 is aligned with the rising edge of the first clock signal ck1 and the second clock signal ck2. Further, the high-level period of the first clock signal ck1 is longer than the high-level period of the second clock signal ck2.

With such an architecture and clock signal timing, when the combination of the second class code and the confirmation code (C21, C22, C23, C24) is equal to 4'b0000, 4'b1000, 4'b1110, or 4'b1111, The output voltage Vout2 from the second-stage circuit directly adds or subtracts the reference voltage.

Please refer to FIG. 9 , which is a flowchart of a method for correcting the offset voltage of a pipeline architecture analog-to-digital converter according to an embodiment of the present invention. The method first generates a first class code and a first output voltage based on the first input voltage (step 901) and generates a second class code based on the first output voltage (step 903). Next, a confirmation code is generated based on the first output voltage (step 905), and the first correction code is determined with reference to the first class code and the confirmation code (step 907).

Next, it is confirmed whether the first class code is different from the first correction code (step 909), and when the first class code is different from the first correction code, A correction code corrects the first class code (step 911) and adjusts the second output voltage of the second stage circuit with a positive reference voltage (+Vref) or a negative reference voltage (-Vref). For example, if the second output voltage is too high, the second output voltage is subtracted from the reference voltage to lower the second output voltage.

Specifically, the generation of the confirmation code is to compare the first output voltage with the positive reference voltage (+Vref) and the negative reference voltage (-Vref), as indicated by the table of FIG. 10 and the waveform of FIG. When the first output voltage is below -Vref and is out of the operating range (ie, point A in Fig. 11), if the class code and the output voltage are not corrected instantaneously, an error code will occur. In order to avoid the occurrence of an error code, an acknowledgment code (c21, c24) equal to 2'b00 and a first correction code (MSB1 LSB1) equal to 2'b00 or 2'b01 are generated instead of the erroneous first class code.

In other embodiments, when the first output voltage exceeds +Vref and is out of range (point B in FIG. 11), a confirmation code equal to 2'b11 (c21 c24) and equal to 2'b01 or 2' is generated. The first correction code of b10 (MSB1 LSB1).

Figure 12 is a diagram showing the truth value table representing the normal and error states of the pipeline architecture analog-to-digital converter in an embodiment of the present invention, and Figure 13 is a waveform diagram showing the output voltage of the class circuit in an embodiment of the present invention. In the embodiments illustrated in Figures 12 and 13, further consideration is given to the fact that the input voltage is substantially higher than the positive reference voltage or lower than the negative reference voltage. In these cases, the voltage is out of range and is not the cause. The offset voltage of the comparator. In Figure 13, the reason why points A, D, E, and H are out of range is because the original input voltage itself is very high. The pressure does not require special correction.

Therefore, when the combination of the first class code, the confirmation code, and the second class code is equal to 6'b001111, 6'b100000, 6'b101111, and 6'b110000, the first correction code (MSB2 LSB2) equal to 2'b01. Will be used to correct the first class code (c11 c12).

On the other hand, if it is found in step 909 that the first class code is identical to the first correction code, then the first class code will remain as it is (step 913). Further, the second correction code may also be determined with reference to the first class code, the second class code, and the correction code. When the second class code is different from the second correction code, the second correction is corrected with the second correction code. Code.

According to the above embodiment, the error class code and the out-of-range output voltage due to the comparator offset voltage can be pre-corrected, thereby preventing the occurrence of an error code while avoiding the output voltage out of range and reducing the analog digital conversion of the pipeline architecture. The probability of an error in the operation of the device.

The present invention has been disclosed in the above embodiments, and is not intended to limit the present invention. Any one of ordinary skill in the art to which the present invention pertains can be variously modified without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

101‧‧‧ class circuit

103‧‧‧Classical digital analog converter

105‧‧‧Sampling and holding circuit

107‧‧‧Digital Analog Converter

109‧‧‧Amplifier

111‧‧‧ Analog Digital Converter

113‧‧‧Sampling and Holding Amplifier

500‧‧‧ Pipeline architecture analog to digital conversion Converter

501‧‧‧ Code Correction Circuit

503‧‧‧First class circuit

505‧‧‧second class circuit

507‧‧‧ third class circuit

509‧‧‧Nth class circuit

511‧‧‧Confirm code generator

513‧‧‧Offset voltage correction circuit

519‧‧‧Decoding logic circuit

521‧‧‧Calibration Generator

601‧‧‧First comparator

603‧‧‧ third comparator

605‧‧‧fourth comparator

607‧‧‧Second comparator

609‧‧‧ fifth comparator

611‧‧‧ sixth comparator

701‧‧‧Operational Amplifier

801‧‧‧Operational Amplifier

901~913‧‧‧Steps

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The traditional pipeline architecture is analogous to digital converters.

3 and 4 are schematic diagrams showing the output voltage waveforms of the class circuits among the pipeline architecture analog-to-digital converters.

FIG. 5 is a block diagram showing a pipeline architecture analog-to-digital converter according to an embodiment of the present invention.

Figure 6 is a circuit diagram showing a confirmation code generator according to an embodiment of the present invention.

Figure 7 is a circuit diagram showing a first-stage circuit of an embodiment of the present invention.

Figure 8 is a circuit diagram showing a second-stage circuit of an embodiment of the present invention.

FIG. 9 is a flow chart showing a method for correcting the offset voltage of a pipeline architecture analog-to-digital converter according to an embodiment of the present invention.

FIG. 10 is a diagram showing a code truth table of a pipeline architecture analog-to-digital converter according to an embodiment of the present invention.

11 is a graph showing conversion characteristics of an input signal and an output signal of a pipeline architecture analog-to-digital converter according to an embodiment of the present invention.

Figure 12 is a diagram showing a truth table representing the pipeline architecture analog-to-digital converter code in an embodiment of the present invention.

Fig. 13 is a view showing the waveform of the output voltage of the class circuit in an embodiment of the present invention.

500‧‧‧Pipeline Analog Analog Digital Converter

501‧‧‧ Code Correction Circuit

503‧‧‧First class circuit

505‧‧‧second class circuit

507‧‧‧ third class circuit

509‧‧‧Nth class circuit

511‧‧‧Confirm code generator

513‧‧‧Offset voltage correction circuit

519‧‧‧Decoding logic circuit

521‧‧‧Calibration Generator

Claims (14)

An offset voltage influence correction method for a pipeline architecture analog to digital converter, the method comprising: generating a first class code and a first output voltage according to a first input voltage; generating a second class according to the first output voltage a code; generating a confirmation code according to the first output voltage; determining a first correction code with reference to the first class code and the confirmation code; and when the first class code is different from the first correction code, The first correction code corrects the first class code. The offset voltage affecting correction method of the pipeline architecture analog digital converter according to claim 1, further comprising: when the first class code is different from the first calibration code, a positive reference voltage or a negative reference voltage And adjusting a second output voltage of one of the second class circuits. The offset voltage affecting correction method of the pipeline architecture analog digital converter according to claim 1, wherein the first output voltage is compared with a first positive reference voltage and a first negative reference voltage to generate the acknowledgement Code. The pipeline architecture analogy of the digital converter as described in claim 3 The shift voltage influence correction method refers to the first class code stored in a lookup table and the confirmation code to determine the first correction code. The offset voltage influence correction method of the pipeline architecture analog digital converter according to claim 1, wherein when the combination of the first class code and the confirmation code corresponds to 4'b1000, the first is equal to 2'b00 The correction code corrects the first class code. The offset voltage influence correction method of the pipeline architecture analog digital converter according to claim 1, wherein when the combination of the first class code and the confirmation code corresponds to 4'b0011, the first is equal to 2'b01 The correction code corrects the first class code. The offset voltage influence correction method of the pipeline architecture analog digital converter according to claim 1, wherein when the combination of the first class code and the confirmation code corresponds to 4'b1011, the first is equal to 2'b10 The correction code corrects the first class code. The offset voltage influence correction method of the pipeline architecture analog digital converter according to claim 1, further comprising: determining a second correction code by referring to the first class code, the second class code, and the confirmation code; When the second class code is different from the second correction code, the second class code is corrected with the second correction code. A pipeline architecture analog-to-digital converter includes: a confirmation code generator for generating a confirmation code according to a first output voltage output by one of the first-stage circuits of the pipeline architecture analog digital converter; a code correction circuit, Receiving, by the first class circuit, a second class circuit, and the confirmation code generator, a first class code, a second class code, and the confirmation code, the code correction circuit also refers to the confirmation a code, the first class code, and the second class code to correct the wrong first class code and the second class code; and an offset voltage correction circuit to correlate the second class code with the confirmation code, Adjusting the magnitude of the output voltage of one of the second-stage circuits. The pipeline architecture analog digital converter according to claim 9, wherein the confirmation code generator comprises: a first comparator having a first input end and a second input end, wherein the first input end is connected to an input Receiving an input voltage, the second input is connected to a positive reference voltage input to receive a positive reference voltage, and a second comparator having a third input and a fourth input, the first The three input terminal is connected to the input port to receive the input voltage, and the fourth input terminal is connected to a negative reference voltage terminal to receive a negative reference voltage. The pipeline architecture analog digital converter of claim 9, wherein the first stage circuit comprises: an operational amplifier having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is coupled to a grounding terminal; a first switch connected between the negative input terminal and the grounding terminal; a second switch and a third switch having a plurality of first terminals, the first terminals being connected to a voltage The input terminal receives an input voltage; a first capacitor and a second capacitor, wherein the first capacitor and one end of the second capacitor are connected to the negative input terminal of the operational amplifier, the first capacitor and the second capacitor The other end of the capacitor is connected to the second switch and the second end of the third switch; a fourth switch is connected to the second end of the second switch and the output of the operational amplifier; And a fifth switch, one end of the fifth switch is connected to the second end of the third switch, and the other end of the fifth switch is connected to a reference voltage input end. The pipeline architecture analog digital converter according to claim 11, wherein the second switch and the third open relationship are controlled by a first clock signal, and the fourth switch and the fifth switch are controlled by a third clock. Controlled by the signal, the first switch is controlled by a second clock signal. The pipeline architecture analog digital converter according to claim 12, wherein the first clock signal and the rising edge of the second clock signal are aligned, and one of the third clock signals is aligned with the first edge. Clock signal And the rising edges of the second clock signal. The pipeline architecture analog digital converter according to claim 13, wherein the high level period of the first clock signal is longer than the high level period of the third clock signal.