CN103545287A - Semiconductor structure - Google Patents
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- CN103545287A CN103545287A CN201210238365.9A CN201210238365A CN103545287A CN 103545287 A CN103545287 A CN 103545287A CN 201210238365 A CN201210238365 A CN 201210238365A CN 103545287 A CN103545287 A CN 103545287A
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- rete
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Abstract
The invention discloses a semiconductor structure which comprises a first capacitor and a second capacitor. The first capacitor comprises a plurality of first units, and each first unit comprises a plurality of first finger electrodes. The second capacitor comprises a plurality of second units, and each second unit comprises a plurality of second finger electrodes. The first units and the second units are arranged in a staggered mode to form an array. The semiconductor structure further comprises a plurality of first connection lines and second connection lines which are parallel with each other. The first connection lines are electrically connected with the first finger electrodes, and the first finger electrodes and the adjacent first connection lines form straight lines. The second connection lines are electrically connected with the second finger electrodes, and the second electrodes and the adjacent second lines form straight lines.
Description
Technical field
The present invention relates to a kind of semiconductor structure, especially relate to a kind of semiconductor capacitance structure that electric capacity does not mate (mismatch) that improves.
Background technology
In modern integrated circuit, capacitor is one of main circuit element.For instance, industry comprises metal-oxide layer-metal (metal-oxide-metal, MOM) capacitor and metal-insulator-metal (metal-insulator-metal, MIM) capacitor etc. for the capacitor of logic simulation element.The capacitance of capacitor is quite responsive to manufacture craft and structural design, so the electric capacity of each capacitor is often because of the unmatched problem of electric capacity, has influence on the accuracy of digital signal afterwards.
Therefore, industry still needs a kind of capacitor arrangement that can effectively improve the problems such as electric capacity does not mate.
Summary of the invention
For addressing the above problem, the invention provides a kind of semiconductor structure, this semiconductor structure includes one first electric capacity, is arranged at one first rete, and this first electric capacity includes a plurality of first modules, and respectively this first module also comprises a plurality of the first finger electrodes.This semiconductor structure also includes one second electric capacity, be arranged at this first rete, this second electric capacity includes a plurality of second units, and these second units and these first modules are staggered and form an array, and respectively this second unit also comprises a plurality of the second finger electrodes.This semiconductor structure also includes a plurality of the first connecting line and the second connecting lines that are arranged at this first rete, and these first connecting lines and these the second connecting lines are parallel to each other.These first connecting lines are electrically connected to these the first finger electrodes, and these first finger electrodes and adjacent these the first connecting line shapes thereof are in line; And these second connecting lines are electrically connected to these the second finger electrodes, and these second finger electrodes and adjacent these the second connecting line shapes thereof are in line.
The present invention also provides a kind of semiconductor structure, and this semiconductor structure includes a plurality of the first finger electrode of one first rete and one second rete, a plurality of the second finger electrode of this first rete and this second rete, a plurality of common finger electrode of this first rete and this second rete, a plurality of the first connecting line and a plurality of the second connecting lines that are arranged in this second rete that are arranged in this first rete of being arranged at of being arranged at of being arranged at.The staggered fork of these common finger electrodes and these the first finger electrodes closes to be arranged to form a plurality of first modules in this first rete and this second rete, and these common finger electrodes close arrangement to form a plurality of second units in this first rete and this second rete with staggered the pitching of these the second finger electrodes.These first connecting lines are in order to be electrically connected to two the first finger electrodes the most close in these first modules; And these second connecting lines to be to be electrically connected to two the second finger electrodes the most close in these second units, and these first connecting lines and these the second connecting lines parallel to each other.
According to semiconductor structure provided by the present invention, in order to connect the connecting line of finger electrode, be all and be arranged in parallel each other, therefore in not affecting the unmatched prerequisite of electric capacity, more promote the reliability of capacitor.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the schematic diagram of the first preferred embodiment of semiconductor structure provided by the present invention;
Fig. 4 is the schematic diagram of one second preferred embodiment of semiconductor structure provided by the present invention;
Fig. 5 to Fig. 7 is the schematic diagram of one the 3rd preferred embodiment of semiconductor element provided by the present invention;
Fig. 8 is a schematic diagram of the 4th preferred embodiment of semiconductor element provided by the present invention;
Fig. 9 is the schematic diagram of the 5th preferred embodiment of semiconductor structure provided by the present invention;
Figure 10 is the schematic diagram of one the 6th preferred embodiment of semiconductor element provided by the present invention;
Figure 11 is the schematic diagram of one the 7th preferred embodiment of semiconductor element provided by the present invention;
Figure 12 and Figure 13 are the schematic diagram of one the 8th preferred embodiment of semiconductor element provided by the present invention.
Main element symbol description
10,14 first retes
20,24 second retes
12 retes
30,32 guard rings
34 connectors
100,300,700 first modules
110,310,710 first finger electrodes
112,312,712 first electrodes
120 the 3rd finger electrodes
122 third electrodes
130,330,730 first connecting lines
132 the 3rd connecting lines
200,400,800 second units
210,410,810 second finger electrodes
212,412,812 second electrodes
220 the 4th finger electrodes
222 the 4th electrodes
230,430,830 second connecting lines
232 the 4th connecting lines
500,900 common finger electrodes
714 first interlayer connectors
814 second interlayer connectors
914 the 3rd interlayer connectors
D
1, d
2spacing
Embodiment
Refer to Fig. 1 to Fig. 3, the schematic diagram of the first preferred embodiment that Fig. 1 to Fig. 3 is semiconductor structure provided by the present invention.As shown in Figure 1, the first preferred embodiment provides one first capacitor C
1with one second capacitor C
2, the first capacitor C
1comprise a plurality of first modules (unit) 100, and the second capacitor C
2comprise a plurality of second units 200.In this preferred embodiment, first module 100 is identical with the quantity of second unit 200, that is to say that first module 100 and the quantity of second unit 200 are 1 than ratio.As shown in Figure 1, each first module 100 comprises respectively a plurality of the first finger electrodes 110 and a plurality of the 3rd finger electrodes 120, and the first finger electrode 110 closes arrangement and forms this first module 100 with the staggered fork of the 3rd finger electrode 120.In like manner, each second unit 200 comprises respectively a plurality of the second finger electrodes 210 and a plurality of the 4th finger electrodes 220, and the second finger electrode 210 closes arrangement and forms this second unit 200 with the staggered fork of the 4th finger electrode 220.Other the first finger electrode 110 is electrically connected to each other and is a comb shape by one first electrode 112, in like manner the 3rd finger electrode 120 by a third electrode 122 be electrically connected to each other form a comb shape, the second finger electrode 210 by one second electrode 212, be electrically connected to each other form a comb shape, the 4th finger electrode 220 is electrically connected to each other and is formed a comb shape by one the 4th electrode 222.First module 100 is arranged in the first rete 10 and the second rete 20 with second unit 200, and in other words, the first finger electrode 110 and the 3rd finger electrode 120 are arranged in the first rete 10 and the second rete 20; In like manner the second finger electrode 210 and the 4th finger electrode 220 are also arranged in the first rete 10 and the second rete 20, and the first rete 10 and the second rete 20 can be for example the first retes (M1) and the second rete (M2) that is positioned at back segment metal interconnecting layer, but are not limited to this.
Please continue to refer to Fig. 1.At the first rete 10, there is identical arrangement position with the first module 100 in the second rete 20 with second unit 200.It should be noted that in the first rete 10 and the second rete 20, first module 100 is all staggered and forms an array with second unit 200.As shown in Figure 1, first module 100 has multirow (column) and multiple row (row) with the array that second unit 200 forms, and the central point of first module 100 and the central point of second unit 200 that are arranged at same row form a broken line as shown in Figure 1.Moreover, the central point of first module 100 and the central point of second unit 200 that are arranged at same a line also form a broken line as shown in Figure 1.The first finger electrode 110 of the first module in adjacent column 100 puts in order contrary with the 3rd finger electrode 120 in addition.For instance, in the first module 100 of odd number row, putting in order of the first finger electrode 110 and the 3rd finger electrode 120 is that the 3rd finger electrode 120 is first, and the first finger electrode 110 is rear; Yet in the first module 100 of even column, putting in order of the first finger electrode 110 and the 3rd finger electrode 120 is that the first finger electrode 110 is first, and the 3rd finger electrode 120 is rear.In like manner the second finger electrode 210 of the second unit in adjacent column 200 puts in order also contrary with the 4th finger electrode 220.For instance, in the second unit 200 of odd number row, putting in order of the second finger electrode 210 and the 4th finger electrode 220 is that the second finger electrode 210 is first, and the 4th finger electrode 220 is rear; Yet in the second unit 200 of even column, putting in order of the second finger electrode 210 and the 4th finger electrode 220 is that the 4th finger electrode 220 is first, and the second finger electrode 210 is rear.
Refer to Fig. 2.The semiconductor structure that this preferred embodiment provides also comprises a plurality of the first connecting lines 130, be arranged at the first rete 10, the first connecting line 130 is electrically connected to the first finger electrode 110, that is to say, the first finger electrode 110 in the first rete 10 is all electrically connected by the first electrode 112 and the first connecting line 130.The first finger electrode 110 and adjacent the first connecting line 130 thereof are parallel, and shape in line more as shown in Figure 2.It should be noted that the first connecting line 130 is electrically connected to the first module of adjacent column 100 by connecting the first finger electrode 110, and the first module 100 of adjacent column is arranged in alternately the first connecting line 130 both sides as alternate leaf.In addition the semiconductor structure that this preferred embodiment provides also comprises a plurality of the second connecting lines 230, be arranged at the first rete 10, the second connecting line 230 is electrically connected to the second finger electrode 210, that is to say, the second finger electrode 210 in the first rete 10 is all electrically connected by the second electrode 212 and the second connecting line 230.The second finger electrode 210 and adjacent the second connecting line 230 thereof are parallel, and shape in line more as shown in Figure 2.The second connecting line 230 is electrically connected to the second unit of adjacent column 200 by connecting the second finger electrode 210, and the second unit 200 of adjacent column is arranged in alternately the second connecting line 230 both sides as alternate leaf.The more important thing is, the first connecting line 130 and the second connecting line 230 are parallel to each other as shown in Figure 2.
Refer to Fig. 3.The semiconductor structure that this preferred embodiment provides in addition also comprises a plurality of the 3rd connecting lines 132, be arranged at the second rete 20, the 3rd connecting line 132 is vertical with the 3rd finger electrode 120, and by the 3rd finger electrode 120 of third electrode 122 electrical connection adjacent lines, and the first module 100 of adjacent lines is arranged in alternately the 3rd connecting line 132 both sides as alternate leaf.The 3rd finger electrode 120 in the second rete 20 is all electrically connected by third electrode 122 and the 3rd connecting line 132.In addition the semiconductor structure that this preferred embodiment provides also comprises a plurality of the 4th connecting lines 232, be arranged at the second rete 20, the 4th connecting line 232 is also vertical with the 4th finger electrode 220, and by the 4th finger electrode 220 of the 4th electrode 222 electrical connection adjacent lines, and the second unit 200 of adjacent lines is arranged in alternately the 4th connecting line 232 both sides as alternate leaf.The 4th finger electrode 220 in the second rete 20 is all electrically connected by the 4th electrode 222 and the 4th connecting line 232.As shown in Figure 3, the 3rd connecting line 132 and the 4th connecting line 232 are parallel to each other.
The semiconductor structure providing according to this first preferred embodiment, in order to be electrically connected to the connecting line of same capacitance unit, be all parallel or perpendicular to finger electrode, and be different from prior art, not parallel or the out of plumb of connecting line and finger electrode, even have approximately 45 degree (°) arrangement mode of angle.Therefore, in prior art, because connecting line and finger electrode is not parallel or off plumb arrangement mode causes the disappearance on electric capacity layout patterns to provide by this preferred embodiment semiconductor structure improve.
In addition, the semiconductor structure that the first preferred embodiment provides has four connection end points (terminal) (not shown), for example, be positioned at the positive end points C of the first electric capacity of the first rete 10
1+ with the positive end points C of the second electric capacity
2+, with the first electrode negative terminal C that is positioned at the second rete 20
1-with the second electric capacity negative terminal C
2-.As previously mentioned, the first finger electrode 110 is all electrically connected, and is electrically connected to the positive end points C of the first electric capacity
1+.In like manner the second finger electrode 210 is all electrically connected, and is electrically connected to the positive end points C of the second electric capacity
2+; The 3rd finger electrode 120 is all electrically connected, and is electrically connected to the first electrode negative terminal C
1-; The 4th finger electrode 220 is all electrically connected, and is electrically connected to the second electric capacity negative terminal C
2-.
Refer to Fig. 4, the schematic diagram of one second preferred embodiment that Fig. 4 is semiconductor structure provided by the present invention.It should be noted that element identical with the first preferred embodiment in the second preferred embodiment is with identical symbol description, and the second preferred embodiment and the first preferred embodiment something in common repeat no more.In addition, Fig. 4 has illustrated the first capacitor C that is arranged at the first rete 10 and the second rete 20 simultaneously
1with the second capacitor C
2.In the first preferred embodiment, the spacing d of first module 100 and the second connecting line 230 and the 4th connecting line 232
1be less than or equal to 0.6 micron (micrometer, μ m); And the spacing d of second unit 200 and the first connecting line 130 and the 3rd connecting line 132
2also be less than or equal to 0.6 μ m.As shown in Figure 4, the semiconductor structure difference that the second preferred embodiment provides is: the spacing d of first module 100 and the second connecting line 230 and the 4th connecting line 232
1between m to 0.8 micron of μ m of 0.6 μ; The spacing d of second unit 200 and the first connecting line 130 and the 3rd connecting line 132 in like manner
2also between 0.6 μ m to 0.8 μ m.In other words, each capacitor cell 100/200 to the spacing of the connecting line of different capacitor cell 200/100 can be exaggerated.
The semiconductor structure providing according to this second preferred embodiment, by increasing capacitor cell 100/200 to the spacing d of the connecting line of different capacitor cell 200/100
1, d
2, reduce the coupling capacitance (coupling capacitance) between different capacitor cells 100/200, and for reducing capacitive cross-talk (capacitive crosstalk).
Refer to Fig. 5 to Fig. 7, the schematic diagram of one the 3rd preferred embodiment that Fig. 5 to Fig. 7 is semiconductor element provided by the present invention.It should be noted that element identical with aforementioned preferred embodiment in the 3rd preferred embodiment is with identical symbol description, and the 3rd preferred embodiment and aforementioned preferred embodiment something in common repeat no more.In addition should be noted, in the 3rd preferred embodiment, each capacitor cell 100/200 to the spacing of the connecting line of different capacitor cell 200/100 can, as described in the second preferred embodiment, be amplified to 0.6 μ m to 0.8 μ m.The 3rd preferred embodiment and the second preferred embodiment difference are: in the first rete 10, this preferred embodiment also arranges a plurality of guard rings (guarding ring) 30 between adjacent first module 100 and second unit 200 as shown in Figure 5 in each row; In this external second rete 20, also optionally also in every a line, between adjacent first module 100 and second unit 200, a plurality of guard rings 32 are set as shown in Figure 6.And as shown in Fig. 5 and Fig. 6, in the first rete 10, the bearing of trend of guard ring 30 is identical with the bearing of trend of the first connecting line 130 and the second connecting line 230; And the bearing of trend of guard ring 32 is identical with the bearing of trend of the 3rd connecting line 132 and the 4th connecting line 232 in the second rete 20.In addition the guard ring 30/32 in different retes 10/20 can be electrically connected to by connector 34, and as shown in Figure 7, by connector 34 ground connection (grounding).Therefore different capacitor cells 100/200 shield by guard ring 30/32, and can more reduce coupling capacitance.
The semiconductor structure providing according to this 3rd preferred embodiment, by increasing capacitor cell 100/200 to the spacing d of the connecting line of different capacitor cell 200/100
1/ d
2, and by the setting of guard ring 30/32, more reduce the coupling capacitance between different capacitor cells 100/200, and for reducing capacitive cross-talk.
Refer to Fig. 8, a schematic diagram of the 4th preferred embodiment that Fig. 8 is semiconductor structure provided by the present invention.It should be noted that element identical with aforementioned preferred embodiment in the 4th preferred embodiment is with identical symbol description.In addition, the semiconductor structure shown in Fig. 8 is by the first rete 10 and superimposed rear the obtained schematic diagram of the second rete 20.As shown in Figure 8, this preferred embodiment also provides one first capacitor C
1with one second capacitor C
2, the first capacitor C
1comprise a plurality of first modules 100, and the second capacitor C
2comprise a plurality of second units 200.
As shown in Figure 8, each first module 100 comprises respectively a plurality of the first finger electrodes 110 and a plurality of the 3rd finger electrodes 120, and the first finger electrode 110 closes arrangement and forms this first module 100 with the staggered fork of the 3rd finger electrode 120.In like manner, each second unit 200 comprises respectively a plurality of the second finger electrodes 210 and a plurality of the 4th finger electrodes 220, and the second finger electrode 210 closes arrangement and forms this second unit 200 with the staggered fork of the 4th finger electrode 220.Other the first finger electrode 110 is electrically connected to each other and is a comb shape by one first electrode 112, in like manner the 3rd finger electrode 120 by a third electrode 122 be electrically connected to each other form a comb shape, the second finger electrode 210 by one second electrode 212, be electrically connected to each other form a comb shape, the 4th finger electrode 220 is electrically connected to each other and is formed a comb shape by one the 4th electrode 222.
Please continue to refer to Fig. 8.The semiconductor structure that this preferred embodiment provides also comprises a plurality of the first connecting lines 130, be arranged at the first rete 10, the first connecting line 130 is electrically connected to the first finger electrodes 110, and the first finger electrode 110 and adjacent the first connecting line 130 parallel, and shape is in line as shown in Figure 8.In addition the semiconductor structure that this preferred embodiment provides also comprises a plurality of the second connecting lines 230, be arranged at the first rete 10, the second connecting line 230 is electrically connected to the second finger electrode 210, and the second finger electrode 210 and adjacent the second connecting line 230 thereof are parallel, and also shape is in line as shown in Figure 8.The more important thing is, the first connecting line 130 and the second connecting line 230 are parallel to each other as shown in Figure 8.
Please still consult Fig. 8.The semiconductor structure that this preferred embodiment provides in addition also comprises a plurality of the 3rd connecting lines 132, is arranged at the second rete 20, the three connecting lines 132 and is electrically connected to the 3rd finger electrode 120 by third electrode 122.In this preferred embodiment, the 3rd connecting line 132 is vertical with the 3rd finger electrode 120.In addition the semiconductor structure that this preferred embodiment provides also comprises a plurality of the 4th connecting lines 232, be arranged at the second rete 20, the 4th connecting line 232 is electrically connected to the 4th finger electrode 220 by the 4th electrode 222, and the 4th connecting line 232 is also vertical with the 4th finger electrode 220.And as shown in Figure 8, the 3rd connecting line 132 and the 4th connecting line 232 are parallel to each other.
It should be noted that in this preferred embodiment, first module 100 is different from the quantity of second unit 200, that is to say that first module 100 and the quantity ratio of second unit 200 have a ratio, and this ratio is greater than 1.As shown in Figure 8, the first module 100 in this preferred embodiment is 3 with the quantity of second unit 200 than ratio, but first module 100 also can be 5 or 7 with the quantity of second unit 200 than ratio, and is not limited to this.
In addition, this preferred embodiment still can increase capacitor cell 100/200 to the spacing d of the connecting line of different capacitor cell 200/100
1, d
2(not shown), and the setting of guard ring 30/32, reduce the coupling capacitance between different capacitor cells 100/200 more, and for reducing capacitive cross-talk.
The semiconductor structure providing according to this 4th preferred embodiment, can, by adjusting the quantity of first module 100 and second unit 200, make the first capacitor C
1with the second capacitor C
2there is different capacitances.In other words, the present invention can be obtained and be had flexible capacitance ratio by different coiling designs, and is more of value to the different electric capacity demand of integrated circuit.
Refer to Fig. 9, the schematic diagram of the 5th preferred embodiment that Fig. 9 is semiconductor structure provided by the present invention.As shown in Figure 9.The 5th preferred embodiment provides one first capacitor C
1with one second capacitor C
2, the first capacitor C
1comprise a plurality of first modules 300, and the second capacitor C
2comprise a plurality of second units 400.In this preferred embodiment, first module 300 is identical with the quantity of second unit 400, that is to say that first module 300 and the quantity of second unit 400 are 1 than ratio.As shown in Figure 9, each first module 300 comprises respectively a plurality of the first finger electrodes 310, and each second unit 400 comprises a plurality of the second finger electrodes 410.Other the first finger electrode 310 is electrically connected to each other and is a comb shape by one first electrode 312, and in like manner the second finger electrode 410 is electrically connected to each other and is formed a comb shape by one second electrode 412.First module 300 is arranged in one first rete 12 with second unit 400, and in other words, the first finger electrode 310 and the second finger electrode 410 are arranged in the first rete 12.It should be noted that this preferred embodiment also comprises a plurality of common finger electrodes 500, be arranged in the first rete 12, and common finger electrode 500 has a herringbone form.As shown in Figure 9, common finger electrode 500 and the staggered fork of the first finger electrode 310 close and arrange to form these first modules 300; In like manner common finger electrode 500 also closes and arranges to form these second units 400 with the staggered fork of the second finger electrode 410.Please continue to refer to Fig. 9.First module 300 in the first rete 12 is all staggered and forms an array with second unit 400.As shown in Figure 9, first module 300 has multirow and multiple row with the array that second unit 400 forms, and the central point of first module 300 and the central point of second unit 400 that are arranged at same row form a broken line.
Please still consult Fig. 9.The semiconductor structure that this preferred embodiment provides also comprises a plurality of the first connecting lines 330, be arranged at the first rete 12, and the first connecting line 330 is electrically connected to the first finger electrode 310, that is to say, the first finger electrode 310 is all electrically connected by the first electrode 312 and the first connecting line 330.The first finger electrode 310 and adjacent the first connecting line 330 thereof are parallel, and shape in line more as shown in Figure 9.It should be noted that the first connecting line 330 is electrically connected to the first module of same row 300 by connecting the first finger electrode 310.In addition the semiconductor structure that this preferred embodiment provides also comprises a plurality of the second connecting lines 430, be arranged at the first rete 12, and the second connecting line 430 is electrically connected to the second finger electrode 410, that is to say, the second finger electrode 410 is all electrically connected by the second electrode 412 and the second connecting line 430.The second finger electrode 410 and adjacent the second connecting line 430 thereof are parallel, and shape in line more as shown in Figure 9.The second connecting line 430 is electrically connected to the second unit of same row 400 by connecting the second finger electrode 410.The more important thing is, the first connecting line 330 and the second connecting line 430 are parallel to each other as shown in Figure 9.
The semiconductor structure providing according to this preferred embodiment, can be carried out up in single rete 12 originally needing two-layer electrode to simplify by the setting of common finger electrode, therefore more can letter economize manufacture craft.Yet be familiar with the personage Ying Zhi of this technology, the semiconductor element that this preferred embodiment provides can be made in respectively in two-layer rete according to product demand, and by interlayer connector (not shown) being set in the axis at the first electrode 412 and the second electrode 512 and the common finger electrode 500 of herring-bone form, in order to be electrically connected to the first module 300 and second unit 400 of different retes, for completing the first capacitor C
1with the second capacitor C
2making.
In addition, the semiconductor structure that the 5th preferred embodiment provides has three connection end point (not shown), for example, be positioned at the positive end points C of the first electric capacity of rete 12
1+, the positive end points C of the second electric capacity
2+ and shared negative terminal C-.As previously mentioned, the first finger electrode 310 is all electrically connected, and is electrically connected to the positive end points C of the first electric capacity
1+.In like manner the second finger electrode 410 is all electrically connected, and is electrically connected to the positive end points C of the second electric capacity
2+; Share finger electrode 500 and be all electrically connected, and be electrically connected to common pole negative terminal C-.
Refer in addition Figure 10 and Figure 11, the schematic diagram of one the 6th preferred embodiment that Figure 10 is semiconductor element provided by the present invention, Figure 11 is the schematic diagram of one the 7th preferred embodiment of semiconductor element provided by the present invention.In addition, can consult the 6th preferred embodiment and the 7th preferred embodiment, the difference disclosing more to understand the 6th preferred embodiment and the 7th preferred embodiment simultaneously.Need in addition it should be noted that the 6th with element identical with the 5th preferred embodiment in the 7th preferred embodiment with identical symbol description, and the 6th and the 7th preferred embodiment and the 5th preferred embodiment something in common repeat no more.
The 6th preferred embodiment is with the 5th preferred embodiment difference: the first finger electrode 310 in the 5th preferred embodiment is electrically connected to and is into comb shape with the second electrode 412 by the first electrode 312 respectively with the second finger electrode 410; But the first finger electrode 310 in the 6th preferred embodiment is electrically connected to and is into herring-bone form with the second electrode 412 by the first electrode 312 respectively with the second finger electrode 410.And the first electrode 312 is for being electrically connected to the axis of each first finger electrode 310; In like manner the second electrode 412 is for connecting the axis of each second finger electrode 410.And between the first finger electrode 310 and the second finger electrode 410, be provided with the common finger electrode 500 of a plurality of herring-bone forms.In this preferred embodiment, the first finger electrode 310 is identical with the quantity of the second finger electrode 410, that is the first capacitor C
1with the second capacitor C
2capacitance ratio be 1.
Refer to Figure 11.Disclosed the 7th preferred embodiment of Figure 11 and the 6th preferred embodiment difference be, in the 7th preferred embodiment, the quantity of the first finger electrode 310 is different from the quantity of the second finger electrode 410.As shown in figure 11, in same a line, the quantity of the first finger electrode 310 and the second finger electrode 410 is than being 3:2; In other words, the ratio of the first finger electrode 310 and the second finger electrode 410 quantity ratios is greater than 1.
The semiconductor structure providing according to the 6th and the 7th preferred embodiment, can be carried out up in single rete 12 originally needing two-layer electrode to simplify by the setting of common finger electrode 500, therefore also can letter economize manufacture craft.In addition, also can, by adjusting the quantity of the first finger electrode 310 and the second finger electrode 410, make the first capacitor C
1with the second capacitor C
2there is different capacitances.In other words, the present invention can be obtained and be had flexible capacitance ratio by different coiling designs, and is more of value to the different electric capacity demand of integrated circuit.
Refer to Figure 12 and Figure 13, the schematic diagram of one the 8th preferred embodiment that Figure 12 and Figure 13 are semiconductor structure provided by the present invention.As shown in Figure 12 and Figure 13, the semiconductor structure that this preferred embodiment provides comprises a plurality of the first finger electrodes 710, a plurality of the second finger electrode 810 and a plurality of common finger electrode 900, is arranged at respectively one first rete 14 and one second rete 24.Other the first finger electrode 710 is electrically connected to each other and is a comb shape by one first electrode 712; In like manner the second finger electrode 810 is electrically connected to each other and is formed a comb shape by one second electrode 812.As shown in Figure 12 and Figure 13, common finger electrode 900 and the staggered fork of the first finger electrode 710 close arrangement, and in the first rete 14 and a plurality of first modules 700 of the interior formation of the second rete 24.In like manner common finger electrode 900 and the staggered fork of the second finger electrode 810 close arrangement, and in the first rete 14 and a plurality of second units 800 of the interior formation of the second rete 24.At the first rete 14, there is identical arrangement position with the first module 700 in the second rete 24 with second unit 800.It should be noted that in the first rete 14 and the second rete 24, first module 700 is all staggered and forms an array with second unit 800.For instance, no matter in this preferred embodiment in the first rete 14 or the second rete 24, first module 700 is all adjacent with second unit 800, therefore first module 700 can be considered oblique angle spread configuration.In like manner second unit 800 is all adjacent with first module 700, therefore second unit 800 can be considered oblique angle spread configuration.
In addition, this preferred embodiment also comprises a plurality of the first interlayer connectors 714, a plurality of the second interlayer connector 814 and a plurality of the 3rd interlayer connector 914(and is all only shown in Figure 13).The first interlayer connector 714 is in order to be electrically connected to the first finger electrode 710 in the first rete 14 and in the second rete 24, the second interlayer connector 814 in order to be electrically connected in the first rete 14 with the second rete 24 in the second finger electrode 810, the three interlayer connectors 914 in order to be electrically connected in the first rete 14 with the second rete 24 in common finger electrode 900.Be electrically connected to each other and form one first capacitor C with the first module 700 in the first rete 14 and in the second rete 24
1; And in the first rete 14 with the second rete 24 in second unit 800 be electrically connected to each other and form one second capacitor C
2.
Please continue to refer to Figure 12 and Figure 13.The semiconductor structure that this preferred embodiment provides also comprises a plurality of the first connecting lines 730, is arranged in the first rete 14, in order to be electrically connected to two the first finger electrodes 710 the most close in first module 700.The semiconductor structure that this preferred embodiment provides also comprises a plurality of the second connecting lines 830, is arranged in the second rete 24, in order to be electrically connected to two the second finger electrodes 810 the most close in second unit 800.It should be noted that the first connecting line 730 is perpendicular to each the first finger electrode 710; And the second connecting line 830 is perpendicular to each the second finger electrode 810.The more important thing is, the first connecting line 730 being arranged in the first rete 14 is parallel to each other with the second connecting line 830 being arranged in the second rete 24.
The semiconductor structure providing according to this preferred embodiment, in order to the connecting line that connects same capacitance unit perpendicular to finger electrode, and be different from prior art, the not parallel or out of plumb of connecting line and finger electrode, even have approximately 45 degree (°) arrangement mode of angle.Therefore, in prior art, because connecting line and finger electrode is not parallel or off plumb arrangement mode causes the disappearance on electric capacity layout patterns to provide by this preferred embodiment semiconductor structure improve.
According to semiconductor structure provided by the present invention, in order to connect the connecting line of finger electrode, be all and be arranged in parallel, and parallel with finger electrode or vertical, therefore can in not affecting the unmatched prerequisite of electric capacity, also promote the reliability of capacitor.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (20)
1. a semiconductor structure, includes:
The first electric capacity, is arranged at the first rete, and this first electric capacity includes a plurality of first modules, and respectively this first module also comprises a plurality of the first finger electrodes;
The second electric capacity, is arranged at this first rete, and this second electric capacity includes a plurality of second units, and the plurality of second unit and the plurality of first module are staggered and form an array, and respectively this second unit also comprises a plurality of the second finger electrodes;
A plurality of the first connecting lines, are arranged at this first rete, and the plurality of the first connecting line is electrically connected to the plurality of the first finger electrode, and the plurality of the first finger electrode and adjacent the plurality of the first connecting line shape thereof are in line; And
A plurality of the second connecting lines, are arranged at this first rete parallel with the plurality of the first connecting line, and the plurality of the second connecting line is electrically connected to the plurality of the second finger electrode, and the plurality of the second finger electrode and adjacent the plurality of the second connecting line shape thereof are in line.
2. semiconductor structure as claimed in claim 1, wherein this array comprises multirow and multiple row.
3. semiconductor structure as claimed in claim 2, the central point of the plurality of first module and the central point of the plurality of second unit that are wherein arranged at same row form a broken line.
4. semiconductor structure as claimed in claim 2, the central point of the plurality of first module and the central point of the plurality of second unit that are wherein arranged at same a line form a broken line.
5. semiconductor structure as claimed in claim 1, wherein respectively this first module also comprises a plurality of the 3rd finger electrodes, is arranged at this first rete, and the plurality of the 3rd finger electrode and the staggered fork of the plurality of the first finger electrode close and arrange to form this first module.
6. semiconductor structure as claimed in claim 5, wherein respectively this second unit also comprises a plurality of the 4th finger electrodes, is arranged at this first rete, and the plurality of the 4th finger electrode and the staggered fork of the plurality of the second finger electrode close and arrange to form this second unit.
7. semiconductor structure as claimed in claim 6, wherein the plurality of the first finger electrode and the plurality of the 3rd finger electrode are also formed at one second rete, and the plurality of the second finger electrode and the plurality of the 4th finger electrode are also formed at this second rete.
8. semiconductor structure as claimed in claim 7, also comprise a plurality of the 3rd connecting lines and a plurality of the 4th connecting line, be arranged at this second rete, the plurality of the 3rd connecting line is electrically connected to the plurality of the 3rd finger electrode, and the plurality of the 4th connecting line is electrically connected to the plurality of the 4th finger electrode.
9. semiconductor structure as claimed in claim 8, wherein the plurality of the 3rd connecting line and the plurality of the 4th connecting line are parallel to each other.
10. semiconductor structure as claimed in claim 1, the spacing of the wherein spacing of this first module and this second connecting line, and this second unit and this first connecting line is all between 0.6 micron to 0.8 micron.
11. semiconductor structures as claimed in claim 1, also comprise a plurality of guard rings, are arranged between the plurality of first module and the plurality of second unit.
12. semiconductor structures as claimed in claim 1, wherein the plurality of first module also comprises a quantity ratio with the plurality of second unit, and the ratio of this quantity ratio is more than or equal to 1.
13. semiconductor structures as claimed in claim 1, also comprise a plurality of common finger electrodes, are arranged in this first rete.
14. semiconductor structures as claimed in claim 13, wherein the staggered fork of the plurality of common finger electrode and the plurality of the first finger electrode closes and arranges to form the plurality of first module, and the plurality of common finger electrode closes arrangement to form the plurality of second unit with the staggered fork of the plurality of the second finger electrode.
15. semiconductor structures as claimed in claim 13, wherein the quantity of the plurality of the first finger electrode is identical with the quantity of this second finger electrode.
16. semiconductor structures as claimed in claim 13, wherein the quantity of the plurality of the first finger electrode is different from the quantity of this second finger electrode.
17. 1 kinds of semiconductor structures, include:
A plurality of the first finger electrodes, are arranged at one first rete and one second rete;
A plurality of the second finger electrodes, are arranged at this first rete and this second rete;
A plurality of common finger electrodes, be arranged at this first rete and this second rete, the staggered fork of the plurality of common finger electrode and the plurality of the first finger electrode closes to be arranged to form a plurality of first modules in this first rete and this second rete, and the plurality of common finger electrode closes arrangement to form a plurality of second units in this first rete and this second rete with staggered the pitching of the plurality of the second finger electrode;
A plurality of the first connecting lines, are arranged in this first rete, in order to be electrically connected to two the first finger electrodes the most close in the plurality of first module; And
A plurality of the second connecting lines, are arranged in this second rete, in order to be electrically connected to two the second finger electrodes the most close in the plurality of second unit, and the plurality of the first connecting line and the plurality of the second connecting line parallel to each other.
18. semiconductor structures as claimed in claim 17, wherein the plurality of first module and the plurality of second unit are staggered and form an array.
19. semiconductor structures as claimed in claim 17, wherein be arranged at this first rete and be electrically connected to form one first electric capacity with the plurality of first module of this second rete, be arranged at this first rete and be electrically connected to form one second electric capacity with the plurality of second unit of this second rete.
20. semiconductor structures as claimed in claim 17, also comprise:
A plurality of the first interlayer connectors, in order to be electrically connected in this first rete with this second rete in the plurality of the first finger electrode;
A plurality of the second interlayer connectors, in order to be electrically connected in this first rete with this second rete in the plurality of the second finger electrode; And
A plurality of the 3rd interlayer connectors, in order to be electrically connected in this first rete with this second rete in the plurality of common finger electrode.
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| CN101681721A (en) * | 2007-06-06 | 2010-03-24 | 高通股份有限公司 | Intertwined finger capacitors |
| CN101894795A (en) * | 2009-05-22 | 2010-11-24 | 新加坡格罗方德半导体制造私人有限公司 | Integrated circuit (IC) system and manufacture method thereof with hierarchical capacitor |
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| CN103545287B (en) | 2017-06-06 |
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