CN103543056B - A kind of failure ratio certain bits method prepared in perspective electron microscopic sample process - Google Patents
A kind of failure ratio certain bits method prepared in perspective electron microscopic sample process Download PDFInfo
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- CN103543056B CN103543056B CN201310526550.2A CN201310526550A CN103543056B CN 103543056 B CN103543056 B CN 103543056B CN 201310526550 A CN201310526550 A CN 201310526550A CN 103543056 B CN103543056 B CN 103543056B
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Abstract
The present invention relates to a kind of failure ratio certain bits method prepared in sample for use in transmitted electron microscope process, comprise the following steps: step one, sample is ground to the position of first layer metal line; Step 2, be positioned in focused ion beam board by the sample after ground, under ion beam, dig duck eye as mark in the alignment of metal target line, described metal target line is column address; Step 3, converts board to electron beam pattern, continues small area analysis scanning samples surface, count row address, near the target tungsten post of row address, precipitate platinum under high-pressure electronic bundle; Step 4, recalls to board under ion beam, sweeps and dig near platinum, and target tungsten post is exposed; Step 5, in the infall determination bit addresses of column address and row address, plates platinum protective seam with ion beam at bit addresses place.The present invention shortens number address time greatly, makes the searching of inefficacy bit addresses become convenient and swift, saves time in a large number and board resource, avoids the artificial destruction to chip itself.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of failure ratio certain bits method prepared in perspective electron microscopic sample process.
Background technology
In general, integrated circuit lost efficacy inevitable in development, production and use procedure, along with people's improving constantly product quality and reliability requirement, failure analysis work also seems more and more important, analyzed by chip failure, Integrated circuit designers can be helped to find not mating of the defect in design, technological parameter or the problem such as improper in designing and operating.For the analysis case of single bit fails, Product Failure Analysis slip-stick artist often needs this bit to cut out from chip and is put in transmission electron microscope and goes to observe its whether textural anomaly.So when using focused ion beam to prepare sample for use in transmitted electron microscope, how from one contain quickly and accurately target is found the chip of millions of same bit most important.Normal practice be first in the metal wire mileage of repetition in column to target column, then enlargement ratio small area analysis ion beam continues to sweep the metal wire dug up near target column and connects with the tungsten post exposing lower floor, thus draws bit row address.The time of digging swept by metal wire and multiplying power all needs very strictly to control, too small, tungsten post or overlong time can not be exposed and waste resource, excessively easily lower floor's tungsten post is dug up the scanning that will again replace, this step often causes the complexity of sample preparation to raise and waste of time.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of failure ratio certain bits method prepared in perspective electron microscopic sample process, compared to prior art, has saved the time, has decreased the damaged condition to sample.
The technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of failure ratio certain bits method prepared in perspective electron microscopic sample process, comprises the following steps:
Step one, is ground to the position of first layer metal line by sample;
Step 2, be positioned in focused ion beam board by the sample after ground, under ion beam, dig duck eye as mark in the alignment of metal target line, described metal target line is column address;
Step 3, converts board to electron beam pattern, continues small area analysis scanning samples surface, count row address under high-pressure electronic bundle, and the platinum that receiving electrode is small near the target tungsten post of row address;
Step 4, then board is recalled to under ion beam, sweep near platinum and dig, target tungsten post is exposed;
Step 5, in the infall determination bit addresses of column address and row address, plates platinum protective seam with ion beam at bit addresses place.
On the basis of technique scheme, the present invention can also do following improvement.
Further, the time of described step 3 precipitation platinum is 10 seconds.
Further, sweeping the time of digging in described step 4 is 25 seconds to 30 seconds.
The invention has the beneficial effects as follows: shorten number address time greatly, make the searching of inefficacy bit addresses become convenient and swift, substantial saving in time and board resource, avoid the artificial destruction to chip itself simultaneously.
Accompanying drawing explanation
Fig. 1 is the method flow diagram of a kind of failure ratio certain bits method prepared in perspective electron microscopic sample process of the present invention.
Embodiment
Be described principle of the present invention and feature below in conjunction with accompanying drawing, example, only for explaining the present invention, is not intended to limit scope of the present invention.
As shown in Figure 1, a kind of failure ratio certain bits method of having an X-rayed electron microscopic sample of the present invention, comprises the following steps:
Step one, is ground to the position of first layer metal line by sample;
Step 2, be positioned in focused ion beam board by the sample after ground, under ion beam, dig duck eye as mark in the alignment of metal target line, described metal target line is column address;
Step 3, converts board to electron beam pattern, continues small area analysis scanning samples surface, count row address under high-pressure electronic bundle, and the platinum that receiving electrode is small near the target tungsten post of row address;
Step 4, then board is recalled to under ion beam, sweep near platinum and dig, target tungsten post is exposed;
Step 5, in the infall determination bit addresses of column address and row address, plates platinum protective seam with ion beam at bit addresses place.
Described step 3 is carried out to when more than 200,000 times at Nonlinear magnify, and the time of described step 3 precipitation platinum is 10 seconds, and sweeping the time of digging in described step 4 is 25 seconds to 30 seconds.First chip front side is ground to first layer metal circuit (in order to ensure the primitiveness of address bit, the metallic circuit on its top necessarily keeps complete); Put into focused ion beam and carry out two-beam and align, first under ion beam in the metal wire mileage of repetition in column to metal target line, this is the column address at bit place, then the metal wire aimed at the mark near arranging, image is amplified to more than 200,000 times again and continues small area analysis ion-beam scanning, such metal wire can be swept by ion beam the tungsten post articulamentum diging up to expose lower floor, can draw the place of bit row address according to tungsten post number, is exactly desired bit addresses in the point of crossing of row and column.Sweep in whole flow process that to dig metal wire one step very crucial, because sweep time and multiplying power all need appropriate control, too small, tungsten post or overlong time can not be exposed and waste resource, excessively easily lower floor's tungsten post is dug up the scanning that will again replace, this just causes the complexity of sample preparation to raise and waste of time.
Innovation of the present invention is to shorten number address time greatly, and step 3 and 4 All Times probably only need 2 minutes, and relative to old technology it can 95% minimizing to the destructiveness of sample.Make the searching of inefficacy bit addresses become convenient and swift, substantial saving in time and board resource, avoid the artificial destruction to chip itself simultaneously.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. prepare the failure ratio certain bits method in perspective electron microscopic sample process, it is characterized in that, comprise the following steps:
Step one, is ground to the position of first layer metal line by sample;
Step 2, be positioned in focused ion beam board by the sample after ground, under ion beam, dig duck eye as mark in the alignment of metal target line, described metal target line is column address;
Step 3, converts board to electron beam pattern, continues small area analysis scanning samples surface, count row address, and precipitate platinum near the target tungsten post of row address under high-pressure electronic bundle;
Step 4, then board is recalled to under ion beam, sweep near platinum and dig, target tungsten post is exposed;
Step 5, in the infall determination bit addresses of column address and row address, plates platinum protective seam with ion beam at bit addresses place.
2. a kind of failure ratio certain bits method prepared in perspective electron microscopic sample process according to claim 1, is characterized in that, the time of described step 3 precipitation platinum is 10 seconds.
3. a kind of failure ratio certain bits method prepared in perspective electron microscopic sample process according to claim 1, it is characterized in that, sweeping the time of digging in described step 4 is 25 seconds to 30 seconds.
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105136539B (en) * | 2015-08-26 | 2019-05-03 | 上海华力微电子有限公司 | A method of preparing TEM chip sample |
| CN105352768A (en) * | 2015-09-27 | 2016-02-24 | 上海华力微电子有限公司 | TEM sample positioning method |
| CN105136545B (en) * | 2015-10-19 | 2019-01-04 | 上海华力微电子有限公司 | A kind of labeling method of TEM chip sample |
| CN114236364B (en) * | 2022-02-24 | 2022-05-31 | 上海聚跃检测技术有限公司 | Failure analysis method and system for integrated circuit chip |
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