CN103532543A - Metal fuse latch structure - Google Patents
Metal fuse latch structure Download PDFInfo
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- CN103532543A CN103532543A CN201310529948.1A CN201310529948A CN103532543A CN 103532543 A CN103532543 A CN 103532543A CN 201310529948 A CN201310529948 A CN 201310529948A CN 103532543 A CN103532543 A CN 103532543A
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Abstract
The invention provides a novel metal fuse latch structure so as to improve the reading performance thereof. The metal fuse latch structure is mainly formed by sequentially connecting three stages of controlled inverters in series, wherein the third-stage inverter comprises a pull-up driving circuit, an N-type transistor N45 and an N-type transistor N46 which are sequentially connected in series; the pull-up driving circuit adopts the structure that a P-type transistor set is connected with a power supply upwardly and connected with a node A downwardly, and is used for generating pull-up driving to the voltage of the node A; the grid electrode of the P-type transistor in the pull-up driving circuit is connected to an adjustable bias voltage source, and the source electrode of the P-type transistor in the pull-up driving circuit is connected to the node A. The reading reliability and stability of the metal fuse latch structure are significantly improved; the metal fuse latch structure comprises a few transistors, so that the layout size is relatively small; after production of an integrated circuit, the reading capability of a fuse latch can be adjusted according to actual resistance characteristics of a fuse.
Description
Technical field
The present invention relates to a kind of metal fuse latch structure.
Background technology
Fuse refers to a kind of resistance of low-resistance value in electronics and power domain, by self fusing, provides the protection to overload current.Basic fuse unit is one section of metal wire or bonding jumper that under large current conditions, can fuse.
Fuse is different from above-mentioned concept in integrated circuit fields, but one section can be at metal wire or the polysilicon lines of artificial fusing of integrated circuit head end test stage.The state of fuse self on-off is used for the configuration information of storage chip.When fuse does not fuse, himself resistance value is zero in theory, is often used in representing " 0 " in circuit, and in the time of fuse fusing, himself resistance value be infinitely great in theory, is often used in expression " 1 " in circuit.After system power failure, the state of fuse on-off can keep, but cannot be reset.
Fuse latch is the particular electrical circuit that reads, stores and export the stored information of fuse for initial phase after chip power.
In integrated circuit, fuse is manufactured by metal wire or the polysilicon lines of first layer metal conventionally.Because resistivity and the contact hole resistance of first layer metal or polysilicon are all higher, so even in the situation that fuse does not fuse, the resistance of fuse self also can not be ignored.On the other hand, due to the restriction of technique, by the fuse of large electric current or laser blown, can not very perfectly be cut off, so its resistance is less than infinity under blown state.
In chip operation, although all right and wrong are Utopian for the conduction resistance value of fuse and fusing resistor value, fuse latch must accurately read the information of its storage, the namely state of fuse on-off.The basic principle circuit of fuse latch is composed in series (as Fig. 1) by a P transistor npn npn, N-type transistor and fuse.The output voltage of circuit represents the state of the fuse that reads out.In circuit working process, if charging current I1 is greater than discharging current I2, output node keeps high level, circuit output " 1 ".If discharging current I2 is greater than charging current I1, output node is pulled to low level, circuit output " 0 ".In order to guarantee the correct of in the nonideal situation of fuse resistance circuit output, the charging current I1 in circuit and discharging current I2 must carefully set according to the resistance characteristic of fuse in actual production.
As shown in Figure 2, its operation principle is as follows for traditional fuse latch structure:
At initial phase P16, P0, open, N0, N46 close, A point voltage is forced to remain on high level " 1 " by P16 by power supply, B point voltage is inverted device (P1 and N1) output and remains on low level " 0 ", and the stronger driving force that C point voltage is provided by P44, P4, P0 remains on high level " 1 ".
Enter after fetch phase, first P16 closes, and N46 opens simultaneously, and A and C point voltage still remain on high level " 1 " by latch (P1, N1, P44, P4, P0, N45, N46), but are no longer subject to by the driving of the supply voltage of P16.N0 opens subsequently, and A point is subject to N0 and by fuse, arrives the drop-down driving on ground, and P0 closes simultaneously, makes C point only be subject to the pulling drive of P44, and the suffered pulling drive ability of A point weakens.By setting transistorized size according to the characteristic of fuse in technique, can determine the mutual ratios of transistor driving ability.If not fusing of fuse like this, although fuse resistance be can not ignore, still can make the drop-down driving force that A is ordered be greater than the pulling drive ability weakening, A point voltage is reduced to low level " 0 "; If fuse fusing, although fuse resistance is not infinitely great, the pulling drive ability that still can make A order is greater than drop-down driving force, and A point voltage keeps high level " 1 ".
Latching output stage, A, B, C point voltage are latched and are exported by latch (P1, N1, P44, P4, P0, N45, N46).
Adopt this scheme, number of transistors is more, causes layout size larger.And the unsteadiness of technique is larger in integrated circuit production process, cause in actual production the characteristic variations of fuse larger.If the characteristic variations of fuse has surpassed expection, because the driving force of P44 cannot be adjusted after production, will cause occurring that mistake reads in the course of work of fuse latch.
Summary of the invention
The defect existing for overcoming above-mentioned traditional scheme, the invention provides a kind of new metal fuse latch structure, to improve its reading performance.
Basic scheme of the present invention is as follows:
A kind of metal fuse latch structure, mainly by three grades of controlled inverter, be followed in series to form, wherein, first order inverter is composed in series successively by P transistor npn npn P16, N-type transistor N0 and fuse, and second level inverter is composed in series by P transistor npn npn P1 and N-type transistor N1; The drain electrode of the source electrode of P transistor npn npn P16 and N-type transistor N0 is connected to node A altogether, and the grid of P transistor npn npn P1 and N-type transistor N1 grid are also connected to node A altogether, and the drain electrode of the source electrode of P transistor npn npn P1 and N-type transistor N1 is connected to node B altogether; Its special character is: third level inverter comprises pulling drive circuit, N-type transistor N45 and the N-type transistor N46 of series connection successively, wherein, pulling drive circuit adopts the structure that meets power supply, lower binding place A in P transistor npn npn group, in order to A point voltage is produced to pulling drive, the grid of a P transistor npn npn in pulling drive circuit is connected to adjustable bias voltage source, and source electrode is connected to node A.
Based on above-mentioned basic scheme, the present invention also further does following optimization and limits:
P45 is in series by P transistor npn npn P44, P transistor npn npn for described pulling drive circuit, wherein, the grid of the grid of P transistor npn npn P44 and N-type transistor N45 is connected to node B altogether, the grid of P transistor npn npn P45 is connected to adjustable bias voltage source, the drain electrode of the source electrode of P transistor npn npn P45 and N-type transistor N45 is connected to node C altogether, and node C and node A are direct-connected.
The present invention has following technique effect:
The present invention has significantly improved reading reliability and the stability of this series products: for the fuse not fusing, if its actual resistance is greater than expection, although can cause the driving force of the drop-down branch road of N0 to weaken, but at fetch phase, can improve bias voltage to weaken the pulling drive ability of P44 and P45, with this, guarantee that fuse latch still can correctly read the state low level " 0 " of fuse; Fuse for fusing, if its actual resistance is less than expection, although can cause the driving force of the drop-down branch road of N0 to strengthen, but at fetch phase, can reduce bias voltage to strengthen the pulling drive ability of P44 and P45, with this, guarantee that fuse latch still can correctly read the state high level " 1 " of fuse.
The number of transistors that the present invention comprises is less, so layout size is less; In addition, after producing, integrated circuit still can adjust according to the actual resistance characteristic of fuse the reading capability of fuse latch.
Accompanying drawing explanation
Fig. 1 is the basic principle figure of fuse latch circuit.
Fig. 2 is traditional fuse latch structure figure.
Fig. 3 is the control signal oscillogram of traditional fuse latch.
Fig. 4 is fuse latch structure figure of the present invention.
Fig. 5 is the control signal oscillogram of application fuse latch of the present invention.
Embodiment
Structure of the present invention as shown in Figure 4, this fuse latch is mainly followed in series to form by three grades of controlled inverter, described first order inverter is composed in series successively by P transistor npn npn P16, N-type transistor N0 and fuse, and second level inverter is composed in series by P transistor npn npn P1 and N-type transistor N1; The drain electrode of the source electrode of P transistor npn npn P16 and N-type transistor N0 is connected to node A altogether, and the grid of P transistor npn npn P1 and N-type transistor N1 grid are also connected to node A altogether, and the drain electrode of the source electrode of P transistor npn npn P1 and N-type transistor N1 is connected to node B altogether; It is characterized in that: third level inverter comprises P transistor npn npn P44, P transistor npn npn P45, N-type transistor N45 and the N-type transistor N46 of series connection successively, wherein, the grid of the grid of P transistor npn npn P44 and N-type transistor N45 is connected to node B altogether, the grid of P transistor npn npn P45 is connected to adjustable bias voltage source, the drain electrode of the source electrode of P transistor npn npn P45 and N-type transistor N45 is connected to node C altogether, and node C and node A are direct-connected.
This fuse latch input signal is three control signal: fpun, fpup_n, and bias, output is: flats, flats_n.
Pulling drive circuit of the present invention is the various deformation that can have other, because pull-up circuit is exactly by connecing power supply on P transistor npn npn, and the A point in lower map interlinking 4 (being the output in Fig. 1) and forming, effect is to charge to A point, above draws A point voltage.So meeting the circuit of said structure and function can here use as pull-up circuit.Such as the series connection of three or more P transistor npn npn single channel, or a plurality of P transistor npn npn multi-channel parallel (as the pull-up circuit of Fig. 2), as long as wherein the pulling drive ability of P transistor npn npn is subject to the control of bias voltage source.
It should be noted that, the circuit shown in Fig. 1 is the basic principle figure of whole metal fuse latch circuit, rather than P transistor npn npn P16, N-type transistor N0 and fuse in presentation graphs 2 or Fig. 4 metal fuse latch.Specifically, the P transistor npn npn of Fig. 1 has represented whole pull-up circuit, and N-type transistor has represented whole pull-down circuit.
Pull-up circuit in the latch of fuse shown in Fig. 2 is comprised of P44, P4 and P0, and pull-down circuit is comprised of N0 and fuse.Pull-up circuit in the latch of fuse shown in Fig. 4 is comprised of P44 and P45, and pull-down circuit is comprised of N0 and fuse.
The fuse latch course of work of the present invention and control signal and traditional fuse latch have similar part, but in the present invention, use a bias voltage to control pull-up circuit in the driving force of fuse latch fetch phase.This bias voltage is provided by voltage source on a sheet, and voltage swing can be regulated by input control signal after production.
At initial phase P16, P45, open, N0, N46 close, A point voltage is forced to remain on high level " 1 " by P16 by power supply, and B point voltage is inverted device (P1 and N1) output and remains on low level " 0 ", and the stronger driving force that C point voltage is provided by P44, P45 remains on high level " 1 ".
Enter after fetch phase, first P16 closes, and N46 opens simultaneously, and A and C point voltage still remain on high level " 1 " by latch (P1, N1, P44, P45, N45, N46), but are no longer subject to by the driving of the supply voltage of P16.N0 opens subsequently, and A point is subject to N0 and by fuse, arrives the drop-down driving on ground, and the grid voltage of P45 is provided by bias voltage and raises simultaneously, and the suffered pulling drive ability of C point (being A point) is weakened.By set the size of transistorized size and bias voltage according to the characteristic of fuse in technique, can determine the mutual ratios of transistor driving ability.If not fusing of fuse like this, although fuse resistance be can not ignore, still can make the drop-down driving force that A is ordered be greater than the pulling drive ability weakening, A point voltage is reduced to low level " 0 "; If fuse fusing, although fuse resistance is not infinitely great, the pulling drive ability that still can make A order is greater than drop-down driving force, and A point voltage keeps high level " 1 ".
Latching output stage, A, B, C point voltage are latched and are exported by latch (P1, N1, P44, P45, N45, N46).
Claims (2)
1. a metal fuse latch structure, mainly by three grades of controlled inverter, be followed in series to form, wherein, first order inverter is composed in series successively by P transistor npn npn P16, N-type transistor N0 and fuse, and second level inverter is composed in series by P transistor npn npn P1 and N-type transistor N1; The drain electrode of the source electrode of P transistor npn npn P16 and N-type transistor N0 is connected to node A altogether, and the grid of P transistor npn npn P1 and N-type transistor N1 grid are also connected to node A altogether, and the drain electrode of the source electrode of P transistor npn npn P1 and N-type transistor N1 is connected to node B altogether; It is characterized in that: third level inverter comprises pulling drive circuit, N-type transistor N45 and the N-type transistor N46 of series connection successively, wherein, pulling drive circuit adopts the structure that meets power supply, lower binding place A in P transistor npn npn group, in order to A point voltage is produced to pulling drive, the grid of a P transistor npn npn in pulling drive circuit is connected to adjustable bias voltage source, and source electrode is connected to node A.
2. metal fuse latch structure according to claim 1, it is characterized in that: P45 is in series by P transistor npn npn P44, P transistor npn npn for described pulling drive circuit, wherein, the grid of the grid of P transistor npn npn P44 and N-type transistor N45 is connected to node B altogether, the grid of P transistor npn npn P45 is connected to adjustable bias voltage source, the drain electrode of the source electrode of P transistor npn npn P45 and N-type transistor N45 is connected to node C altogether, and node C and node A are direct-connected.
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| CN201310529948.1A CN103532543A (en) | 2013-10-30 | 2013-10-30 | Metal fuse latch structure |
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| CN201310529948.1A CN103532543A (en) | 2013-10-30 | 2013-10-30 | Metal fuse latch structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105187045A (en) * | 2015-08-13 | 2015-12-23 | 清华大学 | Dynamic latch with pull-up PMOS (P-channel Metal Oxide Semiconductor) transistor of high-speed circuit |
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| DE102004048238A1 (en) * | 2004-10-04 | 2006-04-06 | Infineon Technologies Ag | Planar field-effect transistor e.g. P-type metal oxide semiconductor field-effect transistor, for e.g. chip planar, has gate region bending/brokenly proceeding in active region in a manner that drain and source regions are of variable sizes |
| US7260012B2 (en) * | 2003-02-14 | 2007-08-21 | Kabushiki Kaisha Toshiba | Fuse latch circuit |
| JP2008071819A (en) * | 2006-09-12 | 2008-03-27 | Toshiba Corp | Semiconductor storage device |
| CN101930787A (en) * | 2009-06-24 | 2010-12-29 | 合肥力杰半导体科技有限公司 | Internal memory interface circuit framework supporting multi-internal memory standard and implementation thereof on metal oxide semiconductor (MOS) process |
| CN203563050U (en) * | 2013-10-30 | 2014-04-23 | 西安华芯半导体有限公司 | Metal fuse latch structure |
-
2013
- 2013-10-30 CN CN201310529948.1A patent/CN103532543A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7260012B2 (en) * | 2003-02-14 | 2007-08-21 | Kabushiki Kaisha Toshiba | Fuse latch circuit |
| DE102004048238A1 (en) * | 2004-10-04 | 2006-04-06 | Infineon Technologies Ag | Planar field-effect transistor e.g. P-type metal oxide semiconductor field-effect transistor, for e.g. chip planar, has gate region bending/brokenly proceeding in active region in a manner that drain and source regions are of variable sizes |
| JP2008071819A (en) * | 2006-09-12 | 2008-03-27 | Toshiba Corp | Semiconductor storage device |
| CN101930787A (en) * | 2009-06-24 | 2010-12-29 | 合肥力杰半导体科技有限公司 | Internal memory interface circuit framework supporting multi-internal memory standard and implementation thereof on metal oxide semiconductor (MOS) process |
| CN203563050U (en) * | 2013-10-30 | 2014-04-23 | 西安华芯半导体有限公司 | Metal fuse latch structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105187045A (en) * | 2015-08-13 | 2015-12-23 | 清华大学 | Dynamic latch with pull-up PMOS (P-channel Metal Oxide Semiconductor) transistor of high-speed circuit |
| CN105187045B (en) * | 2015-08-13 | 2017-12-29 | 清华大学 | A kind of dynamic latch of the band pull-up PMOS of high speed circuit |
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Application publication date: 20140122 |