CN103532392A - Controller for a power converter and method of operating the same - Google Patents

Controller for a power converter and method of operating the same Download PDF

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CN103532392A
CN103532392A CN201310278566.6A CN201310278566A CN103532392A CN 103532392 A CN103532392 A CN 103532392A CN 201310278566 A CN201310278566 A CN 201310278566A CN 103532392 A CN103532392 A CN 103532392A
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controller
power converter
stage
llc
voltage
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CN103532392B (en
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A·布林李
S·钱德拉塞卡兰
S·马拉彻克
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Power Systems Technologies Ltd
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/42Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208Arrangements for improving power factor of AC input
    • H02M1/4225Arrangements for improving power factor of AC input using a non-isolated boost converter
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of DC power input into DC power output
    • H02M3/01Resonant DC/DC converters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0003Details of control, feedback or regulation circuits
    • H02M1/0025Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0003Details of control, feedback or regulation circuits
    • H02M1/0032Control circuits allowing low power mode operation, e.g. in standby mode
    • H02M1/0035Control circuits allowing low power mode operation, e.g. in standby mode using burst mode control
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0048Circuits or arrangements for reducing losses
    • H02M1/0054Transistor switching losses
    • H02M1/0058Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0067Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007Plural converter units in cascade
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of DC power input into DC power output
    • H02M3/22Conversion of DC power input into DC power output with intermediate conversion into AC
    • H02M3/24Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
    • H02M3/28Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
    • H02M3/325Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33571Half-bridge at primary side of an isolation transformer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本发明的各实施方式总体上涉及用于功率转换器的控制器以及对其进行操作的方法。具体地,涉及一种用于功率转换器的控制器以及对其进行操作的方法。在一个实施例中,该控制器包括电感器-电感器-电容器(LLC)控制器,其被配置为接收来自误差放大器的误差信号以控制功率转换器的LLC级的开关频率来对功率转换器的输出电压进行调整。该控制器还包括功率因数校正(PFC)控制器,其被配置为对由功率转换器的PFC级产生并且提供至LLC级的母线电压进行控制以使得LLC级的平均开关频率基本上被保持在期望的开关频率。

Figure 201310278566

Embodiments of the invention generally relate to controllers for power converters and methods of operating the same. In particular, it relates to a controller for a power converter and a method of operating the same. In one embodiment, the controller includes an inductor-inductor-capacitor (LLC) controller configured to receive an error signal from an error amplifier to control the switching frequency of the LLC stage of the power converter to The output voltage is adjusted. The controller also includes a power factor correction (PFC) controller configured to control the bus voltage generated by the PFC stage of the power converter and provided to the LLC stage such that the average switching frequency of the LLC stage is maintained substantially at desired switching frequency.

Figure 201310278566

Description

用于功率转换器的控制器以及对其进行操作的方法Controller for power converter and method of operating same

技术领域technical field

本发明总体上涉及功率电子器件,并且尤其涉及一种用于功率转换器的控制器以及对其进行操作的方法。The present invention relates generally to power electronics, and more particularly to a controller for a power converter and a method of operating the same.

背景技术Background technique

开关模式功率转换器(也被称作“功率转换器”或“调整器”)是将输入电压波形转换为指定输出电压或电流波形的电源或功率处理电路。功率因数校正(PFC)/谐振电感器-电感器-电容器(LLC)功率转换器包括具有后跟LLC级的PFC级的功率系。该功率转换器耦合至电力源(交流(ac)电源)并且提供直流(dc)输出电压。PFC级(从ac电源)接收ac输入电压的整流版本并且提供dc母线电压。LLC级采用母线电压向负载提供dc输出电压。包括PFC级和LLC级的功率转换器可以被用来构建“ac适配器”以从ac电源向笔记本计算机等提供dc输出电压。A switch-mode power converter (also called a "power converter" or "regulator") is a power supply or power processing circuit that converts an input voltage waveform into a specified output voltage or current waveform. A power factor correction (PFC)/resonant inductor-inductor-capacitor (LLC) power converter includes a power train with a PFC stage followed by an LLC stage. The power converter is coupled to a power source (an alternating current (ac) power source) and provides a direct current (dc) output voltage. The PFC stage (from the ac source) receives a rectified version of the ac input voltage and provides a dc bus voltage. The LLC stage uses the bus voltage to provide a dc output voltage to the load. A power converter including a PFC stage and an LLC stage can be used to build an "ac adapter" to provide a dc output voltage from an ac power source to a notebook computer or the like.

与功率转换器相关联的控制器通过控制其中所采用的功率开关的导通周期而对功率转换器的操作进行管理。通常,控制器以反馈回路结构(也被称作“控制回路”或“闭合控制回路”)而耦合在功率转换器的输入和输出之间。经常采用两种控制过程来控制利用后跟LLC级的PFC级形成的功率转换器的输出电压。一种过程控制PFC级的母线电压以对输出电压进行控制,而另一种过程则控制LLC级的开关频率来对输出电压进行控制。如将更为显而易见的,采用两种独立过程对具有PFC级和LLC级的功率转换器的输出电压进行控制会导致有损于该功率转换器的操作和效率的若干设计问题。A controller associated with the power converter manages the operation of the power converter by controlling the conduction period of the power switches employed therein. Typically, a controller is coupled between the input and output of the power converter in a feedback loop configuration (also referred to as a "control loop" or "closed control loop"). Two control procedures are often employed to control the output voltage of a power converter formed with a PFC stage followed by an LLC stage. One process controls the bus voltage of the PFC stage to control the output voltage, while the other process controls the switching frequency of the LLC stage to control the output voltage. As will be more apparent, employing two separate processes to control the output voltage of a power converter having a PFC stage and an LLC stage results in several design issues that detract from the operation and efficiency of the power converter.

关于功率转换器的另一个感兴趣领域通常是在轻载条件下对其进行的检测和操作。在这样的条件下,对于功率转换器而言,进入突发操作模式会是有利的。就突发操作模式而言,功率转换器的功率损失取决于功率开关的栅极驱动信号以及通常基本上不随负载变化的其它持续性功率损失。这些功率损失一般通过使用突发操作模式在非常低的功率水平得以解决,其中在一段时间内(例如,一秒)使得控制器无效,随后为短时间的高功率操作(例如,10毫秒(ms))以提供具有低损耗的低平均输出功率。如这里所描述的控制器可以采用突发操作模式的时间间隔来估计功率转换器的输出(或负载)功率。Another area of interest with power converters is generally their detection and operation under light load conditions. Under such conditions, it may be advantageous for the power converter to enter a burst mode of operation. For the burst mode of operation, the power loss of the power converter depends on the gate drive signal of the power switch and other continuous power losses that generally do not vary substantially with load. These power losses are generally addressed at very low power levels by using a burst mode of operation, in which the controller is disabled for a period of time (e.g., one second), followed by a short period of high power operation (e.g., 10 milliseconds (ms )) to provide low average output power with low losses. A controller as described herein may employ the time interval of the burst mode of operation to estimate the output (or load) power of the power converter.

因此,本领域需要一种控制器,其将混合方法结合到用于在其功率系中采用不同功率级的功率转换器的控制过程以避免现有技术中的缺陷。此外,本领域需要一种控制器,其能够检测并管理在轻载情况下的功率转换器,包括功率转换器进入突发操作模式的操作,以避免现有技术中的缺陷。Therefore, there is a need in the art for a controller that incorporates a hybrid approach to the control process for power converters employing different power levels in their power trains to avoid the deficiencies in the prior art. Furthermore, there is a need in the art for a controller capable of detecting and managing a power converter under light load conditions, including the operation of the power converter into a burst mode of operation, to avoid the deficiencies of the prior art.

发明内容Contents of the invention

技术优势总体上通过本发明的有益实施例得以实现,其包括一种用于功率转换器的控制器以及对其进行操作的方法。在一个实施例中,该控制器包括电感器-电感器-电容器(LLC)控制器,其被配置为从误差放大器接收误差信号以控制功率转换器的LLC级的开关频率来对功率转换器的输出电压进行调整。该控制器还包括功率因数校正(PFC)控制器,其被配置为对由功率转换器的PFC级产生并且提供至LLC级的母线电压进行控制以使得LLC级的平均开关频率基本上被保持在期望的开关频率。Technical advantages are generally achieved by advantageous embodiments of the present invention, including a controller for a power converter and methods of operating the same. In one embodiment, the controller includes an inductor-inductor-capacitor (LLC) controller configured to receive an error signal from an error amplifier to control the switching frequency of the LLC stage of the power converter to The output voltage is adjusted. The controller also includes a power factor correction (PFC) controller configured to control the bus voltage generated by the PFC stage of the power converter and provided to the LLC stage such that the average switching frequency of the LLC stage is maintained substantially at desired switching frequency.

在另一方面,一种用于功率转换器的突发模式控制器包括突发模式发起电路,其被配置为在表示功率转换器的输出电压的信号与第一突发阈值水平相交时发起突发操作模式。该突发模式控制器还包括电压提升电路,其被配置为在时间窗口在表示功率转换器的输出电压的信号与第二突发阈值水平相交之前过期的情况下提供电压提升信号以升高输出电压。In another aspect, a burst mode controller for a power converter includes a burst mode initiation circuit configured to initiate a burst when a signal representing an output voltage of the power converter crosses a first burst threshold level. send operation mode. The burst mode controller also includes a voltage boost circuit configured to provide a voltage boost signal to boost the output if a time window expires before the signal representative of the output voltage of the power converter crosses the second burst threshold level Voltage.

以上已经相当宽泛地对本发明的特征和技术优势进行了概括,以便可以更好地对随后对本发明的详细描述加以理解。下文将对本发明的附加特征和优势进行描述,它们形成了本发明权利要求的主题。本领域技术人员应当意识到的是,所公开的概念和具体实施例可以容易地被用作修改或设计其它结构或过程以实施本发明的相同目的的基础。本领域技术人员还应当意识到的是,这样的等同构造并不背离如所附权利要求中所给出的本发明的精神和范围。The foregoing has outlined rather broadly the features and technical advantages of the present invention so that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

附图说明Description of drawings

为了更为全面地理解本发明,现在参考以下结合附图所进行的描述,其中:For a more comprehensive understanding of the present invention, reference is now made to the following descriptions in conjunction with the accompanying drawings, wherein:

图1图示了根据本发明的原理而构造的包括控制器的功率转换器的实施例的框图;Figure 1 illustrates a block diagram of an embodiment of a power converter including a controller constructed in accordance with the principles of the present invention;

图2图示了根据本发明的原理而构造的包括采用升压拓扑的示例性功率系的功率转换器的一部分的示意图;2 illustrates a schematic diagram of a portion of a power converter including an exemplary power train employing a boost topology, constructed in accordance with the principles of the present invention;

图3图示了根据本发明的原理而构造的利用耦合至LLC级的PFC级而形成的功率转换器的实施例的电路图;3 illustrates a circuit diagram of an embodiment of a power converter formed using a PFC stage coupled to an LLC stage constructed in accordance with the principles of the present invention;

图4-图6图示了根据本发明的原理的功率转换器的示例性操作特性的图形表示;4-6 illustrate graphical representations of exemplary operating characteristics of a power converter in accordance with the principles of the present invention;

图7和图8图示了根据本发明的原理而构造的利用耦合至LLC级的PFC级而形成的功率转换器的实施例的示图;7 and 8 illustrate diagrams of embodiments of power converters formed using a PFC stage coupled to an LLC stage constructed in accordance with the principles of the present invention;

图9图示了依据本发明的原理的被配置为对功率转换器的突发操作模式进行管理的突发模式控制器的实施例的示意图;9 illustrates a schematic diagram of an embodiment of a burst mode controller configured to manage a burst mode of operation of a power converter in accordance with the principles of the present invention;

图10图示了在依据本发明的原理的功率转换器内产生的示例性波形的图形表示;Figure 10 illustrates a graphical representation of exemplary waveforms generated within a power converter in accordance with the principles of the present invention;

图11图示了根据本发明的原理而构造的耦合至功率转换器的输出电压的电阻分压器的实施例的示图;以及Figure 11 illustrates a diagram of an embodiment of a resistive divider coupled to an output voltage of a power converter constructed in accordance with the principles of the present invention; and

图12图示了根据本发明的原理而构造的电压提升电路中用于产生斜率信号的部分的实施例的示图,该斜率信号指示可在突发模式控制器中采用的功率转换器的输出电压的斜率。Figure 12 illustrates a diagram of an embodiment of a portion of a voltage boost circuit constructed in accordance with the principles of the present invention for generating a slope signal indicative of the output of a power converter that may be employed in a burst mode controller The slope of the voltage.

除非另外指出,不同示图中相对应的数字和符号通常指代相对应的部分,并且出于简明的目的可能在第一实例之后不再进行描述。附图被绘制用于对示例性实施例的相关方面进行图示。Corresponding numerals and symbols in the different drawings generally refer to corresponding parts unless otherwise indicated and may not be described after the first instance for the sake of brevity. The figures are drawn to illustrate relevant aspects of the exemplary embodiments.

具体实施方式Detailed ways

以下对该示例性实施例的制造和使用进行详细讨论。然而,应当意识到的是,本发明提供了能够在各种具体环境中得以体现的许多可应用的发明概念。所讨论的具体实施例仅是制造和使用本发明的具体方式的说明,而并不对本发明的范围进行限制。The making and using of the exemplary embodiment are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

将就具体上下文(即,用于功率转换器的控制器)中的示例性实施例对本发明进行描述。虽然将在用于功率因数校正(PFC)/谐振电感器-电感器-电容器(LLC)功率转换器的控制器的环境中对本发明的原理进行描述,但是可以从诸如功率放大器或电机控制器之类的控制器获益的任何应用同样处于本发明的宽泛范围之内。The present invention will be described with respect to exemplary embodiments in a specific context, ie, a controller for a power converter. Although the principles of the present invention will be described in the context of a controller for a power factor correction (PFC)/resonant inductor-inductor-capacitor (LLC) power converter, it can be obtained from, for example, a power amplifier or a motor controller. Any application in which a controller of this type would benefit is also within the broad scope of the present invention.

首先参考图1,其图示了根据本发明的原理而构造的包括控制器110的功率转换器的实施例的框图。功率转换器耦合至由提供输入电压Vin的ac电源所表示的ac干线。该功率转换器包括由控制器110所控制的功率系(power train)105。控制器110通常测量功率转换器的诸如其输出电压Vout的操作特性,并且响应于所测量的操作特性来控制其中的功率开关的占空比D以对该特性进行调整。功率系105可以包括多个功率级以向负载提供经调整的输出电压Vout或其它输出特性。功率转换器的功率系105包括耦合至磁性设备以提供功率转换功能的多个功率开关。Referring first to FIG. 1 , there is illustrated a block diagram of an embodiment of a power converter including a controller 110 constructed in accordance with the principles of the present invention. The power converter is coupled to an ac mains represented by an ac source providing an input voltage Vin. The power converter includes a power train 105 controlled by a controller 110 . The controller 110 typically measures an operating characteristic of the power converter, such as its output voltage Vout, and controls the duty cycle D of the power switch therein in response to the measured operating characteristic to adjust the characteristic. The power train 105 may include multiple power stages to provide a regulated output voltage Vout or other output characteristic to a load. The power train 105 of the power converter includes a plurality of power switches coupled to magnetic devices to provide power conversion functions.

现在转向图2,其图示了根据本发明的原理而构造的包括采用升压拓扑(例如,PFC升压级)的示例性功率系(例如,PFC级201)的功率转换器的一部分的示意图。功率转换器的PFC级210在其输入接收来自诸如ac干线之类的电力源的输入电压Vin(例如,未调整的ac输入电压)并且提供经调整的DC母线电压(也被称作母线电压)Vbus。与升压拓扑的原理相符,该母线电压Vbus通常高于输入电压Vin以使得其开关操作能够对母线电压Vbus进行调整。使得干线功率开关S1(例如,n沟道金属氧化物半导体(NMOS)“有源”开关)能够通过栅极驱动信号GD导通主要间隔并且将输入电压Vin通过桥式整流器203耦合至升压电感器Lboost。在开关周期的主要间隔D期间,电感器电流iin增大并且通过升压电感器Lboost流向局部电路接地端。升压电感器Lboost通常利用单层绕组来形成以减少接近效应而提高功率转换器的效率。Turning now to FIG. 2 , there is illustrated a schematic diagram of a portion of a power converter including an exemplary power train (eg, PFC stage 201 ) employing a boost topology (eg, PFC boost stage) constructed in accordance with the principles of the present invention. . The PFC stage 210 of the power converter receives at its input an input voltage Vin (eg, an unregulated ac input voltage) from a power source such as the ac mains and provides a regulated DC bus voltage (also referred to as the bus voltage) Vbus. Consistent with the principle of boost topology, the bus voltage Vbus is usually higher than the input voltage Vin so that its switching operation can adjust the bus voltage Vbus. The mains power switch S1 (e.g., an n-channel metal-oxide-semiconductor (NMOS) "active" switch) is enabled to conduct the main compartment via the gate drive signal GD and couple the input voltage Vin to the boost voltage via the bridge rectifier 203 Inductor L boost . During the main interval D of the switching cycle, the inductor current i in increases and flows through the boost inductor L boost to the local circuit ground. The boost inductor L boost is usually formed with a single layer winding to reduce the proximity effect and improve the efficiency of the power converter.

PFC级201的占空比在稳态下根据以下等式而取决于输入电压知母线电压(分别为Vin、Vbus)之比:The duty cycle of the PFC stage 201 at steady state depends on the ratio of the input voltage to the bus voltage (Vin, Vbus, respectively) according to the following equation:

DD. == 11 -- VinVin VbusVbus

在互补间隔1-D期间,主功率开关S1被转变至非导通状态而辅助功率开关(例如,二极管D1)导通。在可替换的电路布置中,辅助功率开关可以包括第二有源开关,其被控制由互补栅极驱动信号导通。辅助功率开关D1提供了一种保持流过升压电感器Lboost的电感器电流iin连续性的途径。在互补间隔1-D期间,流过升压电感器Lboost的电感器电流iin降低,并且可以变为零,以及在一段时间保持为零,这导致操作的“非连续导通模式”。During complementary interval 1-D, the main power switch S1 is transitioned to a non-conducting state while the auxiliary power switch (eg, diode D1 ) is conducting. In an alternative circuit arrangement, the auxiliary power switch may comprise a second active switch controlled to be turned on by a complementary gate drive signal. Auxiliary power switch D1 provides a way to maintain continuity of inductor current i in through boost inductor L boost . During the complementary interval 1-D, the inductor current i in flowing through the boost inductor Lboost decreases and may become zero and remain zero for a period of time, which results in a "discontinuous conduction mode" of operation.

在互补间隔1-D期间,流过升压电感器Lboost的电感器电流iin通过二极管D1(即,辅助功率开关)流入滤波电容器C。通常,主功率开关S1的占空比(以及辅助功率开关D1的互补占空比)可以被调节以保持PFC级201的母线电压Vbus的调整。本领域技术人员所理解的是,通过使用“阻尼器(snubber)”电路元件(未示出)或者通过控制电路时序,主功率开关S1和辅助功率开关D1的导通周期可以通过小的时间间隔分隔开来以避免其间的交叉导通电流,并且有利地减少与功率转换器相关联的开关损失。用于避免主功率开关S1和辅助功率开关D1之间的交叉导通电流的电路和控制技术在本领域是公知的并且为了简要而将不对其进行进一步描述。升压电感器Lboost通常利用单层绕组来形成以减少与接近效应相关联的功率损失。During the complementary interval 1-D, the inductor current i in flowing through the boost inductor L boost flows into the filter capacitor C through the diode D1 (ie, the auxiliary power switch). In general, the duty cycle of the main power switch S 1 (and the complementary duty cycle of the auxiliary power switch D 1 ) can be adjusted to maintain regulation of the bus voltage Vbus of the PFC stage 201 . Those skilled in the art understand that by using "snubber" circuit elements (not shown) or by controlling the circuit timing, the conduction period of the main power switch S1 and the auxiliary power switch D1 can be controlled by a small time The spaces are spaced apart to avoid cross-conduction current therebetween and advantageously reduce switching losses associated with the power converter. Circuitry and control techniques for avoiding cross-conduction currents between main power switch S1 and auxiliary power switch D1 are well known in the art and will not be further described for the sake of brevity. The boost inductor L boost is typically formed with a single layer winding to reduce power loss associated with proximity effects.

现在转向图3,图示了根据本发明的原理所构造的利用耦合至LLC级320(例如,半桥式LLC隔离谐振降压级)的PFC级(诸如图2的PFC级201)形成的功率转换器的实施例的电路图。PFC级201和LLC级320可以被用来构造“ac适配器”以从ac干线电源(由输入电压Vin表示)向笔记本计算机提供dc输出电压Vout(例如,19.5伏)。Turning now to FIG. 3, there is illustrated the power developed by a PFC stage, such as PFC stage 201 of FIG. Circuit diagram of an embodiment of the converter. The PFC stage 201 and LLC stage 320 may be used to construct an "ac adapter" to provide a dc output voltage Vout (eg, 19.5 volts) to a notebook computer from an ac mains supply (represented by input voltage Vin).

如以上所提到的,经常采用两种控制过程来控制利用后跟LLC级320的PFC级201所形成的功率转换器的输出电压Vout。一种过程控制PFC级201的母线电压Vbus而对输出电压Vout进行控制,而另一种过程则控制LLC级320的开关频率(也被命名为开关频率fs)而对输出电压Vout进行控制。由PFC级201产生的母线电压Vbus在较慢的响应反馈回路中响应于耦合至LLC级320的输出的负载而受到控制。LLC级320以固定开关频率fs进行操作,该开关频率fs被选择以增加其功率转换效率。LLC级320在理想变压器状态中利用由PFC级201产生的母线电压Vbus而连续操作,该PFC级320被控制以对LLC级320中的IR(电流乘以电阻)下降进行补偿。通常,由PFC级201产生的母线电压Vbus的变化为数十伏的量级。As mentioned above, two control processes are often employed to control the output voltage Vout of a power converter formed with the PFC stage 201 followed by the LLC stage 320 . One process controls the bus voltage Vbus of the PFC stage 201 to control the output voltage Vout, while the other process controls the switching frequency (also named switching frequency fs) of the LLC stage 320 to control the output voltage Vout. The bus voltage Vbus produced by the PFC stage 201 is controlled in response to the load coupled to the output of the LLC stage 320 in a slower response feedback loop. The LLC stage 320 operates at a fixed switching frequency fs selected to increase its power conversion efficiency. The LLC stage 320 operates continuously in an ideal transformer state with the bus voltage Vbus generated by the PFC stage 201 , which is controlled to compensate for the IR (current times resistance) drop in the LLC stage 320 . Typically, the variation of the bus voltage Vbus produced by the PFC stage 201 is on the order of tens of volts.

使用开关频率对LLC级320进行控制,PFC级201产生恒定的dc母线电压Vbus,但是LLC级320则利用开关频率进行操作,该开关频率响应于耦合至功率转换器输出的负载的变化而利用快速响应控制回路(即,具有高的交叉频率的控制回路)进行控制。改变LLC级320的开关频率通常使得LLC级320以低效的开关频率进行操作。The LLC stage 320 is controlled using a switching frequency, the PFC stage 201 produces a constant dc bus voltage Vbus, but the LLC stage 320 operates using a switching frequency that responds to changes in the load coupled to the power converter output using a fast Control is performed in response to a control loop (ie, a control loop with a high crossover frequency). Changing the switching frequency of LLC stage 320 typically causes LLC stage 320 to operate at an inefficient switching frequency.

提供了一种混合控制方法,其中由PFC级201产生的母线电压Vbus利用较慢响应控制回路(即,具有低交叉频率的控制回路)进行控制以处理平均负载功率。利用快速响应反馈回路对LLC级320的开关频率进行控制以处理负载瞬变和ac干线信号退出(dropout)的事件。控制PFC级201以对输出电压Vout进行控制导致了若干设计问题。首先,母线电压Vbus通常由于低的PFC控制回路交叉频率而表现出很差的瞬变响应。其次,在对LLC级320供电的母线电压Vbus上存在大量出现在其输出之上的纹波电压(例如,100-120赫兹的纹波电压)。A hybrid control approach is provided where the bus voltage Vbus produced by the PFC stage 201 is controlled with a slower response control loop (ie a control loop with a low crossover frequency) to handle the average load power. The switching frequency of the LLC stage 320 is controlled using a fast response feedback loop to handle load transients and ac mains signal dropout events. Controlling the PFC stage 201 to control the output voltage Vout leads to several design issues. First, the bus voltage Vbus usually exhibits poor transient response due to low PFC control loop crossover frequency. Second, there is a large amount of ripple voltage (eg, 100-120 Hz ripple voltage) on the bus voltage Vbus that powers the LLC stage 320 that appears on its output.

如这里所介绍的,LLC级320的开关频率利用快速响应控制回路进行控制以衰减通常出现在LLC级320的输出上的由PFC级201产生的纹波电压的影响。此外,LLC级320的变压器/级增益在1/(2π·sqrt((Lm+Lk)·Cr))和1/(2π·sqrt(Lk·Cr))之间的频率区域内被快速响应控制回路所采用以适应大的负载步幅变化以及ac干线输入电压Vin的信号退出的事件。PFC级201的母线电压Vbus响应于负载的缓慢变化而被控制以使得LLC级320能够理想地以其谐振频率或附近继续地操作,其功率转换效率在该点通常为最佳。通过令LLC级320大多数时间在其谐振频率或附近进行操作,但是允许开关频率响应于瞬变而变化,能够获得改善的负载步幅响应、减少的输出电压Vout的纹波以及更高的功率转换效率。As described herein, the switching frequency of the LLC stage 320 is controlled using a fast response control loop to attenuate the effect of the ripple voltage produced by the PFC stage 201 that typically appears on the output of the LLC stage 320 . Furthermore, the transformer/stage gain of the LLC stage 320 is controlled with fast response in the frequency region between 1/(2π sqrt((Lm+Lk) Cr)) and 1/(2π sqrt(Lk Cr)) The loop is adapted to accommodate large load step changes and the event of a signal exit of the ac mains input voltage Vin. The bus voltage Vbus of the PFC stage 201 is controlled in response to slow changes in load so that the LLC stage 320 can ideally continue to operate at or near its resonant frequency, at which point its power conversion efficiency is typically optimal. By having the LLC stage 320 operate at or near its resonant frequency most of the time, but allowing the switching frequency to vary in response to transients, improved load step response, reduced ripple in the output voltage Vout, and higher power can be obtained conversion efficiency.

变压器T1的初级电感是泄露电感Lk加上磁化电感Lm,两个电感都以变压器T1的初级绕组为参考。谐振电容器为Cr。谐振电容器Cr可以被划分为耦合在串行电路中的两个电容器,该串行电路的一端耦合至接地端而另一端则耦合至母线电压Vbus。串行电路布置可以被用来降低启动时的侵入电流。fs的理想开关频率是fo=1/(2π·sqrt(Lk·cr)),在正常情况下这是高效操作点(例如,50千赫(kHz))。在其开始低效电容开关的低开关频率为fmin=1/(2π·sqrt(Lp·Cr))。通常期望以大于最小开关频率fmin的开关频率进行操作,并且甚至避免接近最小开关频率fmin的开关频率。The primary inductance of the transformer T1 is the leakage inductance Lk plus the magnetizing inductance Lm, both inductances are referenced to the primary winding of the transformer T1. The resonant capacitor is Cr. The resonant capacitor Cr can be divided into two capacitors coupled in a series circuit with one end coupled to ground and the other end coupled to the bus voltage Vbus. A serial circuit arrangement can be used to reduce the inrush current at start-up. The ideal switching frequency for fs is fo=1/(2π·sqrt(Lk·cr)), which is the high-efficiency operating point under normal conditions (eg, 50 kilohertz (kHz)). The low switching frequency at which inefficient capacitive switching begins is fmin=1/(2π·sqrt(Lp·Cr)). It is generally desirable to operate at switching frequencies greater than the minimum switching frequency fmin, and to avoid even switching frequencies close to the minimum switching frequency fmin.

控制器325具有用于母线电压Vbus的输入以及来自反馈电路的用于功率转换器的输出电压Vout的输入,该反馈电路包括光耦合器350。如以下参考图7和图8所图示并描述的,压控振荡器(VCO)336对LLC级320的开关频率fs进行控制。因此,PFC级201和LLC级320在电压域和频率域中被联合控制。如以下进一步描述的,不时对控制器325的操作进行测试以使得能够在轻载的情况下进入突发模式。The controller 325 has an input for the bus voltage Vbus and an input for the output voltage Vout of the power converter from a feedback circuit including an optocoupler 350 . As illustrated and described below with reference to FIGS. 7 and 8 , a voltage controlled oscillator (VCO) 336 controls the switching frequency fs of the LLC stage 320 . Therefore, the PFC stage 201 and the LLC stage 320 are jointly controlled in the voltage domain and the frequency domain. As described further below, the operation of the controller 325 is tested from time to time to enable entry into burst mode under light load conditions.

如图3所示,输入电压Vin耦合至电磁干扰滤波器(EMI)310,其输出耦合至桥式整流器203以产生整流电压Vrect。PFC级201产生母线电压Vbus,其耦合至LLC级320的输入以产生输出电压Vout,该输出电压Vout通过功率转换器的输出滤波电容器Cout进行滤波。在可替换实施例中,可以利用全桥式拓扑形成LLC级320。利用误差放大器340感测输出电压Vout,该误差放大器340耦合至利用第一电阻器Rsensel和第二电阻器Rsense2形成的电阻分压器。来自误差放大器340的输出信号耦合至光耦合器350,其产生输出电压误差信号(也被称作“误差信号”)δV。输出电压误差信号δV和母线电压Vbus耦合至控制器325的PFC控制器330和/或LLC控制器333(以下就图7在下文更为详细地进行描述)。控制器325对由PFC级201产生的母线电压Vbus和LLC级320的开关频率fs进行联合控制以对输出电压Vout进行调整,同时将开关频率fs(大多数时间)保持在LLC级320的高效操作点。As shown in FIG. 3 , the input voltage Vin is coupled to an electromagnetic interference filter (EMI) 310 , and its output is coupled to a bridge rectifier 203 to generate a rectified voltage Vrect. The PFC stage 201 generates a bus voltage Vbus, which is coupled to the input of the LLC stage 320 to generate an output voltage Vout, which is filtered by an output filter capacitor Cout of the power converter. In an alternative embodiment, LLC stage 320 may be formed using a full bridge topology. The output voltage Vout is sensed by an error amplifier 340 coupled to a resistor divider formed by a first resistor Rsensel and a second resistor Rsense2. The output signal from error amplifier 340 is coupled to optocoupler 350, which generates an output voltage error signal (also referred to as "error signal") δV. The output voltage error signal δV and bus voltage Vbus are coupled to PFC controller 330 and/or LLC controller 333 of controller 325 (described in more detail below with respect to FIG. 7 ). The controller 325 jointly controls the bus voltage Vbus generated by the PFC stage 201 and the switching frequency fs of the LLC stage 320 to regulate the output voltage Vout while maintaining the switching frequency fs (most of the time) at the efficient operation of the LLC stage 320 point.

在操作中,耦合至输出电压Vout的负载的空载到满载(zero-to-full)的步幅变化例如会使母线电压Vbus由于控制器325的固有地低的交叉频率而从370伏下降至290伏。通过利用快速响应控制回路将LLC级320的开关频率fs从50kHz降至25kHz,可以为1.3至1或更高的LLC级320所增加的电压增益可以被用来对母线电压Vbus的下降进行实质性补偿。随着母线电压Vbus恢复至大约390伏以对LLC级320中的IR下降进行补偿,其开关频率fs返回至50kHz。In operation, a zero-to-full step change in the load coupled to the output voltage Vout, for example, would cause the bus voltage Vbus to drop from 370 volts to 290 volts. By reducing the switching frequency fs of the LLC stage 320 from 50kHz to 25kHz using a fast response control loop, the increased voltage gain of the LLC stage 320 from 1.3 to 1 or more can be used to substantially reduce the bus voltage Vbus. compensate. As the bus voltage Vbus recovers to approximately 390 volts to compensate for the IR drop in the LLC stage 320, its switching frequency fs returns to 50 kHz.

相同原理可以在ac干线电压(输入电压Vin)信号退出时被应用于保持(holdup)事件。在母线电压Vbus从390伏下降至280伏的同时,存储于PFC级201的滤波电容器C中的剩余能量可以被用来保持对输出电压Vout的调整。同样,LLC级320的依赖于频率的电压增益响应于快速响应控制回路而被用来对功率转换器的输出电压Vout进行调整。LLC级320的响应因此可以被用来减小PFC级201的滤波电容器C的大小或者增加功率转换器用于ac输入电压(输入电压Vin)下降的运转(ride-through)时间。如以下进一步描述的,采用非线性反馈以进行控制回路补偿。The same principle can be applied to a holdup event when the ac mains voltage (input voltage Vin) signal exits. While the bus voltage Vbus drops from 390 volts to 280 volts, the remaining energy stored in the filter capacitor C of the PFC stage 201 can be used to maintain regulation of the output voltage Vout. Likewise, the frequency-dependent voltage gain of the LLC stage 320 is used to regulate the output voltage Vout of the power converter in response to a fast response control loop. The response of the LLC stage 320 can thus be used to reduce the size of the filter capacitor C of the PFC stage 201 or to increase the power converter ride-through time for the ac input voltage (input voltage Vin) to drop. As described further below, non-linear feedback is employed for control loop compensation.

如以下更为详细描述的,由控制器325得出突发模式控制信号。当突发模式控制信号为高电平时,控制器325被使能进行操作。相反,当突发模式控制信号为低电平时,控制器325被无效。突发模式控制信号能够被用来使能功率转换器的突发操作模式。PFC控制器330在开关周期的主占空比D和互补占空比1-D期间为PFC级201的主功率开关S1提供栅极驱动信号,并且LLC控制器333在开关周期的主间隔D和互补间隔1-D期间为LLC级320的主功率开关M1和辅助功率开关M2提供栅极驱动信号。PFC控制器330还采用电压Vrect控制来自桥式整流器203的低频电流波形。命名为GDM2的栅极驱动信号表示图12所示的电路中将采用的LLC级320的互补间隔1-D期间至辅助功率开关M2的栅极驱动信号。The burst mode control signal is derived by controller 325 as described in more detail below. When the burst mode control signal is high, the controller 325 is enabled to operate. Conversely, when the burst mode control signal is low, the controller 325 is disabled. The burst mode control signal can be used to enable the burst mode of operation of the power converter. The PFC controller 330 provides a gate drive signal for the main power switch S1 of the PFC stage 201 during the main duty cycle D and the complementary duty cycle 1-D of the switching cycle, and the LLC controller 333 provides the gate drive signal for the main power switch S1 of the PFC stage 201 during the main interval D and the complementary duty cycle 1-D of the switching cycle. Gate drive signals are provided to the main power switch M1 and the auxiliary power switch M2 of the LLC stage 320 during complementary intervals 1-D. PFC controller 330 also uses voltage Vrect to control the low frequency current waveform from bridge rectifier 203 . The gate drive signal named GDM 2 represents the gate drive signal to the auxiliary power switch M 2 during the complementary interval 1-D of the LLC stage 320 to be employed in the circuit shown in FIG. 12 .

现在转向图4-6,图示了根据本发明的原理的功率转换器的示例性操作特性的图形表示。图4图示了功率转换器的LLC级的电压传输特性。在来自PFC级的特定母线电压Vbus(诸如400伏)处的LLC级(和功率转换器)的输出电压Vout以非线性的方式取决于LLC级的开关频率fs。随着母线电压Vbus减小,输出电压Vout在开关频率fs不变的情况下近似地成比例减小。其结果是开关频率fs能够在母线电压Vbus变化时进行变化以对输出电压Vout进行控制。然而,改变开关频率fs对于输出电压Vout的影响是非线性的。谐振频率fres表示LLC级的谐振频率。Turning now to FIGS. 4-6 , there are illustrated graphical representations of exemplary operating characteristics of a power converter in accordance with the principles of the invention. Fig. 4 illustrates the voltage transfer characteristics of the LLC stage of the power converter. The output voltage Vout of the LLC stage (and power converter) at a certain bus voltage Vbus (such as 400 volts) from the PFC stage depends in a non-linear manner on the switching frequency fs of the LLC stage. As the bus voltage Vbus decreases, the output voltage Vout decreases approximately proportionally while the switching frequency fs remains constant. As a result, the switching frequency fs can be varied to control the output voltage Vout when the bus voltage Vbus varies. However, the effect of changing the switching frequency fs on the output voltage Vout is non-linear. The resonance frequency fres represents the resonance frequency of the LLC stage.

现在转向图5,图示了作为图4所示的依赖于频率的曲线的反函数的校正因数G的图形表示。与该校正因数G相乘的如图4所示的依赖于频率的曲线产生LLC级的电压传输特性的依赖于频率的特性的直线。与校正因数G相乘的结果在图6中进行图示,诸如等于400伏的母线电压Vbus的直线610。在一个实施例中,校正因数G通过图5所示的折线校正因数(诸如五段折线校正因数)G′进行近似。Turning now to FIG. 5 , there is illustrated a graphical representation of the correction factor G as an inverse function of the frequency-dependent curve shown in FIG. 4 . The frequency-dependent curve shown in FIG. 4 multiplied by this correction factor G produces a straight line of the frequency-dependent characteristic of the voltage transfer characteristic of the LLC stage. The result of multiplying by the correction factor G is illustrated in FIG. 6 , such as a straight line 610 equal to a bus voltage Vbus of 400 volts. In one embodiment, the correction factor G is approximated by a broken line correction factor G' shown in FIG. 5, such as a five-segment broken line correction factor.

现在转向图7,图示了根据本发明的原理而构造的利用耦合至LLC级(诸如图3的LLC级320)的PFC级(诸如图2的PFC级201)形成的功率转换器的实施例的示图。该功率转换器接收输入电压并(经由桥式整流器)提供整流电压Vrect,该整流电压Vrect被PFC级201和LLC级320转换为输出电压Vout。利用由第一电阻器Rsensel和第二电阻器Rsense2形成的电阻分压器来感测输出电压Vout,并且所感测的输出电压被耦合至误差放大器340的运算放大器345的反相输入。误差放大器340在其反馈路径中包括电阻器电容器网络360以产生输出电压误差信号(也被称作“误差信号”)δV。Turning now to FIG. 7 , illustrated is an embodiment of a power converter formed using a PFC stage (such as PFC stage 201 of FIG. 2 ) coupled to an LLC stage (such as LLC stage 320 of FIG. 3 ) constructed in accordance with the principles of the present invention. diagram of . The power converter receives an input voltage and provides (via a bridge rectifier) a rectified voltage Vrect, which is converted by the PFC stage 201 and the LLC stage 320 to an output voltage Vout. The output voltage Vout is sensed using a resistive divider formed by the first resistor Rsensel and the second resistor Rsense2 , and the sensed output voltage is coupled to the inverting input of the operational amplifier 345 of the error amplifier 340 . Error amplifier 340 includes a resistor capacitor network 360 in its feedback path to generate an output voltage error signal (also referred to as "error signal") δV.

通过在反馈回路中采用非线性函数子系统335来控制LLC级320的开关频率fs以对其依赖于频率的响应进行补偿而获得了更大的反馈回路稳定性。依据非线性子系统335,校正因数G以折线校正因数(例如,五段折线校正因数G′)的形式进行近似,其被应用于输出电压误差信号δV以产生经校正的误差信号δV_cor。应当理解的是,光耦合器(诸如图3所示的光耦合器350)可以与误差放大器340进行协作以产生输出电压误差信号δV。在一个实施例中,在非线性函数子系统335中采用五段折线校正因数G′来减少由LLC级320产生的非线性反馈效应。该五段折线校正因数G′可以更一般地被称作折线校正因数。经校正的误差信号δV_cor被耦合至对LLC级320的开关频率fs进行控制的压控振荡器(VCO)336的输入。非线性函数子系统335和压控振荡器336形成LLC控制器333的至少一部分(同样参见图3)。Greater feedback loop stability is obtained by employing nonlinear function subsystem 335 in the feedback loop to control the switching frequency fs of LLC stage 320 to compensate for its frequency dependent response. According to the non-linear subsystem 335, the correction factor G is approximated in the form of a broken line correction factor (eg, a five-segment broken line correction factor G') which is applied to the output voltage error signal δV to generate a corrected error signal δV_cor. It should be understood that an optocoupler, such as optocoupler 350 shown in FIG. 3 , may cooperate with error amplifier 340 to generate the output voltage error signal δV. In one embodiment, a five-segment polyline correction factor G' is employed in nonlinear function subsystem 335 to reduce nonlinear feedback effects produced by LLC stage 320 . The five-segment broken line correction factor G' may be more generally referred to as a broken line correction factor. The corrected error signal δV_cor is coupled to the input of a voltage controlled oscillator (VCO) 336 that controls the switching frequency fs of the LLC stage 320 . Nonlinear function subsystem 335 and voltage controlled oscillator 336 form at least part of LLC controller 333 (see also FIG. 3 ).

开关频率fs还耦合至PFC控制器330,其产生用于PFC级201的主功率开关S1的栅极驱动信号GD(见图3)。PFC控制器330感测PFC级201的母线电压Vbus。PFC控制器330在较慢响应控制回路中对母线电压Vbus进行控制以将开关频率fs的平均值保持在理想开关频率fo=1/(2π·sqrt(Lk·Cr))附近以保持LLC级320高的功率转换效率。The switching frequency fs is also coupled to the PFC controller 330, which generates the gate drive signal GD for the main power switch S1 of the PFC stage 201 (see FIG. 3). The PFC controller 330 senses the bus voltage Vbus of the PFC stage 201 . The PFC controller 330 controls the bus voltage Vbus in a slower response control loop to keep the average value of the switching frequency fs around the ideal switching frequency fo=1/(2π·sqrt(Lk·Cr)) to maintain the LLC stage 320 High power conversion efficiency.

在又一方面,PFC控制器330简单地不时提升母线电压Vbus(例如,20毫秒内提升了6伏或7伏)以在误差信号δV中生成误差,或者相应地在经校正的误差信号δV_cor中生成误差,以检测轻载操作从而使得能够进入突发操作模式。如以下更为详细地描述的,在轻载情况下的突发模式的操作依据突发模式控制器370而产生功率转换效率的明显改进。PFC控制器330能够通过简单地提升其中结合误差放大器用来对母线电压Vbus进行调整的参考电压来提升母线电压Vbus。如以下参考图8所描述的,耦合至误差放大器332的输入的母线电压参考Vbus_ref被简单地提升以使得能够检测轻载操作。当误差信号δV或经校正的误差信号δV_cor与阈值水平相交时进入突发模式。In yet another aspect, the PFC controller 330 simply boosts the bus voltage Vbus from time to time (e.g., by 6 volts or 7 volts in 20 milliseconds) to generate an error in the error signal δV, or correspondingly in the corrected error signal δV_cor An error is generated to detect light load operation to enable entry into a burst mode of operation. As described in more detail below, burst mode operation under light load conditions results in a significant improvement in power conversion efficiency in accordance with the burst mode controller 370 . The PFC controller 330 is able to boost the bus voltage Vbus by simply boosting the reference voltage in which the error amplifier is used to adjust the bus voltage Vbus. As described below with reference to FIG. 8 , the bus voltage reference Vbus_ref coupled to the input of error amplifier 332 is simply boosted to enable detection of light load operation. Burst mode is entered when the error signal δV or the corrected error signal δV_cor crosses a threshold level.

在轻载情况下的操作中,母线电压Vbus由于LLC级320的降低损失而被降低至低值。当母线电压Vbus在短的时间段内被提升时,误差信号δV中所引起的变化(例如,减小)被用来确定是否进入突发模式。较高的母线电压Vbus降低LLC级320的开关频率。增加的母线电压Vbus和轻载使得误差信号δV充分下降,这被检测到进入突发模式。当输出电压Vout向下漂移至如由误差信号δV的提升所指示的阈值水平时退出突发模式。在突发操作模式中,PFC级201和LLC级320的开关动作均被关闭(例如,终止用来控制相应功率开关的栅极驱动信号的占空比D的交变特性)。In operation at light load conditions, the bus voltage Vbus is reduced to a low value due to the reduction loss of the LLC stage 320 . When the bus voltage Vbus is boosted for a short period of time, the resulting change (eg, decrease) in the error signal δV is used to determine whether to enter burst mode. A higher bus voltage Vbus reduces the switching frequency of the LLC stage 320 . Increased bus voltage Vbus and light loads cause the error signal δV to drop sufficiently, which is detected to enter burst mode. Burst mode is exited when the output voltage Vout drifts down to a threshold level as indicated by a rise in the error signal δV. In the burst mode of operation, the switching actions of both the PFC stage 201 and the LLC stage 320 are turned off (eg, the alternating nature of the duty cycle D of the gate drive signal used to control the respective power switches is terminated).

现在转向图8,图示了根据本发明的原理而构造的利用耦合至LLC级(诸如图3的LLC级320)的PFC级(诸如图2的PFC级201)以及控制器(包括图7的控制器325的各部分)形成的功率转换器的实施例的示图。PFC控制器330包括误差放大器(E/A)331,其具有耦合至由压控振荡器(VCO)336产生的开关频率fs的一个输入,优选地为反相输入。误差放大器331的另一个输入(优选地为非反相输入)耦合至频率参考fs_ref,这是LLC级320的期望的开关频率。在一个实施例中,期望的开关频率(类似于理想开关频率)为fo=1/(2π·sqrt(Lk·Cr))。误差放大器331产生母线电压参考Vbus_ref,其被误差放大器(E/A)332在较慢响应控制回路中用来对由PFC级201产生的母线电压Vbus进行调整。母线电压参考Vbus_ref表示向功率转换器提供高功率转换效率的母线电压Vbus的期望电压电平。以这种方式,控制器325对由PFC级201产生的母线电压Vbus进行调整以产生LLC级320的平均开关频率fs,其导致LLC级320的高功率转换效率。误差放大器340被保持以利用快速响应控制回路对功率转换器的输出电压Vout进行调整以使得功率转换器能够利用降低的纹波电压电平对输出电压Vout进行紧凑调整,该纹波电压将以其它方式由PFC级201的母线电压Vbus上的纹波电压产生。Turning now to FIG. 8 , there is illustrated a diagram utilizing a PFC stage (such as PFC stage 201 of FIG. 2 ) coupled to an LLC stage (such as LLC stage 320 of FIG. 3 ) and a controller (comprising the Parts of the controller 325) form a diagram of an embodiment of a power converter. PFC controller 330 includes an error amplifier (E/A) 331 having one input, preferably an inverting input, coupled to a switching frequency fs generated by a voltage controlled oscillator (VCO) 336 . Another input of error amplifier 331 , preferably a non-inverting input, is coupled to frequency reference fs_ref, which is the desired switching frequency of LLC stage 320 . In one embodiment, the desired switching frequency (similar to the ideal switching frequency) is fo = 1/(2π·sqrt(Lk·Cr)). Error amplifier 331 generates bus voltage reference Vbus_ref, which is used by error amplifier (E/A) 332 in a slower response control loop to regulate bus voltage Vbus generated by PFC stage 201 . The bus voltage reference Vbus_ref represents a desired voltage level of the bus voltage Vbus to provide high power conversion efficiency to the power converter. In this way, the controller 325 adjusts the bus voltage Vbus generated by the PFC stage 201 to generate an average switching frequency fs of the LLC stage 320 , which results in a high power conversion efficiency of the LLC stage 320 . The error amplifier 340 is maintained to regulate the output voltage Vout of the power converter with a fast response control loop to enable tight regulation of the output voltage Vout by the power converter with a reduced ripple voltage level that would otherwise be The mode is generated by the ripple voltage on the bus voltage Vbus of the PFC stage 201 .

因此,已经在此对用于功率转换器的控制器进行了介绍。在一个实施例中,该控制器包括LLC控制器,其被配置为接收来自误差放大器的误差信号以控制该功率转换器的LLC级(例如,LLC谐振降压级)的开关频率而对其输出电压进行调整。该控制器还包括PFC控制器,其被配置为对母线电压进行控制,该母线电压由该功率转换器的PFC级(例如,PFC升压级)产生并且被提供至LLC级以使得其平均开关频率基本上被保持在期望的开关频率(例如,基本上等于LLC级的谐振频率)。与LLC级相关联的控制回路可以具有比与PFC级相关联的控制回路更快的响应。LLC控制器可以包括非线性函数子系统,其被配置为向误差信号应用校正因数(例如,由折线校正因数近似的)以产生经校正的误差信号。LLC控制器可以包括压控振荡器,其被配置为接收经校正的误差信号以对LLC级的开关频率进行控制。Accordingly, a controller for a power converter has been described herein. In one embodiment, the controller includes an LLC controller configured to receive an error signal from an error amplifier to control the switching frequency of an LLC stage (eg, LLC resonant buck stage) of the power converter to output voltage is adjusted. The controller also includes a PFC controller configured to control a bus voltage generated by a PFC stage (eg, a PFC boost stage) of the power converter and provided to the LLC stage so that it switches on average The frequency is maintained substantially at the desired switching frequency (eg, substantially equal to the resonant frequency of the LLC stage). The control loop associated with the LLC stage may have a faster response than the control loop associated with the PFC stage. The LLC controller may include a nonlinear function subsystem configured to apply a correction factor (eg, approximated by a broken line correction factor) to the error signal to produce a corrected error signal. The LLC controller may include a voltage controlled oscillator configured to receive the corrected error signal to control the switching frequency of the LLC stage.

PFC控制器被配置为提升母线电压以在误差信号中生成误差来检测功率转换器的轻载操作。误差放大器耦合至电阻分压器,该电阻分压器被配置为感测输出电压并且将所感测的输出电压提供至误差放大器的运算放大器以产生误差信号。PFC级可以包括至少一个误差放大器,其被配置为对作为LLC级的开关频率和期望的开关频率的函数的母线电压进行控制。该控制器还可以包括突发模式控制器,其被配置为使得该功率转换器在轻载情况下和/或在误差信号与突发阈值水平相交时进入突发操作模式。该控制器还可以耦合至被配置为感测输出电压的电阻分压器,以及耦合至该电阻分压器的第一感测开关和第二感测开关,其被配置为在该功率转换器进入突发操作模式时减少功率损耗。The PFC controller is configured to boost the bus voltage to generate an error in the error signal to detect light load operation of the power converter. The error amplifier is coupled to a resistive voltage divider configured to sense the output voltage and provide the sensed output voltage to an operational amplifier of the error amplifier to generate an error signal. The PFC stage may include at least one error amplifier configured to control the bus voltage as a function of the switching frequency of the LLC stage and the desired switching frequency. The controller may also include a burst mode controller configured to cause the power converter to enter a burst mode of operation under light load conditions and/or when the error signal crosses a burst threshold level. The controller may also be coupled to a resistive voltage divider configured to sense an output voltage, and a first sensing switch and a second sensing switch coupled to the resistive voltage divider configured to sense the output voltage in the power converter. Reduce power loss when entering burst mode of operation.

现在转向图9,图示了依据本发明的原理的被配置为对功率转换器的突发操作模式进行管理的突发模式控制器(诸如图7和图8的突发模式控制器370)的实施例的示意图。控制器325的操作在其间被无效(例如,控制器不输出PFC级或LLC级的栅极驱动信号)的时间长度(或者时间间隔或窗口)可以被用作用于确定输出功率的相当准确的指示器。该时间间隔可以被用来确定突发模式的出口以准备随后可能的瞬变负载步骤。使用跨斜坡电压定时电容器Cramp所产生的电压来测量控制器325的关断时间。Turning now to FIG. 9 , there is illustrated a burst mode controller, such as burst mode controller 370 of FIGS. 7 and 8 , configured to manage a burst mode of operation of a power converter in accordance with the principles of the present invention. Example schematic. The length of time (or time interval or window) during which the operation of the controller 325 is disabled (e.g., the controller does not output a gate drive signal for the PFC stage or LLC stage) can be used as a fairly accurate indicator for determining output power device. This time interval can be used to determine the exit of burst mode in preparation for a possible subsequent transient load step. The off-time of the controller 325 is measured using the voltage developed across the ramp voltage timing capacitor Cramp.

突发模式控制器370耦合至由误差放大器340产生的误差信号δV以设置突发模式控制信号Fon和电压提升信号Fves。误差信号δV与功率转换器的输出电压Vout相关并且提供其指示器。当突发模式控制信号Fon被设置为高电平时,功率转换器的PFC级201和LLC级320的开关动作被使能。相反,当突发模式控制信号Fon为低电平时,功率转换器的PFC级201和LLC级320的开关动作被无效。电压提升信号Fves被用来简单升高功率转换器的经过调整的输出电压Vout从而能够检测到低负载功率以使得能够进入突发操作模式。The burst mode controller 370 is coupled to the error signal δV generated by the error amplifier 340 to set the burst mode control signal Fon and the voltage boost signal Fves. The error signal δV is related to and provides an indicator of the output voltage Vout of the power converter. When the burst mode control signal Fon is set to a high level, the switching action of the PFC stage 201 and the LLC stage 320 of the power converter is enabled. On the contrary, when the burst mode control signal Fon is at low level, the switching actions of the PFC stage 201 and the LLC stage 320 of the power converter are disabled. The voltage boost signal Fves is used to simply boost the regulated output voltage Vout of the power converter so that low load power can be detected to enable entry into the burst mode of operation.

利用第一比较器920和第二比较器930来形成突发模式控制器370,该第一比较器920具有耦合至误差信号δV的非反相输入和耦合至高突发阈值水平Vburst_high(第二突发阈值水平)的反相输入,而该第二比较器930具有耦合至误差信号δV的反相输入和耦合至低突发阈值水平Vburst_low(第一突发阈值水平)的非反相输入。比较器920、930的输出耦合至第一置位-复位触发器940和第二置位-复位触发器970的“置位”输入和“复位”输入之一。第一置位-复位触发器940的“Q”输出设置突发模式控制信号Fon。比较器920、930以及第一置位-复位触发器940形成突发模式控制器370的突发模式发起电路的至少一部分。The burst mode controller 370 is formed using a first comparator 920 having a non-inverting input coupled to the error signal δV and a second comparator 930 coupled to the high burst threshold level Vburst_high (second burst threshold level), while the second comparator 930 has an inverting input coupled to the error signal δV and a non-inverting input coupled to the low burst threshold level Vburst_low (first burst threshold level). The outputs of the comparators 920 , 930 are coupled to one of the “set” and “reset” inputs of the first set-reset flip-flop 940 and the second set-reset flip-flop 970 . The "Q" output of the first set-reset flip-flop 940 sets the burst mode control signal Fon. The comparators 920 , 930 and the first set-reset flip-flop 940 form at least part of a burst mode initiation circuit of the burst mode controller 370 .

电流源950产生电流以对斜坡电压定时电容器Cramp充电,其电容器电压Vcap耦合至第三比较器960的非反相输入。第三比较器960的反相输入耦合至电容器电压阈值V_cap_thresh。由第一置位-复位触发器940产生的突发模式控制信号Fon还耦合至斜坡开关(例如,n沟道MOSFET)Qramp的栅极。当突发模式控制信号Fon为高电平时,斜坡开关Qramp对斜坡电压定时电容器Cramp放电。第三比较器960的输出信号990耦合至第二置位-复位触发器970的置位输入。第二置位-复位触发器970的置位输入还通过与(AND)门995耦合至定时器980。定时器980周期性地将电压提升信号Fves设置为高电平(例如,每40毫秒)。当电压提升信号Fves为高电平时,误差放大器340(见图3、图7和图8)的运算放大器345的参考电压Vref被少量升高(例如,升高了足以将输出电压Vout升高几伏的量),从而第二比较器930能够检测输出电压Vout的高电压电平。电流源950、第三比较器960、第二置位-复位触发器970、斜坡电压定时电容器Cramp和斜坡开关Qramp形成突发模式控制器370的电压提升电路的至少一部分。如以下更为详细描述的,电流源950、斜坡电压定时电容器Cramp和比较器960检测突发操作模式的时间窗口是否过期。The current source 950 generates current to charge the ramp voltage timing capacitor Cramp, whose capacitor voltage Vcap is coupled to the non-inverting input of the third comparator 960 . The inverting input of the third comparator 960 is coupled to the capacitor voltage threshold V_cap_thresh. The burst mode control signal Fon generated by the first set-reset flip-flop 940 is also coupled to the gate of the ramp switch (eg, n-channel MOSFET) Qramp. When the burst mode control signal Fon is at a high level, the ramp switch Qramp discharges the ramp voltage timing capacitor Cramp. The output signal 990 of the third comparator 960 is coupled to the set input of the second set-reset flip-flop 970 . The set input of the second set-reset flip-flop 970 is also coupled to the timer 980 through an AND gate 995 . The timer 980 periodically sets the voltage boost signal Fves to a high level (eg, every 40 milliseconds). When the voltage boost signal Fves is at a high level, the reference voltage Vref of the operational amplifier 345 of the error amplifier 340 (see FIGS. volts), so that the second comparator 930 can detect a high voltage level of the output voltage Vout. The current source 950 , the third comparator 960 , the second set-reset flip-flop 970 , the ramp voltage timing capacitor Cramp and the ramp switch Qramp form at least part of the voltage boost circuit of the burst mode controller 370 . As described in more detail below, current source 950, ramp voltage timing capacitor Cramp, and comparator 960 detect whether the time window for the burst mode of operation has expired.

突发模式控制器370利用以下逻辑进行操作。如果误差信号δv大于高突发阈值水平Vburst_high,则突发模式控制信号Fon被设置为高电平。误差信号δV随后在输出电压Vout降低时升高至高电平。如果误差信号δV小于低突发阈值水平Vburst_low,则突发模式控制信号Fon被设置为低电平以进入突发操作模式。相反,误差信号δV在输出电压Vout增加至高电平时降低至低电平,这将第二比较器930的输出设置为高电平。因此,误差信号在通常形成于功率转换器的初级侧和次级侧之间的隔离势垒(见图3的变压器T1)的初级侧提供了输出电压Vout的指示器,并且误差信号δV相应地对突发模式控制信号Fon进行控制。如果误差信号δV小于低突发阈值水平Vburst_low,则电压提升信号Fves也被设置为低电平。The burst mode controller 370 operates using the following logic. If the error signal δv is greater than the high burst threshold level Vburst_high, the burst mode control signal Fon is set to a high level. The error signal δV then rises to a high level as the output voltage Vout decreases. If the error signal δV is less than the low burst threshold level Vburst_low, the burst mode control signal Fon is set low to enter the burst mode of operation. On the contrary, the error signal δV decreases to a low level when the output voltage Vout increases to a high level, which sets the output of the second comparator 930 to a high level. Thus, the error signal provides an indicator of the output voltage Vout at the primary side of the isolation barrier (see transformer T1 of FIG. 3 ) that is typically formed between the primary and secondary sides of a power converter, and the error signal δV corresponds accordingly The burst mode control signal Fon is controlled. If the error signal δV is less than the low burst threshold level Vburst_low, the voltage boost signal Fves is also set to a low level.

电压提升信号Fves在跨斜坡电压定时电容器Cramp的电容器电压Vcap大于电容器电压阈值V_cap_thresh的情况下被设置为高电平。跨斜坡电压定时电容器Cramp的高电压被认为是耦合至功率转换器的输出的低功率负载的指示,由此使得能够进入突发操作模式。电压提升信号Fves还响应于来自定时器980的信号而被设置为高电平,这提供了一种用于对耦合至功率转换器的输出的负载进行测试的机制。The voltage boost signal Fves is set to a high level if the capacitor voltage Vcap across the ramp voltage timing capacitor Cramp is greater than the capacitor voltage threshold V_cap_thresh. A high voltage across the ramp voltage timing capacitor Cramp is considered an indication of a low power load coupled to the output of the power converter, thereby enabling entry into the burst mode of operation. Voltage boost signal Fves is also set high in response to the signal from timer 980, which provides a mechanism for testing the load coupled to the output of the power converter.

现在转向图10,图示了在依据本发明的原理的功率转换器内所产生的示例性波形的图形表示。继续参考之前的附图,如由用于该功率转换器的功率系的开关的栅极驱动信号的占空比D的周期性开关所指示的,最初假设功率转换器向耦合至其输出的负载提供实质性功率。该功率转换器的开关的周期性开关由突发模式控制信号Fon使能。误差信号δV假设为高突发阈值水平Vburst_high和低突发阈值水平Vburst_low之间的数值以指示输出电压Vout处于可接受的电压调整范围内。电容器电压Vcap由于突发模式控制信号Fon为高电平而保持为零伏,这导通斜坡开关Qramp,使斜坡电压定时电容器Cramp短路。Turning now to FIG. 10 , there is illustrated a graphical representation of exemplary waveforms generated within a power converter in accordance with the principles of the invention. Continuing to refer to the previous figures, it is initially assumed that the power converter supplies a load coupled to its output as indicated by the periodic switching of the duty cycle D of the gate drive signal for the switches of the power converter's power train. Provides substantial power. Periodic switching of the switches of the power converter is enabled by the burst mode control signal Fon. The error signal δV assumes a value between the high burst threshold level Vburst_high and the low burst threshold level Vburst_low to indicate that the output voltage Vout is within an acceptable voltage regulation range. The capacitor voltage Vcap remains at zero volts due to the high level of the burst mode control signal Fon, which turns on the ramp switch Qramp, shorting the ramp voltage timing capacitor Cramp.

在时间T0,定时器980将第二置位-复位触发器970的输出设置为高电平,这将电压提升信号Fves设置为高电平并且升高误差放大器340(见图7、图8和图11)的运算放大器345的参考电压Vref。电压提升信号Fves发起对耦合至功率转换器的输出的轻载的测试。作为其响应,升高功率转换器的输出电压Vout,其最终在时间T1将误差信号δV降低至低突发阈值水平Vburst_low。这使得突发模式控制信号Fon被重置为低电平(以进入突发操作模式),并且电压提升信号Fves也被设置为低电平。如由占空比D的缺失所指示的,停止功率转换器的开关动作。电容器电压Vcap斜坡上升并且如果功率转换器上的负载充分低,则其在时间T2与电容器电压阈值V_cap_thresh相交,这使得电压提升信号Fves和突发模式控制信号Fon被设置为高电平。因此,突发操作模式的时间窗口处于时间T1和时间T2之间。因此,电压提升信号Fves由于时间窗口在误差信号δV与高突发阈值水平Vburst_high相交之前过期而被设置为高电平以升高功率转换器的输出电压Vout。可替换地,定时器980能够使得电压提升信号Fves被设置为高电平,并且相应地设置要提升的参考电压Vref。因此,使用误差信号δV对功率转换器的输出电压Vout进行间接感测并且采用由用于控制突发操作模式的时间间隔所测量的输出信号Vout的斜率来估计功率转换器的输出功率。At time T0, timer 980 sets the output of second set-reset flip-flop 970 high, which sets voltage boost signal Fves high and boosts error amplifier 340 (see FIGS. 7, 8 and The reference voltage Vref of the operational amplifier 345 of FIG. 11 ). The voltage boost signal Fves initiates a test for a light load coupled to the output of the power converter. In response thereto, the output voltage Vout of the power converter is raised, which eventually reduces the error signal δV to the low burst threshold level Vburst_low at time T1. This causes the burst mode control signal Fon to be reset low (to enter the burst operation mode), and the voltage boost signal Fves is also set low. As indicated by the absence of duty cycle D, the switching action of the power converter is stopped. Capacitor voltage Vcap ramps up and if the load on the power converter is sufficiently low, it crosses capacitor voltage threshold V_cap_thresh at time T2, which causes voltage boost signal Fves and burst mode control signal Fon to be set high. Therefore, the time window for the burst mode of operation is between time T1 and time T2. Therefore, the voltage boost signal Fves is set high to boost the output voltage Vout of the power converter due to the time window expiring before the error signal δV crosses the high burst threshold level Vburst_high. Alternatively, the timer 980 can cause the voltage boost signal Fves to be set to a high level, and accordingly set the reference voltage Vref to be boosted. Therefore, the output voltage Vout of the power converter is indirectly sensed using the error signal δV and the slope of the output signal Vout measured by the time interval used to control the burst mode of operation is used to estimate the output power of the power converter.

输出电压Vout的斜率的指示器由图9所示的第三比较器960所感测的时间间隔(时间窗口)来确定。如果电容器电压Vcap在时间T1和时间T2之间(例如,当突发模式控制信号Fon为低电平而指示输出电压Vout处于可接受的电压调整范围之内时)并不与电容器电压阈值v_cap_thresh相交,则输出电压Vout的斜率充分小而发信号通知进入突发操作模式。因此,功率转换器上的负载被估计为小于预定的低阈值水平。例如,如果功率转换器额定提供60瓦的负载,则预定的低阈值水平可以为5瓦并且突发模式控制器370通过以上所描述的操作来确定输出功率小于5瓦。换句话说,突发模式控制器370结合输出电压Vout的斜率来估计输出功率。The indicator of the slope of the output voltage Vout is determined by the time interval (time window) sensed by the third comparator 960 shown in FIG. 9 . If the capacitor voltage Vcap does not cross the capacitor voltage threshold v_cap_thresh between time T1 and time T2 (for example, when the burst mode control signal Fon is low indicating that the output voltage Vout is within the acceptable voltage regulation range) , then the slope of the output voltage Vout is sufficiently small to signal entry into the burst mode of operation. Accordingly, the load on the power converter is estimated to be less than a predetermined low threshold level. For example, if the power converter is rated to supply a load of 60 watts, the predetermined low threshold level may be 5 watts and the burst mode controller 370 determines that the output power is less than 5 watts through the operations described above. In other words, the burst mode controller 370 estimates the output power in conjunction with the slope of the output voltage Vout.

相反地,如果电容器电压Vcap在时间T2之前(例如,当突发模式控制信号Fon为低电平而指示输出电压Vout低于可接受的电压调整范围时)与电容器电压阈值V_cap_thresh相交,则输出电压Vout的斜率充分高而发信号通知从突发操作模式退出(即,使能功率转换器的开关动作)。因此,功率转换器上的负载被估计大于预定的低阈值水平。例如,如果功率转换器额定提供60瓦的负载,则预定的低阈值水平可以为5瓦并且突发模式控制器370通过以上所描述的操作来确定输出功率大于5瓦。换句话说,突发模式控制器370结合输出电压Vout的斜率来估计输出功率。Conversely, if the capacitor voltage Vcap crosses the capacitor voltage threshold V_cap_thresh before time T2 (for example, when the burst mode control signal Fon is low indicating that the output voltage Vout is below the acceptable voltage regulation range), the output voltage The slope of Vout is sufficiently high to signal an exit from the burst mode of operation (ie, enable switching of the power converter). Accordingly, the load on the power converter is estimated to be greater than a predetermined low threshold level. For example, if the power converter is rated to supply a load of 60 watts, the predetermined low threshold level may be 5 watts and the burst mode controller 370 determines that the output power is greater than 5 watts through the operations described above. In other words, the burst mode controller 370 estimates the output power in conjunction with the slope of the output voltage Vout.

结果是充分高的输出电压Vout将突发模式控制信号Fon设置为低电平,并且低输出电压Vout将突发模式控制信号Fon设置为高电平。定时器980周期性地将电压提升信号Fves设置为高电平,并且跨斜坡电压定时电容器Cramp所产生的充分高的电容器电压Vcap也将电压提升信号Fves设置为高电平。因此,功率转换器的突发操作模式的时间间隔被用来确定输出电压Vout的斜率以对该功率转换器的输出功率进行估计。耦合至功率转换器的输出的低功率负载被检测而使得该功率转换器能够进入突发操作模式。与电容器电压阈值V_cap_thresh相交的电容器电压Vcap被用作功率转换器的输出电压Vout的低斜率的指示器,并且相应地用作低功率负载的指示器。The result is that a sufficiently high output voltage Vout sets the burst mode control signal Fon low and a low output voltage Vout sets the burst mode control signal Fon high. The timer 980 periodically sets the voltage boost signal Fves high, and the sufficiently high capacitor voltage Vcap generated across the ramp voltage timing capacitor Cramp also sets the voltage boost signal Fves high. Therefore, the time interval of the burst mode of operation of the power converter is used to determine the slope of the output voltage Vout to estimate the output power of the power converter. A low power load coupled to the output of the power converter is detected enabling the power converter to enter a burst mode of operation. The capacitor voltage Vcap crossing the capacitor voltage threshold V_cap_thresh is used as an indicator of a low slope of the output voltage Vout of the power converter, and accordingly of a low power load.

现在转向图11,图示了根据本发明的原理而构造的利用耦合至功率转换器(例如,见图3、图7和图8的功率转换器)的输出电压Vout的第一电阻器Rsensel和第二电阻器Rsense2形成的电阻分压器的实施例的示图。该电阻分压器现在通过第一感测开关(例如,n沟道MOSFET)Qsense2耦合至运算放大器345的非反相输入,并且通过第二感测开关(例如,n沟道MOSFET)Qsensel耦合至接地端。突发模式控制信号Fon在功率转换器如突发模式控制信号Fon为低电平所指示的处于突发操作模式时打开第一感测开关Qsensel和第二感测开关Qsense2以减少功率损耗。Turning now to FIG. 11 , there is illustrated a first resistor Rsensel constructed in accordance with the principles of the present invention utilizing an output voltage Vout coupled to a power converter (see, for example, the power converters of FIGS. 3 , 7 and 8 ) and Diagram of an embodiment of a resistive voltage divider formed by the second resistor Rsense2. This resistive divider is now coupled to the non-inverting input of operational amplifier 345 through a first sense switch (e.g., n-channel MOSFET) Qsense2, and to ground terminal. The burst mode control signal Fon turns on the first sense switch Qsensel and the second sense switch Qsense2 to reduce power consumption when the power converter is in the burst operation mode as indicated by the burst mode control signal Fon being low.

用来对功率转换器的输出电压Vout进行调整的参考电压Vref通过电阻器R1耦合至电压源V1,并且通过另一电阻器R2耦合至电压提升信号Fves。以这种方式,电压提升信号Fves在电压提升信号Fves被设置为高电平时提升参考电压Vref。A reference voltage Vref used to regulate the output voltage Vout of the power converter is coupled to a voltage source V1 through a resistor R1 and coupled to a voltage boost signal Fves through another resistor R2. In this way, the voltage boost signal Fves boosts the reference voltage Vref when the voltage boost signal Fves is set to a high level.

现在转向图12,图示了根据本发明的原理而构造的可在突发模式控制器370中采用的电压提升电路的一部分的实施例的示图,其用于产生指示功率转换器(例如,见图3、图7和图8的功率转换器)的输出电压Vout的斜率的斜率信号Vslope。图12的电压提升电路的该部分是图9所示的突发模式控制器370的电流源950、第三比较器960、斜坡开关Qramp和斜坡电压定时电容器Cramp的替换形式。图12的电压提升电路的该部分替代图9所示的误差信号δv来感测输出电压Vout。电阻器Rrip通过电容器Crip耦合至输出电压Vout以感测输出电压Vout的导数。利用低通滤波器对该导数进行滤波以产生经滤波的斜率信号Vslope,利用耦合至滤波电容器Cfilter的滤波电阻器Rfilter来形成该低通滤波器。在一个实施例中,利用耦合至电容器Crip的电阻器Rrip形成的电路的时间常数是功率转换器的开关周期的倍数(例如,开关周期的10倍)。在一个实施例中,利用耦合至滤波电容器Cfilter的滤波电阻器Rfilter形成的低通滤波器的时间常数是功率转换器的开关周期的约数(例如,开关周期的0.01倍)。Turning now to FIG. 12 , illustrated is a diagram of an embodiment of a portion of a voltage boost circuit that may be employed in a burst mode controller 370 , constructed in accordance with the principles of the present invention, for generating an indicative power converter (e.g., See the slope signal Vslope of the slope of the output voltage Vout of the power converter in FIG. 3 , FIG. 7 and FIG. 8 . This portion of the voltage boost circuit of FIG. 12 is an alternative to the current source 950, third comparator 960, ramp switch Qramp, and ramp voltage timing capacitor Cramp of the burst mode controller 370 shown in FIG. This portion of the voltage boost circuit of FIG. 12 senses the output voltage Vout instead of the error signal δv shown in FIG. 9 . The resistor Rrip is coupled to the output voltage Vout through the capacitor Crip to sense the derivative of the output voltage Vout. The derivative is filtered with a low pass filter formed with a filter resistor Rfilter coupled to a filter capacitor Cfilter to produce a filtered slope signal Vslope. In one embodiment, the time constant of the circuit formed with resistor Rrip coupled to capacitor Crip is a multiple of the switching period of the power converter (eg, 10 times the switching period). In one embodiment, the time constant of the low pass filter formed with the filter resistor Rfilter coupled to the filter capacitor Cfilter is a submultiple (eg, 0.01 times the switching period) of the power converter.

在互补间隔1-D期间,斜率信号Vslope可以被用来估计耦合至功率转换器的输出的输出或负载功率。该斜率信号Vslope耦合至比较器1220的非反相输入,并且比较器1220的反相输入耦合至斜率参考电压Vrefl。比较器1220的输出信号1230耦合至与(AND)门1240的输入,并且与(AND)门1240的另一输入耦合至栅极驱动信号GDM2,其表示在LLC级320(见图3)的互补间隔1-D期间至辅助功率开关M2的栅极驱动信号。与(AND)门1240的输出对应于输出信号990,其被用于参考图9图示并描述的第二置位-复位触发器970来设置电压提升信号Fves。During the complementary interval 1-D, the slope signal Vslope can be used to estimate the output or load power coupled to the output of the power converter. The slope signal Vslope is coupled to a non-inverting input of comparator 1220, and the inverting input of comparator 1220 is coupled to slope reference voltage Vrefl. The output signal 1230 of the comparator 1220 is coupled to an input of an AND gate 1240, and the other input of the AND gate 1240 is coupled to the gate drive signal GDM 2 , which is represented at the LLC stage 320 (see FIG. 3 ). Gate drive signal to auxiliary power switch M2 during complementary interval 1-D. The output of AND gate 1240 corresponds to output signal 990 which is used to set voltage boost signal Fves by second set-reset flip-flop 970 illustrated and described with reference to FIG. 9 .

输出电压Vout的电压斜率dVout/dt通过以下等式与负载功率相关:The voltage slope dVout/dt of the output voltage Vout is related to the load power by the following equation:

dVout dt = - Vslope Rrip · Crip dVout dt = - V slope Rrip · Crip and

PloadUpload == IloadIload ·&Center Dot; VoutVout == -- VoutVout ·· CoutCout ·&Center Dot; dVoutdVout dtdt == -- VoutVout ·&Center Dot; VslopeV slope ·&Center Dot; CoutCout RripRrip ·&Center Dot; CripCrip

其中Cout是如图3所示的功率转换器的输出滤波电容器。Where Cout is the output filter capacitor of the power converter shown in Figure 3 .

输出信号1230可以被用来估计耦合至功率转换器的输出的负载功率,并且如果负载功率充分轻,则输出信号1230可以被用作另一种机制而使得能够进入突发操作模式(例如,通过设置电压提升信号Fves为高电平)。输出信号1230可以被用于其它开关模式的功率转换器来估计负载功率,并且不限于使得利用PFC级201和LLC级320形成的功率转换器能够进入突发操作模式。The output signal 1230 can be used to estimate the load power coupled to the output of the power converter, and if the load power is sufficiently light, the output signal 1230 can be used as another mechanism to enable entry into the burst mode of operation (e.g., by Set the voltage boost signal Fves to a high level). The output signal 1230 may be used by other switch mode power converters to estimate load power and is not limited to enabling a power converter formed with the PFC stage 201 and the LLC stage 320 to enter a burst mode of operation.

如以上就突发操作模式所提到的,功率转换器的功率损失取决于用于功率开关的栅极驱动信号以及通常基本上不随负载变化的其它持续功率损失。这些功率损失一般通过使用突发操作模式在非常低的功率水平处得以解决,其中在一段时间内(例如,一秒)使得控制器(诸如之前附图中的控制器325)无效随后为短时间(例如,10毫秒(ms))的高功率操作以提供具有低损耗的低平均输出功率。如这里所描述的控制器可以采用突发操作模式的时间间隔来估计功率转换器的输出(或负载)功率。As mentioned above with respect to the burst mode of operation, the power loss of the power converter depends on the gate drive signals for the power switches and other continuous power losses that generally do not vary substantially with load. These power losses are typically addressed at very low power levels by using a burst mode of operation in which a controller (such as controller 325 in the previous figure) is disabled for a period of time (e.g., one second) followed by a short period of time. High power operation (eg, 10 milliseconds (ms)) to provide low average output power with low losses. A controller as described herein may employ the time interval of the burst mode of operation to estimate the output (or load) power of the power converter.

因此,这里已经对用于随功率转换器使用的突发模式控制器进行了介绍。在一个实施例中,该突发模式控制器包括突发模式发起电路,其被配置为在表示功率转换器的输出电压的信号与第一突发阈值水平相交时发起突发操作模式。该突发模式控制器还包括电压提升电路,其被配置为在时间窗口在表示功率转换器的输出电压的信号与第二突发阈值水平相交之前过期的情况下提供电压提升信号以升高输出电压。该突发模式发起电路还被配置为在表示功率转换器的输出电压的信号与第二突发阈值水平相交时终止突发操作模式。Therefore, a burst mode controller for use with a power converter has been described here. In one embodiment, the burst mode controller includes a burst mode initiating circuit configured to initiate a burst mode of operation when a signal representative of an output voltage of the power converter crosses a first burst threshold level. The burst mode controller also includes a voltage boost circuit configured to provide a voltage boost signal to boost the output if a time window expires before the signal representative of the output voltage of the power converter crosses the second burst threshold level Voltage. The burst mode initiating circuit is also configured to terminate the burst mode of operation when the signal representative of the output voltage of the power converter crosses a second burst threshold level.

该突发模式发起电路可以包括比较器,其被配置为将表示功率转换器的输出电压的信号与第一突发阈值水平进行比较。该突发模式发起电路还可以包括触发器,其被配置为在表示功率转换器的输出电压的信号与第一突发阈值水平相交时设置突发模式控制信号以发起突发操作模式。该电压提升电路可以包括电流源、斜坡电压定时电容器以及被配置为检测时间窗口是否过期的比较器。该电压提升电路还可以包括触发器,其被配置为设置电压提升信号以升高输出电压。该电压提升信号被配置为升高误差放大器的参考电压,该误差放大器被配置为对功率转换器的输出电压进行控制。该突发模式发起电路被配置为在表示功率转换器的输出电压的信号与第一突发阈值水平相交时使得电压提升信号无效。该突发模式控制器还可以包括定时器,其被配置为发起(和/或周期性地发起)电压提升信号以升高输出电压。The burst mode initiating circuit may include a comparator configured to compare a signal representative of the output voltage of the power converter to a first burst threshold level. The burst mode initiating circuit may also include a flip-flop configured to set the burst mode control signal to initiate the burst mode of operation when the signal representative of the output voltage of the power converter crosses the first burst threshold level. The voltage boost circuit may include a current source, a ramp voltage timing capacitor, and a comparator configured to detect expiration of a time window. The voltage boost circuit may also include a flip-flop configured to set a voltage boost signal to boost the output voltage. The voltage boost signal is configured to boost a reference voltage of an error amplifier configured to control the output voltage of the power converter. The burst mode initiating circuit is configured to deassert the voltage boost signal when the signal representative of the output voltage of the power converter crosses a first burst threshold level. The burst mode controller may also include a timer configured to initiate (and/or periodically initiate) a voltage boost signal to boost the output voltage.

该控制器和相关方法可以被实施为硬件(包含在包括诸如专用集成电路之类的集成电路的一个或多个芯片中),或者可以被实施为用于由处理器(例如,数字信号处理器)依据存储器来执行的软件或固件。特别地,在固件或软件的情况下,示例性实施例可以被提供为包括计算机可读介质的计算机程序产品,该计算机可读介质在其上包含计算机程序代码(即,软件或固件)以供处理器执行。The controller and associated methods may be implemented as hardware (contained in one or more chips including an integrated circuit such as an application specific integrated circuit), or may be implemented as a ) software or firmware executed from memory. In particular, in the case of firmware or software, exemplary embodiments may be provided as a computer program product comprising a computer-readable medium having computer program code (i.e., software or firmware) embodied thereon for providing Processor executes.

构成各个实施例的程序或代码段可以被存储在计算机可读介质中。例如,包括存储在计算机可读介质(例如,非瞬时计算机可读介质)中的程序代码的计算机程序产品可以形成各个实施例。“计算机可读介质”可以包括能够存储或传输信息的任意介质。计算机可读介质的示例包括电子电路、半导体存储器设备、只读存储器(ROM)、闪存、可擦除ROM(EROM)、软盘、光盘(CD)-ROM等。Programs or code segments constituting the various embodiments can be stored in computer-readable media. For example, a computer program product comprising program code stored on a computer-readable medium (eg, a non-transitory computer-readable medium) may form various embodiments. "Computer-readable medium" may include any medium that can store or transmit information. Examples of computer readable media include electronic circuits, semiconductor memory devices, read only memory (ROM), flash memory, erasable ROM (EROM), floppy disks, compact disk (CD)-ROMs, and the like.

本领域技术人员应当理解的是,之前所描述的包括包含位于直线核心体上的U形核心体的磁性结构的功率转换器以及形成该功率转换器的相关方法的实施例仅出于说明性的目的而被提交。虽然已经在功率转换器的环境中对磁性结构进行了描述,但是该磁性结构还可以被应用于其它系统,诸如但不限于功率放大器或电机控制器。Those skilled in the art will understand that the previously described embodiments of a power converter including a magnetic structure comprising a U-shaped core on a rectilinear core and associated methods of forming the power converter are for illustrative purposes only. submitted for the purpose. Although the magnetic structure has been described in the context of a power converter, the magnetic structure may also be applied to other systems such as, but not limited to, power amplifiers or motor controllers.

为了更好地理解功率转换器,参见Rudolph P.Severns和GordonBloom的“Modern DC-to-DC Power Switch-mode Power ConverterCircuits”(纽约州纽约市Van Nostrand Reinhold公司,1985),以及J.G.Kassakian、M.F.Schlecht和G.C.Verghese的“Principles of PowerElectronics”(Addison-Wesley,1991)。上述参考文献通过引用全文结合于此。For a better understanding of power converters, see "Modern DC-to-DC Power Switch-mode Power Converter Circuits" by Rudolph P. Severns and Gordon Bloom (Van Nostrand Reinhold Company, New York, NY, 1985), and J.G. Kassakian, M.F. Schlecht and "Principles of Power Electronics" by G.C. Verghese (Addison-Wesley, 1991). The above references are hereby incorporated by reference in their entirety.

而且,虽然已经对本发明及其优势进行了详细描述,但是应当理解的是,可以在其中进行各种改变、替换和变化而并不背离如由所附权利要求限定的本发明的精神和范围。例如,以上所讨论的许多过程可以以不同方法来实施以及被其它过程或其组合所替代。Also, although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different ways and replaced by other processes or combinations thereof.

此外,本申请的范围并非意在被局限于说明书中所描述的过程、机器、制造品、物质组合、手段、方法和步骤的特定实施例。正如本领域技术人员将从本发明的公开内容容易意识到的,可以根据本发明对现有的或以后将要开发的与本文所描述的对应实施例执行基本上相同的功能或者获得基本上相同的结果的过程、机器、制造品、物质组合、手段、方法或步骤加以利用。因此,所附权利要求意在将这样的过程、机器、制造品、物质组合、手段、方法或步骤包括在其范围之内。Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As those skilled in the art will readily appreciate from the disclosure of the present invention, it is possible to perform substantially the same functions or obtain substantially the same functions according to the present invention to existing or later developed corresponding embodiments as described herein. process, machine, manufacture, composition of matter, means, method or steps resulting in the utilization of Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (20)

1.一种用于随功率转换器使用的控制器,所述控制器包括:1. A controller for use with a power converter, said controller comprising: 电感器-电感器-电容器(LLC)控制器,被配置为接收来自误差放大器的误差信号以控制所述功率转换器的LLC级的开关频率以对所述功率转换器的输出电压进行调整;以及an inductor-inductor-capacitor (LLC) controller configured to receive an error signal from an error amplifier to control a switching frequency of an LLC stage of the power converter to regulate an output voltage of the power converter; and 功率因数校正(PFC)控制器,被配置为对由所述功率转换器的PFC级产生并且被提供至所述LLC级的母线电压进行控制以使得所述LLC级的平均开关频率基本上被保持在期望的开关频率。a power factor correction (PFC) controller configured to control a bus voltage generated by a PFC stage of the power converter and provided to the LLC stage such that an average switching frequency of the LLC stage is substantially maintained at the desired switching frequency. 2.根据权利要求1所述的控制器,其中所述PFC级为PFC升压级并且所述LLC级为LLC谐振降压级。2. The controller of claim 1, wherein the PFC stage is a PFC boost stage and the LLC stage is an LLC resonant buck stage. 3.根据权利要求1所述的控制器,其中与所述LLC级相关联的控制回路具有比与所述PFC级相关联的控制回路更快的响应。3. The controller of claim 1, wherein a control loop associated with the LLC stage has a faster response than a control loop associated with the PFC stage. 4.根据权利要求1所述的控制器,其中所述LLC控制器包括非线性函数子系统,所述非线性函数子系统被配置为向所述误差信号应用校正因数以产生经校正的误差信号。4. The controller of claim 1 , wherein the LLC controller includes a nonlinear function subsystem configured to apply a correction factor to the error signal to produce a corrected error signal . 5.根据权利要求4所述的控制器,其中所述校正因数由折线校正因数进行近似。5. The controller of claim 4, wherein the correction factor is approximated by a broken line correction factor. 6.根据权利要求4所述的控制器,其中所述LLC控制器包括压控振荡器,所述压控振荡器被配置为接收所述经校正的误差信号以对所述LLC级的所述开关频率进行控制。6. The controller of claim 4, wherein the LLC controller comprises a voltage controlled oscillator configured to receive the corrected error signal for the The switching frequency is controlled. 7.根据权利要求1所述的控制器,其中所述PFC控制器被配置为提升所述母线电压以在所述误差信号中生成误差来检测所述功率转换器的轻载操作。7. The controller of claim 1, wherein the PFC controller is configured to boost the bus voltage to generate an error in the error signal to detect light load operation of the power converter. 8.根据权利要求1所述的控制器,其中所述误差放大器耦合至电阻分压器,所述电阻分压器被配置为感测所述输出电压并且将感测的输出电压提供至所述误差放大器的运算放大器以产生所述误差信号。8. The controller of claim 1, wherein the error amplifier is coupled to a resistor divider configured to sense the output voltage and provide a sensed output voltage to the The error amplifier is an operational amplifier to generate the error signal. 9.根据权利要求1所述的控制器,其中所述PFC级包括至少一个误差放大器,所述误差放大器被配置为对作为所述LLC级的所述开关频率和所述期望的开关频率的函数的所述母线电压进行控制。9. The controller of claim 1 , wherein the PFC stage includes at least one error amplifier configured to be a function of the switching frequency of the LLC stage and the desired switching frequency The bus voltage is controlled. 10.根据权利要求1所述的控制器,进一步包括突发模式控制器,所述突发模式控制器被配置为使得所述功率转换器在轻载的情况下进入突发操作模式。10. The controller of claim 1, further comprising a burst mode controller configured to cause the power converter to enter a burst mode of operation under light load conditions. 11.根据权利要求1所述的控制器,进一步包括突发模式控制器,所述突发模式控制器被配置为使得所述功率转换器在所述误差信号与突发阈值水平相交时进入突发操作模式。11. The controller of claim 1, further comprising a burst mode controller configured to cause the power converter to enter burst when the error signal crosses a burst threshold level. send operation mode. 12.根据权利要求1所述的控制器,其中电阻分压器被配置为感测所述输出电压,并且耦合至所述电阻分压器的第一感测开关和第二感测开关被配置为在所述功率转换器进入突发操作模式时减少功率损耗。12. The controller of claim 1, wherein a resistive divider is configured to sense the output voltage, and a first sense switch and a second sense switch coupled to the resistive divider are configured to To reduce power loss when the power converter enters a burst mode of operation. 13.根据权利要求1所述的控制器,其中所述期望的开关频率基本上等于所述LLC级的谐振频率。13. The controller of claim 1, wherein the desired switching frequency is substantially equal to a resonant frequency of the LLC stage. 14.一种对功率转换器进行操作的方法,包括:14. A method of operating a power converter comprising: 接收来自误差放大器的误差信号以控制所述功率转换器的电感器-电感器-电容器(LLC)级的开关频率来对所述功率转换器的输出电压进行调整;以及receiving an error signal from an error amplifier to control a switching frequency of an inductor-inductor-capacitor (LLC) stage of the power converter to regulate an output voltage of the power converter; and 对由所述功率转换器的功率因数校正(PFC)级产生并且被提供至所述LLC级的母线电压进行控制以使得所述LLC级的平均开关频率基本上被保持在期望的开关频率。A bus voltage generated by a power factor correction (PFC) stage of the power converter and provided to the LLC stage is controlled such that the average switching frequency of the LLC stage is substantially maintained at a desired switching frequency. 15.根据权利要求14所述的方法,其中与所述LLC级相关联的控制回路具有比与所述PFC级相关联的控制回路更快的响应。15. The method of claim 14, wherein a control loop associated with the LLC stage has a faster response than a control loop associated with the PFC stage. 16.根据权利要求14所述的方法,进一步包括向所述误差信号应用校正因数以产生经校正的误差信号以及对作为所述经校正的误差信号的函数的所述LLC级的所述开关频率进行控制。16. The method of claim 14 , further comprising applying a correction factor to the error signal to produce a corrected error signal and the switching frequency of the LLC stage as a function of the corrected error signal Take control. 17.根据权利要求14所述的方法,进一步包括提升所述母线电压以在所述误差信号中生成误差来检测所述功率转换器的轻载操作。17. The method of claim 14, further comprising boosting the bus voltage to generate an error in the error signal to detect light load operation of the power converter. 18.根据权利要求14所述的方法,进一步包括使得所述功率转换器在轻载的情况下进入突发操作模式。18. The method of claim 14, further comprising causing the power converter to enter a burst mode of operation under light load conditions. 19.根据权利要求14所述的方法,进一步包括使得所述功率转换器在所述误差信号与突发阈值水平相交时进入突发操作模式。19. The method of claim 14, further comprising causing the power converter to enter a burst mode of operation when the error signal crosses a burst threshold level. 20.根据权利要求14所述的方法,进一步包括感测所述输出电压,以及在所述功率转换器进入突发操作模式时减少功率损耗。20. The method of claim 14, further comprising sensing the output voltage, and reducing power loss when the power converter enters a burst mode of operation.
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