CN103532392A - Controller for a power converter and method of operating the same - Google Patents

Abstract

Embodiments of the invention generally relate to controllers for power converters and methods of operating the same. In particular, it relates to a controller for a power converter and a method of operating the same. In one embodiment, the controller includes an inductor-inductor-capacitor (LLC) controller configured to receive an error signal from an error amplifier to control the switching frequency of the LLC stage of the power converter to The output voltage is adjusted. The controller also includes a power factor correction (PFC) controller configured to control the bus voltage generated by the PFC stage of the power converter and provided to the LLC stage such that the average switching frequency of the LLC stage is maintained substantially at desired switching frequency.

Description

Controller for power converter and method of operating same

technical field

The present invention relates generally to power electronics, and more particularly to a controller for a power converter and a method of operating the same.

Background technique

A switch-mode power converter (also called a "power converter" or "regulator") is a power supply or power processing circuit that converts an input voltage waveform into a specified output voltage or current waveform. A power factor correction (PFC)/resonant inductor-inductor-capacitor (LLC) power converter includes a power train with a PFC stage followed by an LLC stage. The power converter is coupled to a power source (an alternating current (ac) power source) and provides a direct current (dc) output voltage. The PFC stage (from the ac source) receives a rectified version of the ac input voltage and provides a dc bus voltage. The LLC stage uses the bus voltage to provide a dc output voltage to the load. A power converter including a PFC stage and an LLC stage can be used to build an "ac adapter" to provide a dc output voltage from an ac power source to a notebook computer or the like.

A controller associated with the power converter manages the operation of the power converter by controlling the conduction period of the power switches employed therein. Typically, a controller is coupled between the input and output of the power converter in a feedback loop configuration (also referred to as a "control loop" or "closed control loop"). Two control procedures are often employed to control the output voltage of a power converter formed with a PFC stage followed by an LLC stage. One process controls the bus voltage of the PFC stage to control the output voltage, while the other process controls the switching frequency of the LLC stage to control the output voltage. As will be more apparent, employing two separate processes to control the output voltage of a power converter having a PFC stage and an LLC stage results in several design issues that detract from the operation and efficiency of the power converter.

Another area of interest with power converters is generally their detection and operation under light load conditions. Under such conditions, it may be advantageous for the power converter to enter a burst mode of operation. For the burst mode of operation, the power loss of the power converter depends on the gate drive signal of the power switch and other continuous power losses that generally do not vary substantially with load. These power losses are generally addressed at very low power levels by using a burst mode of operation, in which the controller is disabled for a period of time (e.g., one second), followed by a short period of high power operation (e.g., 10 milliseconds (ms )) to provide low average output power with low losses. A controller as described herein may employ the time interval of the burst mode of operation to estimate the output (or load) power of the power converter.

Therefore, there is a need in the art for a controller that incorporates a hybrid approach to the control process for power converters employing different power levels in their power trains to avoid the deficiencies in the prior art. Furthermore, there is a need in the art for a controller capable of detecting and managing a power converter under light load conditions, including the operation of the power converter into a burst mode of operation, to avoid the deficiencies of the prior art.

Contents of the invention

Technical advantages are generally achieved by advantageous embodiments of the present invention, including a controller for a power converter and methods of operating the same. In one embodiment, the controller includes an inductor-inductor-capacitor (LLC) controller configured to receive an error signal from an error amplifier to control the switching frequency of the LLC stage of the power converter to The output voltage is adjusted. The controller also includes a power factor correction (PFC) controller configured to control the bus voltage generated by the PFC stage of the power converter and provided to the LLC stage such that the average switching frequency of the LLC stage is maintained substantially at desired switching frequency.

In another aspect, a burst mode controller for a power converter includes a burst mode initiation circuit configured to initiate a burst when a signal representing an output voltage of the power converter crosses a first burst threshold level. send operation mode. The burst mode controller also includes a voltage boost circuit configured to provide a voltage boost signal to boost the output if a time window expires before the signal representative of the output voltage of the power converter crosses the second burst threshold level Voltage.

The foregoing has outlined rather broadly the features and technical advantages of the present invention so that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

Description of drawings

For a more comprehensive understanding of the present invention, reference is now made to the following descriptions in conjunction with the accompanying drawings, wherein:

Figure 1 illustrates a block diagram of an embodiment of a power converter including a controller constructed in accordance with the principles of the present invention;

2 illustrates a schematic diagram of a portion of a power converter including an exemplary power train employing a boost topology, constructed in accordance with the principles of the present invention;

3 illustrates a circuit diagram of an embodiment of a power converter formed using a PFC stage coupled to an LLC stage constructed in accordance with the principles of the present invention;

4-6 illustrate graphical representations of exemplary operating characteristics of a power converter in accordance with the principles of the present invention;

7 and 8 illustrate diagrams of embodiments of power converters formed using a PFC stage coupled to an LLC stage constructed in accordance with the principles of the present invention;

9 illustrates a schematic diagram of an embodiment of a burst mode controller configured to manage a burst mode of operation of a power converter in accordance with the principles of the present invention;

Figure 10 illustrates a graphical representation of exemplary waveforms generated within a power converter in accordance with the principles of the present invention;

Figure 11 illustrates a diagram of an embodiment of a resistive divider coupled to an output voltage of a power converter constructed in accordance with the principles of the present invention; and

Figure 12 illustrates a diagram of an embodiment of a portion of a voltage boost circuit constructed in accordance with the principles of the present invention for generating a slope signal indicative of the output of a power converter that may be employed in a burst mode controller The slope of the voltage.

Corresponding numerals and symbols in the different drawings generally refer to corresponding parts unless otherwise indicated and may not be described after the first instance for the sake of brevity. The figures are drawn to illustrate relevant aspects of the exemplary embodiments.

Detailed ways

The making and using of the exemplary embodiment are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to exemplary embodiments in a specific context, ie, a controller for a power converter. Although the principles of the present invention will be described in the context of a controller for a power factor correction (PFC)/resonant inductor-inductor-capacitor (LLC) power converter, it can be obtained from, for example, a power amplifier or a motor controller. Any application in which a controller of this type would benefit is also within the broad scope of the present invention.

Referring first to FIG. 1 , there is illustrated a block diagram of an embodiment of a power converter including a controller 110 constructed in accordance with the principles of the present invention. The power converter is coupled to an ac mains represented by an ac source providing an input voltage Vin. The power converter includes a power train 105 controlled by a controller 110 . The controller 110 typically measures an operating characteristic of the power converter, such as its output voltage Vout, and controls the duty cycle D of the power switch therein in response to the measured operating characteristic to adjust the characteristic. The power train 105 may include multiple power stages to provide a regulated output voltage Vout or other output characteristic to a load. The power train 105 of the power converter includes a plurality of power switches coupled to magnetic devices to provide power conversion functions.

Turning now to FIG. 2 , there is illustrated a schematic diagram of a portion of a power converter including an exemplary power train (eg, PFC stage 201 ) employing a boost topology (eg, PFC boost stage) constructed in accordance with the principles of the present invention. . The PFC stage 210 of the power converter receives at its input an input voltage Vin (eg, an unregulated ac input voltage) from a power source such as the ac mains and provides a regulated DC bus voltage (also referred to as the bus voltage) Vbus. Consistent with the principle of boost topology, the bus voltage Vbus is usually higher than the input voltage Vin so that its switching operation can adjust the bus voltage Vbus. The mains power switch _S1 (e.g., an n-channel metal-oxide-semiconductor (NMOS) "active" switch) is enabled to conduct the main compartment via the gate drive signal GD and couple the input voltage Vin to the boost voltage via the bridge rectifier 203 Inductor L _boost . During the main interval D of the switching cycle, the inductor current i _in increases and flows through the boost inductor L _boost to the local circuit ground. The boost inductor L _boost is usually formed with a single layer winding to reduce the proximity effect and improve the efficiency of the power converter.

The duty cycle of the PFC stage 201 at steady state depends on the ratio of the input voltage to the bus voltage (Vin, Vbus, respectively) according to the following equation:

$\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; Vin</span>}}{\mathrm{<span\; class="notranslate">\; Vbus</span>}}$

During complementary interval 1-D, the main power switch _S1 is transitioned to a non-conducting state while the auxiliary power switch (eg, diode D1 ) is conducting. In an alternative circuit arrangement, the auxiliary power switch may comprise a second active switch controlled to be turned on by a complementary gate drive signal. Auxiliary power switch D1 provides a way to maintain continuity of inductor current i _{in through} boost inductor L _boost . During the complementary interval 1-D, the inductor current i _in flowing through the _boost inductor Lboost decreases and may become zero and remain zero for a period of time, which results in a "discontinuous conduction mode" of operation.

During the complementary interval 1-D, the inductor current i _in flowing through the _boost inductor L boost flows into the filter capacitor C through the diode D1 (ie, the auxiliary power switch). In general, the duty cycle of the main power switch S ₁ (and the complementary duty cycle of the auxiliary power switch D 1 ) can be adjusted to maintain regulation of the bus voltage Vbus of the PFC stage 201 . Those skilled in the art understand that by using "snubber" circuit elements (not shown) or by controlling the circuit timing, the conduction period of the main power switch _S1 and the auxiliary power switch D1 can be controlled by a small time The spaces are spaced apart to avoid cross-conduction current therebetween and advantageously reduce switching losses associated with the power converter. Circuitry and control techniques for avoiding cross-conduction currents between main power switch _S1 and auxiliary power switch D1 are well known in the art and will not be further described for the sake of brevity. The boost inductor L _boost is typically formed with a single layer winding to reduce power loss associated with proximity effects.

Turning now to FIG. 3, there is illustrated the power developed by a PFC stage, such as PFC stage 201 of FIG. Circuit diagram of an embodiment of the converter. The PFC stage 201 and LLC stage 320 may be used to construct an "ac adapter" to provide a dc output voltage Vout (eg, 19.5 volts) to a notebook computer from an ac mains supply (represented by input voltage Vin).

As mentioned above, two control processes are often employed to control the output voltage Vout of a power converter formed with the PFC stage 201 followed by the LLC stage 320 . One process controls the bus voltage Vbus of the PFC stage 201 to control the output voltage Vout, while the other process controls the switching frequency (also named switching frequency fs) of the LLC stage 320 to control the output voltage Vout. The bus voltage Vbus produced by the PFC stage 201 is controlled in response to the load coupled to the output of the LLC stage 320 in a slower response feedback loop. The LLC stage 320 operates at a fixed switching frequency fs selected to increase its power conversion efficiency. The LLC stage 320 operates continuously in an ideal transformer state with the bus voltage Vbus generated by the PFC stage 201 , which is controlled to compensate for the IR (current times resistance) drop in the LLC stage 320 . Typically, the variation of the bus voltage Vbus produced by the PFC stage 201 is on the order of tens of volts.

The LLC stage 320 is controlled using a switching frequency, the PFC stage 201 produces a constant dc bus voltage Vbus, but the LLC stage 320 operates using a switching frequency that responds to changes in the load coupled to the power converter output using a fast Control is performed in response to a control loop (ie, a control loop with a high crossover frequency). Changing the switching frequency of LLC stage 320 typically causes LLC stage 320 to operate at an inefficient switching frequency.

A hybrid control approach is provided where the bus voltage Vbus produced by the PFC stage 201 is controlled with a slower response control loop (ie a control loop with a low crossover frequency) to handle the average load power. The switching frequency of the LLC stage 320 is controlled using a fast response feedback loop to handle load transients and ac mains signal dropout events. Controlling the PFC stage 201 to control the output voltage Vout leads to several design issues. First, the bus voltage Vbus usually exhibits poor transient response due to low PFC control loop crossover frequency. Second, there is a large amount of ripple voltage (eg, 100-120 Hz ripple voltage) on the bus voltage Vbus that powers the LLC stage 320 that appears on its output.

As described herein, the switching frequency of the LLC stage 320 is controlled using a fast response control loop to attenuate the effect of the ripple voltage produced by the PFC stage 201 that typically appears on the output of the LLC stage 320 . Furthermore, the transformer/stage gain of the LLC stage 320 is controlled with fast response in the frequency region between 1/(2π sqrt((Lm+Lk) Cr)) and 1/(2π sqrt(Lk Cr)) The loop is adapted to accommodate large load step changes and the event of a signal exit of the ac mains input voltage Vin. The bus voltage Vbus of the PFC stage 201 is controlled in response to slow changes in load so that the LLC stage 320 can ideally continue to operate at or near its resonant frequency, at which point its power conversion efficiency is typically optimal. By having the LLC stage 320 operate at or near its resonant frequency most of the time, but allowing the switching frequency to vary in response to transients, improved load step response, reduced ripple in the output voltage Vout, and higher power can be obtained conversion efficiency.

The primary inductance of the transformer T1 is the leakage inductance Lk plus the magnetizing inductance Lm, both inductances are referenced to the primary winding of the transformer T1. The resonant capacitor is Cr. The resonant capacitor Cr can be divided into two capacitors coupled in a series circuit with one end coupled to ground and the other end coupled to the bus voltage Vbus. A serial circuit arrangement can be used to reduce the inrush current at start-up. The ideal switching frequency for fs is fo=1/(2π·sqrt(Lk·cr)), which is the high-efficiency operating point under normal conditions (eg, 50 kilohertz (kHz)). The low switching frequency at which inefficient capacitive switching begins is fmin=1/(2π·sqrt(Lp·Cr)). It is generally desirable to operate at switching frequencies greater than the minimum switching frequency fmin, and to avoid even switching frequencies close to the minimum switching frequency fmin.

The controller 325 has an input for the bus voltage Vbus and an input for the output voltage Vout of the power converter from a feedback circuit including an optocoupler 350 . As illustrated and described below with reference to FIGS. 7 and 8 , a voltage controlled oscillator (VCO) 336 controls the switching frequency fs of the LLC stage 320 . Therefore, the PFC stage 201 and the LLC stage 320 are jointly controlled in the voltage domain and the frequency domain. As described further below, the operation of the controller 325 is tested from time to time to enable entry into burst mode under light load conditions.

As shown in FIG. 3 , the input voltage Vin is coupled to an electromagnetic interference filter (EMI) 310 , and its output is coupled to a bridge rectifier 203 to generate a rectified voltage Vrect. The PFC stage 201 generates a bus voltage Vbus, which is coupled to the input of the LLC stage 320 to generate an output voltage Vout, which is filtered by an output filter capacitor Cout of the power converter. In an alternative embodiment, LLC stage 320 may be formed using a full bridge topology. The output voltage Vout is sensed by an error amplifier 340 coupled to a resistor divider formed by a first resistor Rsensel and a second resistor Rsense2. The output signal from error amplifier 340 is coupled to optocoupler 350, which generates an output voltage error signal (also referred to as "error signal") δV. The output voltage error signal δV and bus voltage Vbus are coupled to PFC controller 330 and/or LLC controller 333 of controller 325 (described in more detail below with respect to FIG. 7 ). The controller 325 jointly controls the bus voltage Vbus generated by the PFC stage 201 and the switching frequency fs of the LLC stage 320 to regulate the output voltage Vout while maintaining the switching frequency fs (most of the time) at the efficient operation of the LLC stage 320 point.

In operation, a zero-to-full step change in the load coupled to the output voltage Vout, for example, would cause the bus voltage Vbus to drop from 370 volts to 290 volts. By reducing the switching frequency fs of the LLC stage 320 from 50kHz to 25kHz using a fast response control loop, the increased voltage gain of the LLC stage 320 from 1.3 to 1 or more can be used to substantially reduce the bus voltage Vbus. compensate. As the bus voltage Vbus recovers to approximately 390 volts to compensate for the IR drop in the LLC stage 320, its switching frequency fs returns to 50 kHz.

The same principle can be applied to a holdup event when the ac mains voltage (input voltage Vin) signal exits. While the bus voltage Vbus drops from 390 volts to 280 volts, the remaining energy stored in the filter capacitor C of the PFC stage 201 can be used to maintain regulation of the output voltage Vout. Likewise, the frequency-dependent voltage gain of the LLC stage 320 is used to regulate the output voltage Vout of the power converter in response to a fast response control loop. The response of the LLC stage 320 can thus be used to reduce the size of the filter capacitor C of the PFC stage 201 or to increase the power converter ride-through time for the ac input voltage (input voltage Vin) to drop. As described further below, non-linear feedback is employed for control loop compensation.

The burst mode control signal is derived by controller 325 as described in more detail below. When the burst mode control signal is high, the controller 325 is enabled to operate. Conversely, when the burst mode control signal is low, the controller 325 is disabled. The burst mode control signal can be used to enable the burst mode of operation of the power converter. The PFC controller 330 provides a gate drive signal for the main power switch S1 of the PFC stage 201 during the main duty cycle D and the complementary duty cycle 1-D of the switching cycle, and the LLC controller 333 provides the gate drive signal for the main power switch S1 of the PFC stage 201 during the main interval D and the complementary duty cycle 1-D of the switching cycle. Gate drive signals are provided to the main power switch M1 and the auxiliary power switch _M2 of the LLC stage 320 during complementary intervals 1-D. PFC controller 330 also uses voltage Vrect to control the low frequency current waveform from bridge rectifier 203 . The gate drive signal named GDM ₂ represents the gate drive signal to the auxiliary power switch M ₂ during the complementary interval 1-D of the LLC stage 320 to be employed in the circuit shown in FIG. 12 .

Turning now to FIGS. 4-6 , there are illustrated graphical representations of exemplary operating characteristics of a power converter in accordance with the principles of the invention. Fig. 4 illustrates the voltage transfer characteristics of the LLC stage of the power converter. The output voltage Vout of the LLC stage (and power converter) at a certain bus voltage Vbus (such as 400 volts) from the PFC stage depends in a non-linear manner on the switching frequency fs of the LLC stage. As the bus voltage Vbus decreases, the output voltage Vout decreases approximately proportionally while the switching frequency fs remains constant. As a result, the switching frequency fs can be varied to control the output voltage Vout when the bus voltage Vbus varies. However, the effect of changing the switching frequency fs on the output voltage Vout is non-linear. The resonance frequency fres represents the resonance frequency of the LLC stage.

Turning now to FIG. 5 , there is illustrated a graphical representation of the correction factor G as an inverse function of the frequency-dependent curve shown in FIG. 4 . The frequency-dependent curve shown in FIG. 4 multiplied by this correction factor G produces a straight line of the frequency-dependent characteristic of the voltage transfer characteristic of the LLC stage. The result of multiplying by the correction factor G is illustrated in FIG. 6 , such as a straight line 610 equal to a bus voltage Vbus of 400 volts. In one embodiment, the correction factor G is approximated by a broken line correction factor G' shown in FIG. 5, such as a five-segment broken line correction factor.

Turning now to FIG. 7 , illustrated is an embodiment of a power converter formed using a PFC stage (such as PFC stage 201 of FIG. 2 ) coupled to an LLC stage (such as LLC stage 320 of FIG. 3 ) constructed in accordance with the principles of the present invention. diagram of . The power converter receives an input voltage and provides (via a bridge rectifier) a rectified voltage Vrect, which is converted by the PFC stage 201 and the LLC stage 320 to an output voltage Vout. The output voltage Vout is sensed using a resistive divider formed by the first resistor Rsensel and the second resistor Rsense2 , and the sensed output voltage is coupled to the inverting input of the operational amplifier 345 of the error amplifier 340 . Error amplifier 340 includes a resistor capacitor network 360 in its feedback path to generate an output voltage error signal (also referred to as "error signal") δV.

Greater feedback loop stability is obtained by employing nonlinear function subsystem 335 in the feedback loop to control the switching frequency fs of LLC stage 320 to compensate for its frequency dependent response. According to the non-linear subsystem 335, the correction factor G is approximated in the form of a broken line correction factor (eg, a five-segment broken line correction factor G') which is applied to the output voltage error signal δV to generate a corrected error signal δV_cor. It should be understood that an optocoupler, such as optocoupler 350 shown in FIG. 3 , may cooperate with error amplifier 340 to generate the output voltage error signal δV. In one embodiment, a five-segment polyline correction factor G' is employed in nonlinear function subsystem 335 to reduce nonlinear feedback effects produced by LLC stage 320 . The five-segment broken line correction factor G' may be more generally referred to as a broken line correction factor. The corrected error signal δV_cor is coupled to the input of a voltage controlled oscillator (VCO) 336 that controls the switching frequency fs of the LLC stage 320 . Nonlinear function subsystem 335 and voltage controlled oscillator 336 form at least part of LLC controller 333 (see also FIG. 3 ).

The switching frequency fs is also coupled to the PFC controller 330, which generates the gate drive signal GD for the main power switch _S1 of the PFC stage 201 (see FIG. 3). The PFC controller 330 senses the bus voltage Vbus of the PFC stage 201 . The PFC controller 330 controls the bus voltage Vbus in a slower response control loop to keep the average value of the switching frequency fs around the ideal switching frequency fo=1/(2π·sqrt(Lk·Cr)) to maintain the LLC stage 320 High power conversion efficiency.

In yet another aspect, the PFC controller 330 simply boosts the bus voltage Vbus from time to time (e.g., by 6 volts or 7 volts in 20 milliseconds) to generate an error in the error signal δV, or correspondingly in the corrected error signal δV_cor An error is generated to detect light load operation to enable entry into a burst mode of operation. As described in more detail below, burst mode operation under light load conditions results in a significant improvement in power conversion efficiency in accordance with the burst mode controller 370 . The PFC controller 330 is able to boost the bus voltage Vbus by simply boosting the reference voltage in which the error amplifier is used to adjust the bus voltage Vbus. As described below with reference to FIG. 8 , the bus voltage reference Vbus_ref coupled to the input of error amplifier 332 is simply boosted to enable detection of light load operation. Burst mode is entered when the error signal δV or the corrected error signal δV_cor crosses a threshold level.

In operation at light load conditions, the bus voltage Vbus is reduced to a low value due to the reduction loss of the LLC stage 320 . When the bus voltage Vbus is boosted for a short period of time, the resulting change (eg, decrease) in the error signal δV is used to determine whether to enter burst mode. A higher bus voltage Vbus reduces the switching frequency of the LLC stage 320 . Increased bus voltage Vbus and light loads cause the error signal δV to drop sufficiently, which is detected to enter burst mode. Burst mode is exited when the output voltage Vout drifts down to a threshold level as indicated by a rise in the error signal δV. In the burst mode of operation, the switching actions of both the PFC stage 201 and the LLC stage 320 are turned off (eg, the alternating nature of the duty cycle D of the gate drive signal used to control the respective power switches is terminated).

Turning now to FIG. 8 , there is illustrated a diagram utilizing a PFC stage (such as PFC stage 201 of FIG. 2 ) coupled to an LLC stage (such as LLC stage 320 of FIG. 3 ) and a controller (comprising the Parts of the controller 325) form a diagram of an embodiment of a power converter. PFC controller 330 includes an error amplifier (E/A) 331 having one input, preferably an inverting input, coupled to a switching frequency fs generated by a voltage controlled oscillator (VCO) 336 . Another input of error amplifier 331 , preferably a non-inverting input, is coupled to frequency reference fs_ref, which is the desired switching frequency of LLC stage 320 . In one embodiment, the desired switching frequency (similar to the ideal switching frequency) is fo = 1/(2π·sqrt(Lk·Cr)). Error amplifier 331 generates bus voltage reference Vbus_ref, which is used by error amplifier (E/A) 332 in a slower response control loop to regulate bus voltage Vbus generated by PFC stage 201 . The bus voltage reference Vbus_ref represents a desired voltage level of the bus voltage Vbus to provide high power conversion efficiency to the power converter. In this way, the controller 325 adjusts the bus voltage Vbus generated by the PFC stage 201 to generate an average switching frequency fs of the LLC stage 320 , which results in a high power conversion efficiency of the LLC stage 320 . The error amplifier 340 is maintained to regulate the output voltage Vout of the power converter with a fast response control loop to enable tight regulation of the output voltage Vout by the power converter with a reduced ripple voltage level that would otherwise be The mode is generated by the ripple voltage on the bus voltage Vbus of the PFC stage 201 .

Accordingly, a controller for a power converter has been described herein. In one embodiment, the controller includes an LLC controller configured to receive an error signal from an error amplifier to control the switching frequency of an LLC stage (eg, LLC resonant buck stage) of the power converter to output voltage is adjusted. The controller also includes a PFC controller configured to control a bus voltage generated by a PFC stage (eg, a PFC boost stage) of the power converter and provided to the LLC stage so that it switches on average The frequency is maintained substantially at the desired switching frequency (eg, substantially equal to the resonant frequency of the LLC stage). The control loop associated with the LLC stage may have a faster response than the control loop associated with the PFC stage. The LLC controller may include a nonlinear function subsystem configured to apply a correction factor (eg, approximated by a broken line correction factor) to the error signal to produce a corrected error signal. The LLC controller may include a voltage controlled oscillator configured to receive the corrected error signal to control the switching frequency of the LLC stage.

The PFC controller is configured to boost the bus voltage to generate an error in the error signal to detect light load operation of the power converter. The error amplifier is coupled to a resistive voltage divider configured to sense the output voltage and provide the sensed output voltage to an operational amplifier of the error amplifier to generate an error signal. The PFC stage may include at least one error amplifier configured to control the bus voltage as a function of the switching frequency of the LLC stage and the desired switching frequency. The controller may also include a burst mode controller configured to cause the power converter to enter a burst mode of operation under light load conditions and/or when the error signal crosses a burst threshold level. The controller may also be coupled to a resistive voltage divider configured to sense an output voltage, and a first sensing switch and a second sensing switch coupled to the resistive voltage divider configured to sense the output voltage in the power converter. Reduce power loss when entering burst mode of operation.

Turning now to FIG. 9 , there is illustrated a burst mode controller, such as burst mode controller 370 of FIGS. 7 and 8 , configured to manage a burst mode of operation of a power converter in accordance with the principles of the present invention. Example schematic. The length of time (or time interval or window) during which the operation of the controller 325 is disabled (e.g., the controller does not output a gate drive signal for the PFC stage or LLC stage) can be used as a fairly accurate indicator for determining output power device. This time interval can be used to determine the exit of burst mode in preparation for a possible subsequent transient load step. The off-time of the controller 325 is measured using the voltage developed across the ramp voltage timing capacitor Cramp.

The burst mode controller 370 is coupled to the error signal δV generated by the error amplifier 340 to set the burst mode control signal Fon and the voltage boost signal Fves. The error signal δV is related to and provides an indicator of the output voltage Vout of the power converter. When the burst mode control signal Fon is set to a high level, the switching action of the PFC stage 201 and the LLC stage 320 of the power converter is enabled. On the contrary, when the burst mode control signal Fon is at low level, the switching actions of the PFC stage 201 and the LLC stage 320 of the power converter are disabled. The voltage boost signal Fves is used to simply boost the regulated output voltage Vout of the power converter so that low load power can be detected to enable entry into the burst mode of operation.

The burst mode controller 370 is formed using a first comparator 920 having a non-inverting input coupled to the error signal δV and a second comparator 930 coupled to the high burst threshold level Vburst_high (second burst threshold level), while the second comparator 930 has an inverting input coupled to the error signal δV and a non-inverting input coupled to the low burst threshold level Vburst_low (first burst threshold level). The outputs of the comparators 920 , 930 are coupled to one of the “set” and “reset” inputs of the first set-reset flip-flop 940 and the second set-reset flip-flop 970 . The "Q" output of the first set-reset flip-flop 940 sets the burst mode control signal Fon. The comparators 920 , 930 and the first set-reset flip-flop 940 form at least part of a burst mode initiation circuit of the burst mode controller 370 .

The current source 950 generates current to charge the ramp voltage timing capacitor Cramp, whose capacitor voltage Vcap is coupled to the non-inverting input of the third comparator 960 . The inverting input of the third comparator 960 is coupled to the capacitor voltage threshold V_cap_thresh. The burst mode control signal Fon generated by the first set-reset flip-flop 940 is also coupled to the gate of the ramp switch (eg, n-channel MOSFET) Qramp. When the burst mode control signal Fon is at a high level, the ramp switch Qramp discharges the ramp voltage timing capacitor Cramp. The output signal 990 of the third comparator 960 is coupled to the set input of the second set-reset flip-flop 970 . The set input of the second set-reset flip-flop 970 is also coupled to the timer 980 through an AND gate 995 . The timer 980 periodically sets the voltage boost signal Fves to a high level (eg, every 40 milliseconds). When the voltage boost signal Fves is at a high level, the reference voltage Vref of the operational amplifier 345 of the error amplifier 340 (see FIGS. volts), so that the second comparator 930 can detect a high voltage level of the output voltage Vout. The current source 950 , the third comparator 960 , the second set-reset flip-flop 970 , the ramp voltage timing capacitor Cramp and the ramp switch Qramp form at least part of the voltage boost circuit of the burst mode controller 370 . As described in more detail below, current source 950, ramp voltage timing capacitor Cramp, and comparator 960 detect whether the time window for the burst mode of operation has expired.

The burst mode controller 370 operates using the following logic. If the error signal δv is greater than the high burst threshold level Vburst_high, the burst mode control signal Fon is set to a high level. The error signal δV then rises to a high level as the output voltage Vout decreases. If the error signal δV is less than the low burst threshold level Vburst_low, the burst mode control signal Fon is set low to enter the burst mode of operation. On the contrary, the error signal δV decreases to a low level when the output voltage Vout increases to a high level, which sets the output of the second comparator 930 to a high level. Thus, the error signal provides an indicator of the output voltage Vout at the primary side of the isolation barrier (see transformer T1 of FIG. 3 ) that is typically formed between the primary and secondary sides of a power converter, and the error signal δV corresponds accordingly The burst mode control signal Fon is controlled. If the error signal δV is less than the low burst threshold level Vburst_low, the voltage boost signal Fves is also set to a low level.

The voltage boost signal Fves is set to a high level if the capacitor voltage Vcap across the ramp voltage timing capacitor Cramp is greater than the capacitor voltage threshold V_cap_thresh. A high voltage across the ramp voltage timing capacitor Cramp is considered an indication of a low power load coupled to the output of the power converter, thereby enabling entry into the burst mode of operation. Voltage boost signal Fves is also set high in response to the signal from timer 980, which provides a mechanism for testing the load coupled to the output of the power converter.

Turning now to FIG. 10 , there is illustrated a graphical representation of exemplary waveforms generated within a power converter in accordance with the principles of the invention. Continuing to refer to the previous figures, it is initially assumed that the power converter supplies a load coupled to its output as indicated by the periodic switching of the duty cycle D of the gate drive signal for the switches of the power converter's power train. Provides substantial power. Periodic switching of the switches of the power converter is enabled by the burst mode control signal Fon. The error signal δV assumes a value between the high burst threshold level Vburst_high and the low burst threshold level Vburst_low to indicate that the output voltage Vout is within an acceptable voltage regulation range. The capacitor voltage Vcap remains at zero volts due to the high level of the burst mode control signal Fon, which turns on the ramp switch Qramp, shorting the ramp voltage timing capacitor Cramp.

At time T0, timer 980 sets the output of second set-reset flip-flop 970 high, which sets voltage boost signal Fves high and boosts error amplifier 340 (see FIGS. 7, 8 and The reference voltage Vref of the operational amplifier 345 of FIG. 11 ). The voltage boost signal Fves initiates a test for a light load coupled to the output of the power converter. In response thereto, the output voltage Vout of the power converter is raised, which eventually reduces the error signal δV to the low burst threshold level Vburst_low at time T1. This causes the burst mode control signal Fon to be reset low (to enter the burst operation mode), and the voltage boost signal Fves is also set low. As indicated by the absence of duty cycle D, the switching action of the power converter is stopped. Capacitor voltage Vcap ramps up and if the load on the power converter is sufficiently low, it crosses capacitor voltage threshold V_cap_thresh at time T2, which causes voltage boost signal Fves and burst mode control signal Fon to be set high. Therefore, the time window for the burst mode of operation is between time T1 and time T2. Therefore, the voltage boost signal Fves is set high to boost the output voltage Vout of the power converter due to the time window expiring before the error signal δV crosses the high burst threshold level Vburst_high. Alternatively, the timer 980 can cause the voltage boost signal Fves to be set to a high level, and accordingly set the reference voltage Vref to be boosted. Therefore, the output voltage Vout of the power converter is indirectly sensed using the error signal δV and the slope of the output signal Vout measured by the time interval used to control the burst mode of operation is used to estimate the output power of the power converter.

The indicator of the slope of the output voltage Vout is determined by the time interval (time window) sensed by the third comparator 960 shown in FIG. 9 . If the capacitor voltage Vcap does not cross the capacitor voltage threshold v_cap_thresh between time T1 and time T2 (for example, when the burst mode control signal Fon is low indicating that the output voltage Vout is within the acceptable voltage regulation range) , then the slope of the output voltage Vout is sufficiently small to signal entry into the burst mode of operation. Accordingly, the load on the power converter is estimated to be less than a predetermined low threshold level. For example, if the power converter is rated to supply a load of 60 watts, the predetermined low threshold level may be 5 watts and the burst mode controller 370 determines that the output power is less than 5 watts through the operations described above. In other words, the burst mode controller 370 estimates the output power in conjunction with the slope of the output voltage Vout.

Conversely, if the capacitor voltage Vcap crosses the capacitor voltage threshold V_cap_thresh before time T2 (for example, when the burst mode control signal Fon is low indicating that the output voltage Vout is below the acceptable voltage regulation range), the output voltage The slope of Vout is sufficiently high to signal an exit from the burst mode of operation (ie, enable switching of the power converter). Accordingly, the load on the power converter is estimated to be greater than a predetermined low threshold level. For example, if the power converter is rated to supply a load of 60 watts, the predetermined low threshold level may be 5 watts and the burst mode controller 370 determines that the output power is greater than 5 watts through the operations described above. In other words, the burst mode controller 370 estimates the output power in conjunction with the slope of the output voltage Vout.

The result is that a sufficiently high output voltage Vout sets the burst mode control signal Fon low and a low output voltage Vout sets the burst mode control signal Fon high. The timer 980 periodically sets the voltage boost signal Fves high, and the sufficiently high capacitor voltage Vcap generated across the ramp voltage timing capacitor Cramp also sets the voltage boost signal Fves high. Therefore, the time interval of the burst mode of operation of the power converter is used to determine the slope of the output voltage Vout to estimate the output power of the power converter. A low power load coupled to the output of the power converter is detected enabling the power converter to enter a burst mode of operation. The capacitor voltage Vcap crossing the capacitor voltage threshold V_cap_thresh is used as an indicator of a low slope of the output voltage Vout of the power converter, and accordingly of a low power load.

Turning now to FIG. 11 , there is illustrated a first resistor Rsensel constructed in accordance with the principles of the present invention utilizing an output voltage Vout coupled to a power converter (see, for example, the power converters of FIGS. 3 , 7 and 8 ) and Diagram of an embodiment of a resistive voltage divider formed by the second resistor Rsense2. This resistive divider is now coupled to the non-inverting input of operational amplifier 345 through a first sense switch (e.g., n-channel MOSFET) Qsense2, and to ground terminal. The burst mode control signal Fon turns on the first sense switch Qsensel and the second sense switch Qsense2 to reduce power consumption when the power converter is in the burst operation mode as indicated by the burst mode control signal Fon being low.

A reference voltage Vref used to regulate the output voltage Vout of the power converter is coupled to a voltage source V1 through a resistor R1 and coupled to a voltage boost signal Fves through another resistor R2. In this way, the voltage boost signal Fves boosts the reference voltage Vref when the voltage boost signal Fves is set to a high level.

Turning now to FIG. 12 , illustrated is a diagram of an embodiment of a portion of a voltage boost circuit that may be employed in a burst mode controller 370 , constructed in accordance with the principles of the present invention, for generating an indicative power converter (e.g., See the slope signal Vslope of the slope of the output voltage Vout of the power converter in FIG. 3 , FIG. 7 and FIG. 8 . This portion of the voltage boost circuit of FIG. 12 is an alternative to the current source 950, third comparator 960, ramp switch Qramp, and ramp voltage timing capacitor Cramp of the burst mode controller 370 shown in FIG. This portion of the voltage boost circuit of FIG. 12 senses the output voltage Vout instead of the error signal δv shown in FIG. 9 . The resistor Rrip is coupled to the output voltage Vout through the capacitor Crip to sense the derivative of the output voltage Vout. The derivative is filtered with a low pass filter formed with a filter resistor Rfilter coupled to a filter capacitor Cfilter to produce a filtered slope signal Vslope. In one embodiment, the time constant of the circuit formed with resistor Rrip coupled to capacitor Crip is a multiple of the switching period of the power converter (eg, 10 times the switching period). In one embodiment, the time constant of the low pass filter formed with the filter resistor Rfilter coupled to the filter capacitor Cfilter is a submultiple (eg, 0.01 times the switching period) of the power converter.

During the complementary interval 1-D, the slope signal Vslope can be used to estimate the output or load power coupled to the output of the power converter. The slope signal Vslope is coupled to a non-inverting input of comparator 1220, and the inverting input of comparator 1220 is coupled to slope reference voltage Vrefl. The output signal 1230 of the comparator 1220 is coupled to an input of an AND gate 1240, and the other input of the AND gate 1240 is coupled to the gate drive signal GDM ₂ , which is represented at the LLC stage 320 (see FIG. 3 ). Gate drive signal to auxiliary power switch _M2 during complementary interval 1-D. The output of AND gate 1240 corresponds to output signal 990 which is used to set voltage boost signal Fves by second set-reset flip-flop 970 illustrated and described with reference to FIG. 9 .

The voltage slope dVout/dt of the output voltage Vout is related to the load power by the following equation:

$\frac{\mathrm{dVout}}{\mathrm{dt}}=\frac{-\mathrm{V\; slope}}{\mathrm{Rrip}\&CenterDot;\mathrm{Crip}}$ and

$\mathrm{<span\; class="notranslate">\; Upload</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; Iload</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; Vout</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vout</span>}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; Cout</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; dVout</span>}}{\mathrm{<span\; class="notranslate">\; dt</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; Vout</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; V\; slope</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; Cout</span>}}{\mathrm{<span\; class="notranslate">\; Rrip</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; Crip</span>}}$

Where Cout is the output filter capacitor of the power converter shown in Figure 3 .

The output signal 1230 can be used to estimate the load power coupled to the output of the power converter, and if the load power is sufficiently light, the output signal 1230 can be used as another mechanism to enable entry into the burst mode of operation (e.g., by Set the voltage boost signal Fves to a high level). The output signal 1230 may be used by other switch mode power converters to estimate load power and is not limited to enabling a power converter formed with the PFC stage 201 and the LLC stage 320 to enter a burst mode of operation.

As mentioned above with respect to the burst mode of operation, the power loss of the power converter depends on the gate drive signals for the power switches and other continuous power losses that generally do not vary substantially with load. These power losses are typically addressed at very low power levels by using a burst mode of operation in which a controller (such as controller 325 in the previous figure) is disabled for a period of time (e.g., one second) followed by a short period of time. High power operation (eg, 10 milliseconds (ms)) to provide low average output power with low losses. A controller as described herein may employ the time interval of the burst mode of operation to estimate the output (or load) power of the power converter.

Therefore, a burst mode controller for use with a power converter has been described here. In one embodiment, the burst mode controller includes a burst mode initiating circuit configured to initiate a burst mode of operation when a signal representative of an output voltage of the power converter crosses a first burst threshold level. The burst mode controller also includes a voltage boost circuit configured to provide a voltage boost signal to boost the output if a time window expires before the signal representative of the output voltage of the power converter crosses the second burst threshold level Voltage. The burst mode initiating circuit is also configured to terminate the burst mode of operation when the signal representative of the output voltage of the power converter crosses a second burst threshold level.

The burst mode initiating circuit may include a comparator configured to compare a signal representative of the output voltage of the power converter to a first burst threshold level. The burst mode initiating circuit may also include a flip-flop configured to set the burst mode control signal to initiate the burst mode of operation when the signal representative of the output voltage of the power converter crosses the first burst threshold level. The voltage boost circuit may include a current source, a ramp voltage timing capacitor, and a comparator configured to detect expiration of a time window. The voltage boost circuit may also include a flip-flop configured to set a voltage boost signal to boost the output voltage. The voltage boost signal is configured to boost a reference voltage of an error amplifier configured to control the output voltage of the power converter. The burst mode initiating circuit is configured to deassert the voltage boost signal when the signal representative of the output voltage of the power converter crosses a first burst threshold level. The burst mode controller may also include a timer configured to initiate (and/or periodically initiate) a voltage boost signal to boost the output voltage.

The controller and associated methods may be implemented as hardware (contained in one or more chips including an integrated circuit such as an application specific integrated circuit), or may be implemented as a ) software or firmware executed from memory. In particular, in the case of firmware or software, exemplary embodiments may be provided as a computer program product comprising a computer-readable medium having computer program code (i.e., software or firmware) embodied thereon for providing Processor executes.

Programs or code segments constituting the various embodiments can be stored in computer-readable media. For example, a computer program product comprising program code stored on a computer-readable medium (eg, a non-transitory computer-readable medium) may form various embodiments. "Computer-readable medium" may include any medium that can store or transmit information. Examples of computer readable media include electronic circuits, semiconductor memory devices, read only memory (ROM), flash memory, erasable ROM (EROM), floppy disks, compact disk (CD)-ROMs, and the like.

Those skilled in the art will understand that the previously described embodiments of a power converter including a magnetic structure comprising a U-shaped core on a rectilinear core and associated methods of forming the power converter are for illustrative purposes only. submitted for the purpose. Although the magnetic structure has been described in the context of a power converter, the magnetic structure may also be applied to other systems such as, but not limited to, power amplifiers or motor controllers.

For a better understanding of power converters, see "Modern DC-to-DC Power Switch-mode Power Converter Circuits" by Rudolph P. Severns and Gordon Bloom (Van Nostrand Reinhold Company, New York, NY, 1985), and J.G. Kassakian, M.F. Schlecht and "Principles of Power Electronics" by G.C. Verghese (Addison-Wesley, 1991). The above references are hereby incorporated by reference in their entirety.

Also, although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As those skilled in the art will readily appreciate from the disclosure of the present invention, it is possible to perform substantially the same functions or obtain substantially the same functions according to the present invention to existing or later developed corresponding embodiments as described herein. process, machine, manufacture, composition of matter, means, method or steps resulting in the utilization of Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (20)

1. A controller for use with a power converter, said controller comprising: an inductor-inductor-capacitor (LLC) controller configured to receive an error signal from an error amplifier to control a switching frequency of an LLC stage of the power converter to regulate an output voltage of the power converter; and a power factor correction (PFC) controller configured to control a bus voltage generated by a PFC stage of the power converter and provided to the LLC stage such that an average switching frequency of the LLC stage is substantially maintained at the desired switching frequency. 2. The controller of claim 1, wherein the PFC stage is a PFC boost stage and the LLC stage is an LLC resonant buck stage. 3. The controller of claim 1, wherein a control loop associated with the LLC stage has a faster response than a control loop associated with the PFC stage. 4. The controller of claim 1 , wherein the LLC controller includes a nonlinear function subsystem configured to apply a correction factor to the error signal to produce a corrected error signal . 5. The controller of claim 4, wherein the correction factor is approximated by a broken line correction factor. 6. The controller of claim 4, wherein the LLC controller comprises a voltage controlled oscillator configured to receive the corrected error signal for the The switching frequency is controlled. 7. The controller of claim 1, wherein the PFC controller is configured to boost the bus voltage to generate an error in the error signal to detect light load operation of the power converter. 8. The controller of claim 1, wherein the error amplifier is coupled to a resistor divider configured to sense the output voltage and provide a sensed output voltage to the The error amplifier is an operational amplifier to generate the error signal. 9. The controller of claim 1 , wherein the PFC stage includes at least one error amplifier configured to be a function of the switching frequency of the LLC stage and the desired switching frequency The bus voltage is controlled. 10. The controller of claim 1, further comprising a burst mode controller configured to cause the power converter to enter a burst mode of operation under light load conditions. 11. The controller of claim 1, further comprising a burst mode controller configured to cause the power converter to enter burst when the error signal crosses a burst threshold level. send operation mode. 12. The controller of claim 1, wherein a resistive divider is configured to sense the output voltage, and a first sense switch and a second sense switch coupled to the resistive divider are configured to To reduce power loss when the power converter enters a burst mode of operation. 13. The controller of claim 1, wherein the desired switching frequency is substantially equal to a resonant frequency of the LLC stage. 14. A method of operating a power converter comprising: receiving an error signal from an error amplifier to control a switching frequency of an inductor-inductor-capacitor (LLC) stage of the power converter to regulate an output voltage of the power converter; and A bus voltage generated by a power factor correction (PFC) stage of the power converter and provided to the LLC stage is controlled such that the average switching frequency of the LLC stage is substantially maintained at a desired switching frequency. 15. The method of claim 14, wherein a control loop associated with the LLC stage has a faster response than a control loop associated with the PFC stage. 16. The method of claim 14 , further comprising applying a correction factor to the error signal to produce a corrected error signal and the switching frequency of the LLC stage as a function of the corrected error signal Take control. 17. The method of claim 14, further comprising boosting the bus voltage to generate an error in the error signal to detect light load operation of the power converter. 18. The method of claim 14, further comprising causing the power converter to enter a burst mode of operation under light load conditions. 19. The method of claim 14, further comprising causing the power converter to enter a burst mode of operation when the error signal crosses a burst threshold level. 20. The method of claim 14, further comprising sensing the output voltage, and reducing power loss when the power converter enters a burst mode of operation.

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