CN103531543A - Method for reducing shadow effect in technology for preparing static random access memory - Google Patents
Method for reducing shadow effect in technology for preparing static random access memory Download PDFInfo
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- CN103531543A CN103531543A CN201310491996.6A CN201310491996A CN103531543A CN 103531543 A CN103531543 A CN 103531543A CN 201310491996 A CN201310491996 A CN 201310491996A CN 103531543 A CN103531543 A CN 103531543A
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- 238000005516 engineering process Methods 0.000 title claims abstract description 37
- 230000003068 static effect Effects 0.000 title claims abstract description 34
- 230000000694 effects Effects 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 42
- 239000010703 silicon Substances 0.000 claims abstract description 42
- 238000002513 implantation Methods 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims description 42
- 239000007924 injection Substances 0.000 claims description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 238000002360 preparation method Methods 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000003292 diminished effect Effects 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 abstract 2
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
A method for reducing a shadow effect in a technology for preparing a static random access memory comprises the following steps: step S1, providing a silicon-based substrate and forming shadow trench isolation; step S2, arranging a gate oxide layer and a multi-crystalline silicon gate on the silicon-based substrate, and arranging a source electrode zone and a drain electrode zone at the two sides of the gate oxide layer; step S3, arranging a photo-resistant layer on the surface of the silicon-based substrate, setting a dip angle alpha which is greater than 0 and smaller than 90 degrees between the side wall of the photo-resistant layer and the upper surface of the silicon-based substrate; step S4, implanting ions in a target region by an annular implantation technology. The photo-resistant layer is arranged on the surface of the silicon-based substrate, which is different from that of the gate oxide layer, and the dip angle alpha between the side wall of the photo-resistant layer and the upper surface of the silicon-based substrate is greater than 0 and smaller than 90 degrees, so that the projection area of the implantation direction of annular implantation on the silicon-based substrate is reduced. Therefore, when the annular implantation technology is carried out, the annularly implanted ions can be implanted in the target region to reduce the shadow effect in the technology for preparing the static random access memory.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of method that reduces shadow effect in static random access memory preparation technology.
Background technology
Static random access memory (Static Random Access Memory, SRAM), as the class staple product in semiconductor memory, is widely used in the high speed data exchange systems such as computer, communication, multimedia.
Area is an important measurement index of described static random access memory.In order to save area, normally, the domain of the static random access memory below described 90nm includes source region, polysilicon gate, and three levels of contact hole.Along with the continuous progress of technology, the adjusting of described static random access memory also becomes increasingly complex, and needs if desired specially described control transistor (Pass Gate) to be carried out to threshold value (V
t) regulate.That is, by described static random access memory being carried out to ring-type injection (Hole Implantation), thereby reach the object that regulates control valve threshold voltage.
But, as those skilled in the art, hold intelligibly, when described static random access memory carries out ring-type injection technology, because the sidewall of photoresist layer is perpendicular to described substrate, the projected area of Implantation direction on described substrate is larger, and in described view field, ring-type is injected ion cannot be injected into substrate.More seriously, along with the size of static random access memory is constantly dwindled, distance between described photoresist layer and polysilicon gate, gate oxide is more and more less, in the time of below the projection of described injection direction on described substrate extends to described gate oxide, described ring-type is injected the target area that ion cannot be injected into substrate, and then generation shadow effect, make described control transistor to inject and to carry out threshold voltage adjustments by ring-type.
Therefore the problem existing for prior art, this case designer relies on the industry experience for many years of being engaged in, and active research improvement, so there has been a kind of method that reduces shadow effect in static random access memory preparation technology of the present invention.
Summary of the invention
The present invention be directed in prior art, the size of described traditional static random access memory is constantly dwindled, distance between described photoresist layer and polysilicon gate, gate oxide is more and more less, in the time of below the projection of described injection direction on described substrate extends to described gate oxide, described ring-type is injected the target area that ion cannot be injected into substrate, and then generation shadow effect, make described control transistor to inject defects such as carrying out threshold voltage adjustments by ring-type a kind of method that reduces static random access memory preparation technology shadow effect is provided.
For realizing the present invention's object, the invention provides a kind of method that reduces shadow effect in static random access memory preparation technology, described method comprises:
Execution step S1: silicon-based substrate is provided, and in described silicon-based substrate, form spaced described shallow trench isolation from;
Execution step S2: set gradually gate oxide and polysilicon gate in described silicon-based substrate, and in described gate oxide both sides, lightly-doped source polar region and lightly mixed drain area are set, to form described control transistor;
Execution step S3: the surface that differs from described gate oxide in described silicon-based substrate arranges photoresist layer, and surface has inclination alpha on the sidewall that closes on described gate oxide one side of described photoresist layer and described silicon-based substrate, 0 90 ° of < α <;
Execution step S4: by described ring-type injection technology, Implantation is carried out in described target area.
Alternatively, the inclination alpha that on the sidewall that closes on described gate oxide one side of described photoresist layer and described silicon-based substrate, surface has arranges according to the position of the target area of described ring-type injection.
Alternatively, the arranging of described inclination alpha further comprises and reduces described inclination alpha, the sidewall of described gate oxide one side of closing on of described photoresist layer and the angle β between the injection direction of described ring-type injection are diminished, and then the projected area of the injection direction that makes described ring-type injection in described silicon-based substrate reduce.
Alternatively, described ring-type injection technology is carried out Implantation to described target area, carries out the transistorized threshold voltage adjustments of control of described static random access memory.
In sum, the present invention arranges photoresist layer by the surface that differs from described gate oxide in described silicon-based substrate, and on the sidewall that closes on described gate oxide one side of described photoresist layer and described silicon-based substrate, surface has inclination alpha, 0 90 ° of < α <, when reducing described inclination alpha, the sidewall of described gate oxide one side of closing on of described photoresist layer and the angle β between the injection direction of described ring-type injection are diminished, and then the projected area of the injection direction that makes described ring-type injection in described silicon-based substrate reduces, therefore when carrying out described ring-type injection technology, described ring-type is injected ion just can be injected into target area, to reduce the shadow effect in static random access memory preparation technology.
Accompanying drawing explanation
Figure 1 shows that the present invention reduces the flow chart of the method for shadow effect in static random access memory preparation technology;
Figure 2 shows that the present invention reduces the interim structural representation of the method for shadow effect in static random access memory preparation technology.
Embodiment
By describe in detail the invention technology contents, structural feature, reached object and effect, below in conjunction with embodiment and coordinate accompanying drawing to be described in detail.
Refer to Fig. 1, Figure 1 shows that the present invention reduces the flow chart of the method for shadow effect in static random access memory preparation technology.The method of shadow effect in described reduction static random access memory preparation technology, comprising:
Execution step S1: silicon-based substrate is provided, and in described silicon-based substrate, form spaced described shallow trench isolation from;
Execution step S2: set gradually gate oxide and polysilicon gate in described silicon-based substrate, and in described gate oxide both sides, lightly-doped source polar region and lightly mixed drain area are set, to form described control transistor;
Execution step S3: the surface that differs from described gate oxide in described silicon-based substrate arranges photoresist layer, and surface has inclination alpha on the sidewall that closes on described gate oxide one side of described photoresist layer and described silicon-based substrate, 0 90 ° of < α <;
Execution step S4: by described ring-type injection technology, Implantation is carried out in described target area.
Refer to Fig. 2, and in conjunction with consulting Fig. 1, Figure 2 shows that the present invention reduces the interim structural representation of the method for shadow effect in static random access memory preparation technology.The method of shadow effect in described reduction static random access memory preparation technology, comprising:
Execution step S1: silicon-based substrate 11 is provided, and at the spaced described shallow trench isolation of the interior formation of described silicon-based substrate 11 from 12;
Execution step S2: set gradually gate oxide 13 and polysilicon gate 14 in described silicon-based substrate 11, and in the both sides of described gate oxide 13,15He lightly mixed drain area, lightly-doped source polar region 16 is set, to form described control transistor 10;
Execution step S3: the surface at the described gate oxide 13 of differing from of described silicon-based substrate 11 arranges photoresist layer 17, and on the sidewall that closes on described gate oxide 13 1 sides 171 of described photoresist layer 17 and described silicon-based substrate 11, surface 111 has inclination alpha, 0 90 ° of < α <;
As those skilled in the art, hold intelligibly, on the sidewall that closes on described gate oxide 13 1 sides 171 of described photoresist layer 17 and described silicon-based substrate 11, surface 111 inclination alpha that have can arrange according to the position of the target area 18 of described ring-type injection.Particularly, reduce described inclination alpha, the sidewall 171 of described gate oxide 13 1 sides of closing on of described photoresist layer 17 and the angle β between the injection direction 19 of described ring-type injection are diminished, and then the projected area of the injection direction 19 that makes described ring-type injection in described silicon-based substrate 11 reduce, to reduce the shadow effect in static random access memory preparation technology.
Execution step S4: by described ring-type injection technology, Implantation is carried out in the target area 18 of described silicon-based substrate 11.In described step S4, on the sidewall that closes on described gate oxide 13 1 sides 171 of described photoresist layer 17 and described silicon-based substrate 11, surface 111 has inclination alpha, 0 90 ° of < α <, when reducing described inclination alpha, the sidewall 171 of described gate oxide 13 1 sides of closing on of described photoresist layer 17 and the angle β between the injection direction 19 of described ring-type injection are diminished, and then the projected area of the injection direction 19 that makes described ring-type injection in described silicon-based substrate 11 reduces, therefore when carrying out described ring-type injection technology, described ring-type is injected ion just can be injected into target area 18, to reduce the shadow effect in static random access memory preparation technology.
Apparently, when described injection Implantation is behind described target area 18, the threshold voltage of the control transistor 10 of described static random access memory just can regulate by described ring-type injection technology.
In sum, the present invention arranges photoresist layer by the surface that differs from described gate oxide in described silicon-based substrate, and on the sidewall that closes on described gate oxide one side of described photoresist layer and described silicon-based substrate, surface has inclination alpha, 0 90 ° of < α <, when reducing described inclination alpha, the sidewall of described gate oxide one side of closing on of described photoresist layer and the angle β between the injection direction of described ring-type injection are diminished, and then the projected area of the injection direction that makes described ring-type injection in described silicon-based substrate reduces, therefore when carrying out described ring-type injection technology, described ring-type is injected ion just can be injected into target area, to reduce the shadow effect in static random access memory preparation technology.
Those skilled in the art all should be appreciated that, in the situation that not departing from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any modification or modification fall in the protection range of appended claims and equivalent, think that the present invention contains these modifications and modification.
Claims (4)
1. a method that reduces shadow effect in static random access memory preparation technology, is characterized in that, described method comprises:
Execution step S1: silicon-based substrate is provided, and in described silicon-based substrate, form spaced described shallow trench isolation from;
Execution step S2: set gradually gate oxide and polysilicon gate in described silicon-based substrate, and in described gate oxide both sides, lightly-doped source polar region and lightly mixed drain area are set, to form described control transistor;
Execution step S3: the surface that differs from described gate oxide in described silicon-based substrate arranges photoresist layer, and surface has inclination alpha on the sidewall that closes on described gate oxide one side of described photoresist layer and described silicon-based substrate, 0 90 ° of < α <;
Execution step S4: by described ring-type injection technology, Implantation is carried out in described target area.
2. the method for shadow effect in reduction static random access memory preparation technology as claimed in claim 1, it is characterized in that, the inclination alpha that on the sidewall that closes on described gate oxide one side of described photoresist layer and described silicon-based substrate, surface has arranges according to the position of the target area of described ring-type injection.
3. static random access memory as claimed in claim 2, it is characterized in that, the arranging of described inclination alpha further comprises and reduces described inclination alpha, the sidewall of described gate oxide one side of closing on of described photoresist layer and the angle β between the injection direction of described ring-type injection are diminished, and then the projected area of the injection direction that makes described ring-type injection in described silicon-based substrate reduce.
4. the method for shadow effect in reduction static random access memory preparation technology as claimed in claim 1, it is characterized in that, described ring-type injection technology is carried out Implantation to described target area, carries out the transistorized threshold voltage adjustments of control of described static random access memory.
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| CN201310491996.6A CN103531543A (en) | 2013-10-18 | 2013-10-18 | Method for reducing shadow effect in technology for preparing static random access memory |
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| CN201310491996.6A CN103531543A (en) | 2013-10-18 | 2013-10-18 | Method for reducing shadow effect in technology for preparing static random access memory |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090224290A1 (en) * | 2008-03-06 | 2009-09-10 | Kabushiki Kaisha Toshiba | Two-way Halo Implant |
| CN102623313A (en) * | 2012-03-23 | 2012-08-01 | 上海华力微电子有限公司 | Ring ion injection method, semiconductor device and manufacture method thereof |
| CN103337482A (en) * | 2013-06-17 | 2013-10-02 | 上海集成电路研发中心有限公司 | Static random access memory transistor unit manufacturing method capable of adjusting threshold voltage |
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- 2013-10-18 CN CN201310491996.6A patent/CN103531543A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090224290A1 (en) * | 2008-03-06 | 2009-09-10 | Kabushiki Kaisha Toshiba | Two-way Halo Implant |
| CN102623313A (en) * | 2012-03-23 | 2012-08-01 | 上海华力微电子有限公司 | Ring ion injection method, semiconductor device and manufacture method thereof |
| CN103337482A (en) * | 2013-06-17 | 2013-10-02 | 上海集成电路研发中心有限公司 | Static random access memory transistor unit manufacturing method capable of adjusting threshold voltage |
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Application publication date: 20140122 |