CN103531521A - Method for forming shallow trench isolation structure - Google Patents
Method for forming shallow trench isolation structure Download PDFInfo
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- CN103531521A CN103531521A CN201310491518.5A CN201310491518A CN103531521A CN 103531521 A CN103531521 A CN 103531521A CN 201310491518 A CN201310491518 A CN 201310491518A CN 103531521 A CN103531521 A CN 103531521A
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- isolation structure
- oxide layer
- fleet plough
- plough groove
- groove isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
The invention provides a method for forming a shallow trench isolation structure. The method comprises the following steps of forming a first oxide layer through an SACVD (sub-atmospheric chemical vapor deposition) process, then, executing a dry etching process to remove the weak surface of the first oxide layer, and then, forming a second oxide layer through the SACVD process. The isolation effect of the shallow trench isolation structure formed by the steps is good. A semiconductor device comprising the shallow trench isolation structure has the advantages that the stability is high, and electric leakage or breakdown is not easy to occur.
Description
Technical field
The present invention relates to ic manufacturing technology field, particularly a kind of formation method of fleet plough groove isolation structure.
Background technology
Along with semiconductor technology enters the deep-submicron epoch, 0.18 micron of following element (for example, between the active area of CMOS integrated circuit) mostly adopts fleet plough groove isolation structure (STI) to carry out lateral isolation and makes.And along with constantly the reducing of feature sizes of semiconductor devices, for the size of the fleet plough groove isolation structure of device isolation, also diminish, corresponding, the depth-to-width ratio that is used to form the isolated groove of fleet plough groove isolation structure becomes large.
In existing Advanced Manufacturing Technology, since 45 nm technology node, its shallow ditch groove separation process has started to use on a large scale sub-atmospheric pressure chemical vapour deposition (CVD) (SACVD) technique to carry out trench oxide filling, and coordinates follow-up Technology for Heating Processing to reach tight filling.But with respect to traditional high-density plasma (HDPCVD) technique, although the filling capacity of SACVD technique is significantly enhanced, but when applying this technique, also produced a new integration difficult problem: in the oxide centre position of groove, can form a fragile face (as shown in dotted line circle in Fig. 1), this fragility face is very easy to be subject to the erosion of follow-up wet processing, thereby make the uniformity of subsequent technique control very difficult, cause the isolation performance of fleet plough groove isolation structure not good, the semiconductor device that comprises fleet plough groove isolation structure easily leaks electricity, had a strong impact on the stability of the semiconductor device that comprises fleet plough groove isolation structure.
Therefore, how to avoid forming fragile face in formed fleet plough groove isolation structure, improve the isolation performance of the fleet plough groove isolation structure that forms, just become those skilled in the art's problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide a kind of formation method of fleet plough groove isolation structure, avoid forming fragile face in formed fleet plough groove isolation structure, improve the isolation performance of the fleet plough groove isolation structure that forms, and then improve the performance of the semiconductor device that forms.
For solving the problems of the technologies described above, the invention provides a kind of formation method of fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with some isolated grooves;
By SACVD technique, in described Semiconductor substrate, form the first oxide layer, described the first oxide layer is filled up described isolated groove;
Carry out dry back etching technics, in described the first oxide layer, form a recess;
By SACVD technique, in described the first oxide layer, form the second oxide layer; And
The first oxide layer and the second oxide layer described in planarization, form fleet plough groove isolation structure.
Optionally, in the formation method of described fleet plough groove isolation structure, the etching gas of described dry back etching technics is the mist of H2, He and NF3.
Optionally, in the formation method of described fleet plough groove isolation structure, the radio-frequency power of described dry back etching technics is 500～2000W.
Optionally, in the formation method of described fleet plough groove isolation structure, the H2 flow of described dry back etching technics is 200～1500sccm, and He flow is 50～300sccm, and NF3 flow is 100～1000sccm.
Optionally, in the formation method of described fleet plough groove isolation structure, the time of described dry back etching technics is 2～10s.
Optionally, in the formation method of described fleet plough groove isolation structure, the method that forms some isolated grooves in described Semiconductor substrate comprises:
In Semiconductor substrate, form etching stop layer and hard mask layer;
Hard mask layer and etching stop layer described in etching, form the opening that runs through described hard mask layer and etching stopping layer thickness, and the shape of described opening is corresponding with the shape of isolated groove; And
Take described hard mask layer and etching stop layer as mask, along Semiconductor substrate described in opening etching, form some isolated grooves.
Optionally, in the formation method of described fleet plough groove isolation structure, described etching stop layer is silica, and described hard mask layer is silicon nitride.
Optionally, in the formation method of described fleet plough groove isolation structure, form after isolated groove, also comprise: by thermal oxidation technology, at bottom and the sidewall of described isolated groove, form cushion oxide layer.
Optionally, in the formation method of described fleet plough groove isolation structure, after the first oxide layer and the second oxide layer, utilize hot phosphoric acid to remove described hard mask layer described in planarization.
Optionally, in the formation method of described fleet plough groove isolation structure, the method for the first oxide layer and the second oxide layer is chemical mechanical milling tech described in planarization.
Compared with prior art, technical solution of the present invention has the following advantages:
The present invention forms after the first oxide layer by SACVD technique, carry out dry back etching technics and eliminate the fragile face in the first oxide layer, and then form the second oxide layer by SACVD technique, because the second oxide layer is without filling the larger groove of depth-to-width ratio, therefore can not form fragile face, the isolation effect of the fleet plough groove isolation structure forming is thus good, and the good stability of the semiconductor device that comprises fleet plough groove isolation structure difficultly leaks electricity, punctures.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the fragile face of existing fleet plough groove isolation structure;
Fig. 2 is the schematic flow sheet of an execution mode of formation method of fleet plough groove isolation structure of the present invention;
In embodiment of formation method that Fig. 3 to Fig. 7 is fleet plough groove isolation structure of the present invention the cross-sectional view of formation fleet plough groove isolation structure.
Embodiment
As described in background, along with constantly reducing of feature sizes of semiconductor devices, the size that is used for the fleet plough groove isolation structure of device isolation also diminishes, the depth-to-width ratio that is used to form the isolated groove of fleet plough groove isolation structure becomes large, while filling formation oxide layer in isolated groove by SACVD technique, be prone to fragile face, cause the isolation performance of fleet plough groove isolation structure not good, the semiconductor device that comprises fleet plough groove isolation structure easily leaks electricity, poor stability.For this reason, the present invention forms after the first oxide layer by SACVD technique, carry out dry etch process and eliminate fragile face, and then form the second oxide layer by SACVD technique, and then execution flatening process, the isolation effect of the fleet plough groove isolation structure forming is thus good, and the good stability of the semiconductor device that comprises fleet plough groove isolation structure difficultly leaks electricity, punctures.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here, implement, so the present invention has not been subject to the restriction of following public specific embodiment.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the present invention is described in detail in detail, for ease of explanation, described schematic diagram is example, and it should not limit the scope of protection of the invention at this.
With reference to figure 2, the schematic flow sheet for the execution mode of formation method of fleet plough groove isolation structure of the present invention, comprising:
Step S100: Semiconductor substrate is provided, is formed with some isolated grooves in described Semiconductor substrate;
Step S110: form the first oxide layer in described Semiconductor substrate by SACVD technique, described the first oxide layer is filled up described isolated groove;
Step S120: carry out dry back etching technics, form a recess in described the first oxide layer;
Step S130: form the second oxide layer by SACVD technique in described the first oxide layer;
Step S140: the first oxide layer and the second oxide layer described in planarization, form fleet plough groove isolation structure.
Fig. 3～Fig. 7 shows the cross-sectional view of the fleet plough groove isolation structure that forms in embodiment of formation method of fleet plough groove isolation structure of the present invention, with reference to figure 3～Fig. 7, by specific embodiment, the formation method of fleet plough groove isolation structure of the present invention is described further.
With reference to figure 3, Semiconductor substrate 201 is provided, in described Semiconductor substrate 201, be formed with some isolated grooves 203.Particularly, the material of described Semiconductor substrate 201 can be silicon, germanium silicon or silicon-on-insulator (SOI).In the present embodiment, the material of described Semiconductor substrate 201 is silicon.The method that forms some isolated grooves 203 in Semiconductor substrate 201 comprises: Semiconductor substrate 201 is provided; In described Semiconductor substrate 201, form etching stop layer (pad oxide) 202 and hard mask layer 204; Hard mask layer 204 and etching stop layer 202 described in etching, form the opening that runs through described hard mask layer 204 and etching stop layer 202 thickness, and the shape of described opening is corresponding with the shape of isolated groove; Take described hard mask layer 204 and etching stop layer 202 is mask, along Semiconductor substrate 201 described in opening etching, forms isolated groove 203.Described hard mask layer 204 is silicon nitride, and described etching stop layer 202 is silica (pad oxide).The method that forms described etching stop layer 202 and hard mask layer 204 can be chemical vapour deposition (CVD) (CVD, Chemical Vapor Deposition) technique.Described in etching, the method for Semiconductor substrate 201 can be dry etching, the etching gas of described dry etching is the mist of Cl2, HBr and O2 or the mist of He and CO4, pressure is 10mTorr～30mTorr, its concrete lithographic method is well known to those skilled in the art, and at this, does not repeat.
Continuation, with reference to figure 3, forms cushion oxide layer (liner oxide) 205 by thermal oxidation technology at bottom and the sidewall of described isolated groove 203, to repair the damage of etching technics to silicon substrate.In the present embodiment, the reacting gas of described thermal oxidation technology is the mist of trans-dichloroethylene (DCE, trans-dichloroethylene) and oxygen (O2), wherein, the flow of trans-dichloroethylene is 0.08slm～0.24slm, and the flow of oxygen is 8slm～15slm; The pressure of described thermal oxidation technology is a standard atmospheric pressure (1.013E5Pa).
With reference to figure 4, on described etching stop layer 205, form the first oxide layer 207, described the first oxide layer 207 fills up bottom and sidewall is formed with the isolated groove 203 of etching stop layer 205.In the present embodiment, the material of described the first oxide layer 207 is silica, and the method that forms described the first oxide layer 207 is SACVD technique, and the reacting gas of described SACVD technique is the mist of silane and oxygen, its concrete technique that forms is well known to those skilled in the art, and does not repeat them here.Through present inventor, study discovery, while utilizing SACVD technique to form the first oxide layer, the first oxide layer 207 centre positions at groove can form a fragile face 207a, this fragility face 207a is very easy to be subject to the erosion of follow-up wet processing, thereby make the uniformity of subsequent technique control very difficult, and cause the isolation performance of fleet plough groove isolation structure not good, the semiconductor device that comprises fleet plough groove isolation structure easily leaks electricity, and has had a strong impact on the stability of the semiconductor device that comprises fleet plough groove isolation structure.
With reference to figure 5, carry out dry back etching technics, described dry back etching technics can be got rid of the first oxide layer of a part of thickness, and, owing to thering is a fragile face in the middle of the first oxide layer 207, after dry back etching technics, form a recess 207b, described recess 207b is V-arrangement.In the present embodiment, adopt LAMHDP SPEED Max(SPM-F) board, the etching gas of described dry back etching is the mist of H2, He and NF3, radio-frequency power (RF power) is 500～2000W, H2 flow is 200～1500sccm, He flow is 50～300sccm, and NF3 flow is 100～1000sccm, and the process time is 2～10s.
With reference to figure 6, in described the first oxide layer 207, form the second oxide layer 208, the method that forms described the second oxide layer 208 is SACVD technique, the reacting gas of described SACVD technique is the mist of silane and oxygen, its concrete technique that forms is well known to those skilled in the art, and does not repeat them here.Because this SACVD technique is not to fill the larger groove of depth-to-width ratio, thereby generally can not form fragile face in the second oxide layer 208.Preferably, form the rear execution Technology for Heating Processing of the second oxide layer 208, the first oxide layer 207 and the second oxide layer 208 stabilisations and densification that SACVD technique is formed.The thickness of described the first oxide layer 207 and the second oxide layer 208 can be determined according to the size of concrete isolated groove, the thickness of the first oxide layer 207 at least will guarantee to fill completely described isolated groove, equally, the thickness of the second oxide layer 208 will guarantee to fill and lead up the opening that dry back etching technics forms, and does not repeat them here.
With reference to figure 7, the first oxide layer 207 and the second oxide layer 208 described in planarization, to exposing described hard mask layer 204.In the present embodiment, by the first oxide layer 207 described in chemical mechanical milling tech planarization and the second oxide layer 208.
Subsequently, can utilize hot phosphoric acid to remove described hard mask layer 204, form fleet plough groove isolation structure 207b.Can select whether to remove etching stop layer 202 according to concrete requirement on devices.
In sum, the present invention forms after the first oxide layer by SACVD technique, carry out dry etch process and in the first oxide layer, form a recess, eliminate described fragile face, and then form the second oxide layer by SACVD technique, because the second oxide layer is without filling the larger groove of depth-to-width ratio, therefore can not form fragile face, the isolation effect of the fleet plough groove isolation structure forming is thus good, and the good stability of the semiconductor device that comprises fleet plough groove isolation structure difficultly leaks electricity, punctures.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a formation method for fleet plough groove isolation structure, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with some isolated grooves;
By SACVD technique, in described Semiconductor substrate, form the first oxide layer, described the first oxide layer is filled up described isolated groove;
Carry out dry back etching technics, in described the first oxide layer, form a recess;
By SACVD technique, in described the first oxide layer, form the second oxide layer; And
The first oxide layer and the second oxide layer described in planarization, form fleet plough groove isolation structure.
2. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, the etching gas of described dry back etching technics is the mist of H2, He and NF3.
3. the formation method of fleet plough groove isolation structure as claimed in claim 2, is characterized in that, the radio-frequency power of described dry back etching technics is 500～2000W.
4. the formation method of fleet plough groove isolation structure as claimed in claim 2, is characterized in that, the H2 flow of described dry back etching technics is 200～1500sccm, and He flow is 50～300sccm, and NF3 flow is 100～1000sccm.
5. the formation method of fleet plough groove isolation structure as claimed in claim 2, is characterized in that, the time of described dry back etching technics is 2～10s.
6. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, the method that forms some isolated grooves in described Semiconductor substrate comprises:
In Semiconductor substrate, form etching stop layer and hard mask layer;
Hard mask layer and etching stop layer described in etching, form the opening that runs through described hard mask layer and etching stopping layer thickness, and the shape of described opening is corresponding with the shape of isolated groove; And
Take described hard mask layer and etching stop layer as mask, along Semiconductor substrate described in opening etching, form some isolated grooves.
7. the formation method of fleet plough groove isolation structure as claimed in claim 6, is characterized in that, described etching stop layer is silica, and described hard mask layer is silicon nitride.
8. the formation method of fleet plough groove isolation structure as claimed in claim 6, is characterized in that, forms after isolated groove, also comprises: by thermal oxidation technology, at bottom and the sidewall of described isolated groove, form cushion oxide layer.
9. the formation method of fleet plough groove isolation structure as claimed in claim 6, is characterized in that, after the first oxide layer and the second oxide layer, utilizes hot phosphoric acid to remove described hard mask layer described in planarization.
10. the formation method of fleet plough groove isolation structure as claimed in claim 1, is characterized in that, the method for the first oxide layer and the second oxide layer is chemical mechanical milling tech described in planarization.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010023134A1 (en) * | 1998-03-31 | 2001-09-20 | Hiroyuki Akatsu | Method of manufacturing a semiconductor device including a seamless shallow trench isolation step |
| CN1481014A (en) * | 2002-09-04 | 2004-03-10 | 旺宏电子股份有限公司 | Method for filling in shallow groove isolation structure with high depth-width ratio |
| TW200531206A (en) * | 2003-12-23 | 2005-09-16 | Applied Materials Inc | Improved gap-fill techniques |
| CN101299417A (en) * | 2006-12-07 | 2008-11-05 | 应用材料股份有限公司 | Methods of thin film process |
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2013
- 2013-10-18 CN CN201310491518.5A patent/CN103531521A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010023134A1 (en) * | 1998-03-31 | 2001-09-20 | Hiroyuki Akatsu | Method of manufacturing a semiconductor device including a seamless shallow trench isolation step |
| CN1481014A (en) * | 2002-09-04 | 2004-03-10 | 旺宏电子股份有限公司 | Method for filling in shallow groove isolation structure with high depth-width ratio |
| TW200531206A (en) * | 2003-12-23 | 2005-09-16 | Applied Materials Inc | Improved gap-fill techniques |
| CN101299417A (en) * | 2006-12-07 | 2008-11-05 | 应用材料股份有限公司 | Methods of thin film process |
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