CN103545243B - A kind of forming method of fleet plough groove isolation structure - Google Patents
A kind of forming method of fleet plough groove isolation structure Download PDFInfo
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- CN103545243B CN103545243B CN201310565677.5A CN201310565677A CN103545243B CN 103545243 B CN103545243 B CN 103545243B CN 201310565677 A CN201310565677 A CN 201310565677A CN 103545243 B CN103545243 B CN 103545243B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
The invention provides the forming method of a kind of fleet plough groove isolation structure, after forming the first oxide layer by SACVD technique, perform dry etch process and eliminate the fragile face of the first oxide layer, then the second oxide layer is formed again through SACVD technique, the isolation effect of the fleet plough groove isolation structure being consequently formed is good, comprise the good stability of the semiconductor device of fleet plough groove isolation structure, be not susceptible to electric leakage, puncture.It addition, increase hydrogen passivation technique, described hydrogen passivation technique can eliminate the unsaturated bond of film surface, so that the sedimentation rate of subsequent technique is stable, and finally improves film gauge uniformity.Additionally, adopt oxygen gas plasma to process technique, O2 plasma is utilized effectively to be removed by the hydrogen bond on body structure surface and top layer, to eliminate the Q-time effect of successive process sedimentation rate, so that it is more stable before successive process deposits.
Description
Technical field
The present invention relates to ic manufacturing technology field, particularly to the forming method of a kind of fleet plough groove isolation structure.
Background technology
Along with semiconductor technology enters deep sub-micron era, the element (such as between the active area of CMOS integrated circuit) of less than 0.18 micron mostly adopts fleet plough groove isolation structure (STI) to carry out lateral isolation and makes.And along with the continuous reduction of feature sizes of semiconductor devices, the size for the fleet plough groove isolation structure of device isolation also diminishes, accordingly, the depth-to-width ratio for forming the isolated groove of fleet plough groove isolation structure becomes big.
In existing Advanced Manufacturing Technology, from 45 nm technology node, its shallow ditch groove separation process has begun to large-scale use sub-atmospheric pressure chemical vapour deposition (CVD) (SACVD) technique and carries out trench oxide filling, and coordinates follow-up Technology for Heating Processing to reach tight filling.But relative to traditional high-density plasma (HDPCVD) technique, although the filling capacity of SACVD technique is significantly enhanced, but while applying this technique, also a new integration difficult problem is created: a fragile face (in Fig. 1 shown in dotted line circle) can be formed in the oxide centre position of groove, this fragility face is highly susceptible to the erosion of subsequent wet technique, so that the uniformity controlling of subsequent technique is highly difficult, cause that the isolation performance of fleet plough groove isolation structure is not good, the semiconductor device comprising fleet plough groove isolation structure easily leaks electricity, have a strong impact on the stability of the semiconductor device comprising fleet plough groove isolation structure.
Therefore, how to avoid in the fleet plough groove isolation structure formed, form fragile face, improve the isolation performance of formed fleet plough groove isolation structure, just become those skilled in the art's problem demanding prompt solution.
Summary of the invention
It is an object of the invention to provide the forming method of a kind of fleet plough groove isolation structure, it is to avoid in the fleet plough groove isolation structure formed, form fragile face, improve the isolation performance of formed fleet plough groove isolation structure, and then improve the performance of formed semiconductor device.
For solving above-mentioned technical problem, the present invention provides the forming method of a kind of fleet plough groove isolation structure, including:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with some isolated grooves；
Forming the first oxide layer on the semiconductor substrate by SACVD technique, described first oxide layer fills up described isolated groove；
Perform dry back etching technics, in described first oxide layer, form a recess；
Perform hydrogen passivation technique；
Perform oxygen gas plasma and process technique；
In described first oxide layer, the second oxide layer is formed by SACVD technique；And
Planarize described first oxide layer and the second oxide layer, form fleet plough groove isolation structure.
Optionally, in the forming method of described fleet plough groove isolation structure, described oxygen gas plasma processes the technological parameter of technique and is: O2 flow is 50～500sccm, He flow is 50～300sccm, radio-frequency power 1000～9000W, and the time is 5～60 seconds.
Optionally, in the forming method of described fleet plough groove isolation structure, the technological parameter of described dry back etching technics is: radio-frequency power is 500～2000W, H2 flow is 200～1500sccm, He flow is 50～300sccm, NF3 flow is 100～1000sccm, and the time is 2～10s.
Optionally, in the forming method of described fleet plough groove isolation structure, the technological parameter of described hydrogen passivation technique is: radio-frequency power is 2000～6000W, H2 flow is 500～2000sccm, and the process time is 5～50s.
Optionally, in the forming method of described fleet plough groove isolation structure, the method forming some isolated grooves in described Semiconductor substrate includes:
Form etching stop layer and hard mask layer on a semiconductor substrate；
Etching described hard mask layer and etching stop layer, formed and run through described hard mask layer and the opening of etching stopping layer thickness, the shape of described opening is corresponding with the shape of isolated groove；And
With described hard mask layer and etching stop layer for mask, etch described Semiconductor substrate along opening, form some isolated grooves.
Optionally, in the forming method of described fleet plough groove isolation structure, described etching stop layer is silicon oxide, and described hard mask layer is silicon nitride.
Optionally, in the forming method of described fleet plough groove isolation structure, formed after isolated groove, also include: form cushion oxide layer by the thermal oxidation technology bottom at described isolated groove and sidewall.
Optionally, in the forming method of described fleet plough groove isolation structure, after planarizing described first oxide layer and the second oxide layer, hot phosphoric acid is utilized to remove described hard mask layer.
Optionally, in the forming method of described fleet plough groove isolation structure, the method planarizing described first oxide layer and the second oxide layer is chemical mechanical milling tech.
Compared with prior art, technical solution of the present invention has the advantage that
After the present invention forms the first oxide layer by SACVD technique, perform dry back etching technics and eliminate the fragile face in the first oxide layer, then the second oxide layer is formed again through SACVD technique, due to the groove that the second oxide layer is bigger without filling depth-to-width ratio, thus without forming fragile face, the isolation effect of the fleet plough groove isolation structure being consequently formed is good, comprises the good stability of the semiconductor device of fleet plough groove isolation structure, is not susceptible to electric leakage, punctures.Further, increasing hydrogen passivation (H2passivation) technique, described hydrogen passivation technique can eliminate the unsaturated bond of film surface, so that the sedimentation rate of subsequent technique is stable, and finally improves film gauge uniformity.Additionally, adopt oxygen gas plasma to process technique, O2 plasma is utilized effectively to be removed by the hydrogen bond on body structure surface and top layer, to eliminate the Q-time effect of successive process sedimentation rate, so that more stable before its successive process deposition.
Accompanying drawing explanation
Fig. 1 is the schematic diagram in the fragile face of existing fleet plough groove isolation structure；
Fig. 2 is the schematic flow sheet of one embodiment of forming method of fleet plough groove isolation structure of the present invention；
In one embodiment of the forming method that Fig. 3 to Fig. 7 is fleet plough groove isolation structure of the present invention the cross-sectional view of formation fleet plough groove isolation structure.
Detailed description of the invention
As described in background, continuous reduction along with feature sizes of semiconductor devices, size for the fleet plough groove isolation structure of device isolation also diminishes, depth-to-width ratio for forming the isolated groove of fleet plough groove isolation structure becomes big, when filling formation oxide layer in isolated groove by SACVD technique, fragile face easily occurs, causing that the isolation performance of fleet plough groove isolation structure is not good, the semiconductor device comprising fleet plough groove isolation structure easily leaks electricity, poor stability.For this, after the present invention forms the first oxide layer by SACVD technique, perform dry etch process and eliminate fragile face, then the second oxide layer is formed again through SACVD technique, then flatening process is performed again, the isolation effect of the fleet plough groove isolation structure being consequently formed is good, comprises the good stability of the semiconductor device of fleet plough groove isolation structure, is not susceptible to electric leakage, punctures.It addition, increase hydrogen passivation (H2passivation) technique, described hydrogen passivation technique can eliminate the unsaturated bond of film surface, so that the sedimentation rate of subsequent technique is stable, and finally improves film gauge uniformity.Further, adopt oxygen gas plasma to process technique, utilize O2 plasma effectively to be removed by the hydrogen bond on body structure surface and top layer, to eliminate the Q-time effect of successive process sedimentation rate, so that more stable before its successive process deposition.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Elaborating a lot of detail in the following description so that fully understanding the present invention, but the present invention can also adopt other to be different from alternate manner described here to be implemented, therefore the present invention is not by the restriction of following public specific embodiment.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when describing the embodiment of the present invention in detail, for purposes of illustration only, described schematic diagram is example, it should not limit the scope of protection of the invention at this.
With reference to Fig. 2, for the schematic flow sheet of one embodiment of forming method of fleet plough groove isolation structure of the present invention, including:
Step S100: Semiconductor substrate is provided, is formed with some isolated grooves in described Semiconductor substrate；
Step S110: forming the first oxide layer on the semiconductor substrate by SACVD technique, described first oxide layer fills up described isolated groove；
Step S120: perform dry back etching technics, form a recess in described first oxide layer；
Step S130: perform hydrogen passivation technique；
Step S140: perform oxygen gas plasma and process technique；
Step S150: form the second oxide layer in described first oxide layer by SACVD technique；
Step S160: planarize described first oxide layer and the second oxide layer, forms fleet plough groove isolation structure.
Fig. 3～Fig. 7 illustrates the cross-sectional view of formed fleet plough groove isolation structure in one embodiment of forming method of fleet plough groove isolation structure of the present invention, with reference to Fig. 3～Fig. 7, by specific embodiment, the forming method of fleet plough groove isolation structure of the present invention is described further.
With reference to Fig. 3, it is provided that Semiconductor substrate 201, described Semiconductor substrate 201 is formed with some isolated grooves 203.Specifically, the material of described Semiconductor substrate 201 can be silicon, germanium silicon or silicon-on-insulator (SOI).In the present embodiment, the material of described Semiconductor substrate 201 is silicon.The method forming some isolated grooves 203 in Semiconductor substrate 201 includes: provide Semiconductor substrate 201；Described Semiconductor substrate 201 is formed etching stop layer (padoxide) 202 and hard mask layer 204；Etching described hard mask layer 204 and etching stop layer 202, formed and run through described hard mask layer 204 and the opening of etching stop layer 202 thickness, the shape of described opening is corresponding with the shape of isolated groove；With described hard mask layer 204 and etching stop layer 202 for mask, etch described Semiconductor substrate 201 along opening, form isolated groove 203.Described hard mask layer 204 is silicon nitride, and described etching stop layer 202 is silicon oxide (padoxide).The method forming described etching stop layer 202 and hard mask layer 204 can be chemical vapour deposition (CVD) (CVD, ChemicalVaporDeposition) technique.The method etching described Semiconductor substrate 201 can be dry etching, the etching gas of described dry etching is the mixing gas mixing gas or He and CO4 of Cl2, HBr and O2, pressure is 10mTorr～30mTorr, its concrete lithographic method is well known to those skilled in the art, and does not repeat at this.
With continued reference to Fig. 3, form cushion oxide layer (lineroxide) 205 by the thermal oxidation technology bottom at described isolated groove 203 and sidewall, to repair the etching technics damage to silicon substrate.In the present embodiment, the reacting gas of described thermal oxidation technology is trans-dichloroethylene (DCE, trans-dichloroethylene) and the mixing gas of oxygen (O2), wherein, the flow of trans-dichloroethylene is 0.08slm～0.24slm, and the flow of oxygen is 8slm～15slm；The pressure of described thermal oxidation technology is a normal atmosphere (1.013E5Pa).
With reference to Fig. 4, forming the first oxide layer 207 on described etching stop layer 205, described first oxide layer 207 fills up bottom and sidewall is formed with the isolated groove 203 of etching stop layer 205.In the present embodiment, the material of described first oxide layer 207 is silicon oxide, and the method forming described first oxide layer 207 is SACVD technique, the mixing gas that reacting gas is silane and oxygen of described SACVD technique, its concrete formation process is well known to those skilled in the art, and does not repeat them here.Discovery is studied through present inventor, when utilizing SACVD technique to form the first oxide layer, a fragile face 207a can be formed in the first oxide layer 207 centre position of groove, this fragility face 207a is highly susceptible to the erosion of subsequent wet technique, so that the uniformity controlling of subsequent technique is highly difficult, and cause that the isolation performance of fleet plough groove isolation structure is not good, the semiconductor device comprising fleet plough groove isolation structure easily leaks electricity, and has had a strong impact on the stability of the semiconductor device comprising fleet plough groove isolation structure.
With reference to Fig. 5, performing dry back etching technics, described dry back etching technics can get rid of the first oxide layer of a part of thickness, and, owing to having a fragile face in the middle of the first oxide layer 207, forming a recess 207b after dry back etching technics, described recess 207b is V-arrangement.In the present embodiment, adopt LAMHDPSPEEDMax(SPM-F) board, the mixing gas that etching gas is H2, He and NF3 of described dry back etching, radio-frequency power (RFpower) is 500～2000W, H2 flow is 200～1500sccm, He flow is 50～300sccm, NF3 flow is 100～1000sccm, and the process time is 2～10s.
After performing dry back etching technics, perform hydrogen passivation technique.Described hydrogen passivation technique can eliminate the unsaturated bond of film surface, so that the sedimentation rate of subsequent technique is stable, and finally improves film gauge uniformity.In the present embodiment, adopt LAMHDPSPEEDMax(SPM-F) board, radio-frequency power (RFpower) is 2000～6000W, H2 flow is 500～2000sccm, and the process time is 5～50s.Finding through experiment, hydrogen passivation technique (high-density plasma H2 Passivation Treatment) can make the thickness evenness of laminated construction be greatly improved, when laminated thickness isDuring left and right, in wafer film thickness difference fromIt is reduced to
In practice, it has been found that after performing hydrogen passivation technique, although the unevenness of successive process is significantly improved, but the speed of growth of successive process has obvious Q-time effect, i.e. As time goes on the speed of growth of thin film is more and more slower.Study for a long period of time discovery through present inventor, this is because after performing hydrogen passivation technique there is hydrogen bond in body structure surface, when hydrogen bond exposes in atmosphere, As time goes on, it can change at silicon chip surface and internal distribution, thus affecting the sedimentation rate of follow-up deposition manufacture process.For this, the present invention performs oxygen (O2) plasma-treating technology after performing hydrogen passivation technique, O2 plasma is utilized effectively to be removed by the hydrogen bond on body structure surface and top layer, to eliminate the Q-time effect of successive process sedimentation rate, so that it is more stable before successive process deposits.In the present embodiment, adopt LAMHDPSPEEDMax(SPM-F) board, O2 flow is 50～500sccm, He flow is 50～300sccm, radio-frequency power 1000～9000W, and the time is 5～60 seconds.
With reference to Fig. 6, described first oxide layer 207 forms the second oxide layer 208, the method forming described second oxide layer 208 is SACVD technique, the mixing gas that reacting gas is silane and oxygen of described SACVD technique, its concrete formation process is well known to those skilled in the art, and does not repeat them here.It is not fill the groove that depth-to-width ratio is bigger due to this SACVD technique, thus the second oxide layer 208 generally will not be formed fragile face.It is also preferred that the left perform Technology for Heating Processing after forming the second oxide layer 208, make the first oxide layer 207 and the second oxide layer 208 stabilisation and densification that SACVD technique is formed.The thickness of described first oxide layer 207 and the second oxide layer 208 can be complied with the size of concrete isolated groove and be determined, the thickness of the first oxide layer 207 at least to ensure to be filled up completely with described isolated groove, equally, the thickness of the second oxide layer 208 to ensure to fill and lead up the opening that dry back etching technics is formed, and does not repeat them here.
With reference to Fig. 7, planarize described first oxide layer 207 and the second oxide layer 208, to exposing described hard mask layer 204.In the present embodiment, planarize described first oxide layer 207 and the second oxide layer 208 by chemical mechanical milling tech.
Subsequently, available hot phosphoric acid removes described hard mask layer 204, forms fleet plough groove isolation structure 207b.Can choose whether to remove etching stop layer 202 according to concrete requirement on devices.
In sum, after the present invention forms the first oxide layer by SACVD technique, perform dry etch process in the first oxide layer, form a recess, eliminate described fragile face, then form the second oxide layer again through SACVD technique, due to the groove that the second oxide layer is bigger without filling depth-to-width ratio, thus without forming fragile face, the isolation effect of the fleet plough groove isolation structure being consequently formed is good, comprises the good stability of the semiconductor device of fleet plough groove isolation structure, is not susceptible to electric leakage, punctures.Further, increasing hydrogen passivation (H2passivation) technique, described hydrogen passivation technique can eliminate the unsaturated bond of film surface, so that the sedimentation rate of subsequent technique is stable, and finally improves film gauge uniformity.Additionally, adopt oxygen (O2) plasma-treating technology, O2 plasma is utilized effectively to be removed by the hydrogen bond on body structure surface and top layer, to eliminate the Q-time effect of successive process sedimentation rate, so that it is more stable before successive process deposits.
Although the present invention is with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art are without departing from the spirit and scope of the present invention; may be by the method for the disclosure above and technology contents and technical solution of the present invention is made possible variation and amendment; therefore; every content without departing from technical solution of the present invention; according to any simple modification, equivalent variations and modification that above example is made by the technical spirit of the present invention, belong to the protection domain of technical solution of the present invention.
Claims (8)
1. the forming method of a fleet plough groove isolation structure, it is characterised in that including:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with some isolated grooves；
Forming the first oxide layer on the semiconductor substrate by SACVD technique, described first oxide layer fills up described isolated groove；
Perform dry back etching technics, in described first oxide layer, form a recess；
Performing hydrogen passivation technique, the technological parameter of described hydrogen passivation technique is: radio-frequency power is 2000～6000W, H2 flow is 500～2000sccm, and the process time is 5～50s；
Perform oxygen gas plasma and process technique；
In described first oxide layer, the second oxide layer is formed by SACVD technique；And
Planarize described first oxide layer and the second oxide layer, form fleet plough groove isolation structure.
2. the forming method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, described oxygen gas plasma processes the technological parameter of technique and is: O2 flow is 50～500sccm, He flow is 50～300sccm, radio-frequency power 1000～9000W, the time is 5～60 seconds.
3. the forming method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, the technological parameter of described dry back etching technics is: radio-frequency power is 500～2000W, H2 flow is 200～1500sccm, He flow is 50～300sccm, NF3 flow is 100～1000sccm, and the time is 2～10s.
4. the forming method of fleet plough groove isolation structure as claimed in claim 1, it is characterised in that the method forming some isolated grooves in described Semiconductor substrate includes:
Form etching stop layer and hard mask layer on a semiconductor substrate；
Etching described hard mask layer and etching stop layer, formed and run through described hard mask layer and the opening of etching stopping layer thickness, the shape of described opening is corresponding with the shape of isolated groove；And
With described hard mask layer and etching stop layer for mask, etch described Semiconductor substrate along opening, form some isolated grooves.
5. the forming method of fleet plough groove isolation structure as claimed in claim 4, it is characterised in that described etching stop layer is silicon oxide, and described hard mask layer is silicon nitride.
6. the forming method of fleet plough groove isolation structure as claimed in claim 4, it is characterised in that after forming isolated groove, also include: form cushion oxide layer by the thermal oxidation technology bottom at described isolated groove and sidewall.
7. the forming method of fleet plough groove isolation structure as claimed in claim 4, it is characterised in that after planarizing described first oxide layer and the second oxide layer, utilizes hot phosphoric acid to remove described hard mask layer.
8. the forming method of fleet plough groove isolation structure as claimed in claim 1, it is characterised in that the method planarizing described first oxide layer and the second oxide layer is chemical mechanical milling tech.
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| CN101673660A (en) * | 2008-09-09 | 2010-03-17 | 中芯国际集成电路制造(北京)有限公司 | Processing method of gap filling and manufacturing method of shallow trench isolation groove |
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