CN103531167A

CN103531167A - Serial/parallel data control circuit

Info

Publication number: CN103531167A
Application number: CN201310500253.0A
Authority: CN
Inventors: 曾宏博; 元薇; 徐建强; 林昕
Original assignee: Teralane Semiconductor (Shenzhen) Co Ltd
Current assignee: Teralane Semiconductor (Shenzhen) Co Ltd
Priority date: 2013-10-23
Filing date: 2013-10-23
Publication date: 2014-01-22

Abstract

The invention relates to a serial/parallel data control circuit which comprises a digital circuit, a shift register data conversion unit and a SOURCE circuit which are supported by a power supply unit, wherein the digital circuit receives a CPU (Central Processing Unit) control signal, a CPU interface signal and a reset signal; the shift register data conversion unit is connected with the digital circuit and comprises a shift register circuit and a serial/parallel data conversion circuit; and the SOURCE circuit is connected with the shift register data conversion unit through a DAC (digital-analog converter) circuit and provided with a data output port. Due to a combination of the circuits and structures thereof, a design structure of the serial/parallel data control circuit is realized, and good effects of reducing the product size and product cost are achieved.

Description

A kind of serial/parallel row data control circuit

Technical field

The invention provides a kind of serial/parallel row data control circuit, refer in particular to the serial/parallel row data control circuit of a kind of SRAM of being applicable to.

Background technology

In LCDs drives chip, the display screen that chip can drive is big or small, has just determined the size of SRAM circuit size in chip, and the number of DAC circuit in SOURCE circuit.Generally: be exactly that display screen is larger, in chip area, the shared area of SRAM circuit is just larger, and in SOURCE circuit, the number of DAC circuit is just more.Traditional way is that the output data of SRAM circuit are directly connected with the DAC circuit in SOURCE circuit, and in SRAM circuit and SOURCE circuit, the line between DAC circuit will change along with the variation of display screen size at that rate.

Suppose that the display screen size that chip can drive is M*N (RGB), in this chip, the size of SRAM circuit size is also M*N (RGB) so, in SOURCE circuit, the number of DAC circuit is N*3, the display color of set and display screen is 262K look, in SRAM circuit, the figure place of each pixel is 18bit, so the session number between DAC circuit just equals N*18 in SRAM circuit and SOURCE circuit.

When display screen is reduced size (162*132 (RGB)), the session number in SRAM circuit and SOURCE circuit between DAC circuit just equals N*18=132*18=2376; When display screen is large-size (800*480 (RGB)), the session number in SRAM circuit and SOURCE circuit between DAC circuit just equals N*18=480*18=8640.

For undersized display screen drive chip, more than 2,000 line may be nothing, and still, for large-sized display screen drive chip, more than 8,000 line will occupy the area of major part in domain.Yet for chip, area is the smaller the better.This theory is equally applicable to display screen drive chip.

Summary of the invention

For solving the problems of the technologies described above, the object of the invention is to effectively to reduce display screen drive chip size, and a kind of serial/parallel row data control circuit that reduces cost of products, this kind of serial/parallel row data control circuit is applicable to the serial/parallel row data control circuit of SRAM.

For achieving the above object, the present invention's a kind of serial/parallel row data control circuit, comprise digital circuit, shift LD Date Conversion Unit and the SOURCE circuit by power supply unit, supported, wherein: this digital circuit is accepted CPU control signal, cpu i/f signal and reset signal; This shift LD Date Conversion Unit connects described digital circuit and comprises shift-register circuit and serial/parallel data converting circuit, and this SOURCE circuit is connected this shift LD Date Conversion Unit and had data-out port by DAC circuit.

Preferred in the present embodiment, the input signal of this shift-register circuit comes from digital circuit, and its output signal is exported to this serial/parallel data converting circuit being connected.

Preferred in the present embodiment, this shift-register circuit comprises d type flip flop circuit and logic control circuit.

Preferred in the present embodiment, this d type flip flop circuit forms the d type flip flop circuit with the rising edge triggering of reset function by transmission gate and basic logic unit.

Preferred in the present embodiment, this logic control circuit produces control bus, and described d type flip flop circuit is controlled.

Preferred in the present embodiment, this serial/parallel data converting circuit comprises latch circuit and shift control circuit.

Preferred in the present embodiment, this shift control circuit produces control signal described latch circuit and data input signal is controlled.

Preferred in the present embodiment, this serial/parallel data converting circuit comprises LOGIC CONTROL module and BUFFER module.

Compared with prior art, its beneficial effect is in the present invention: not only can effectively reduce the size of display screen drive chip, and can reduce cost of products.

Accompanying drawing explanation

Fig. 1 is the structural representation that the LCDs of the present embodiment drives chip.

Fig. 2 is the structural representation of shift LD Date Conversion Unit in Fig. 1.

Fig. 3 is the principle schematic of shift-register circuit in Fig. 2.

Fig. 4 is the principle schematic of serial/parallel data converting circuit in Fig. 2.

Embodiment

By describe in detail the present invention technology contents, structural attitude, reached object and effect, below hereby exemplify embodiment and coordinate accompanying drawing to be explained in detail.

Refer to shown in Fig. 1 and in conjunction with consulting shown in Fig. 2, the invention provides a kind of serial/parallel row data control circuit, comprise digital circuit 20, shift LD Date Conversion Unit 30 and the SOURCE circuit 40 by power supply unit 10, supported, wherein: this digital circuit 20 is accepted CPU control signal, cpu i/f signal and reset signal; This shift LD Date Conversion Unit 30 connects described digital circuit 20 and comprises shift-register circuit 31 and serial/parallel data converting circuit 32, and this SOURCE circuit 40 connects this shift LD Date Conversion Unit 30 and had data-out port by DAC circuit, wherein: the session number in this shift-register circuit 31 and this SOURCE circuit between DAC circuit will become 18 from N*18=480*18=8640.

Incorporated by reference to consulting shown in Fig. 3, this shift-register circuit 31, its all input signal all comes from digital circuit 20, and output signal is connected directly to described serial/parallel data converting circuit 32.Reset signal RESET resetted to all d type flip flops before input clock CLK and incoming level signal D arrival, made all d type flip flops be output as low level.When the rising edge of input clock CLK signal arrives, d type flip flop 1 sends incoming level signal D to the output Q of d type flip flop 1, output shift clock SH_CLK<0>, and when the rising edge of input clock CLK signal arrives again, d type flip flop 1 sends incoming level signal D to the output Q of d type flip flop 1 again, output shift clock SH_CLK<0>; D type flip flop 2 sends the output Q of d type flip flop 1 to the output Q of d type flip flop 2 simultaneously, output shift clock SH_CLK<1>.By that analogy, thus output shift clock SH_CLK<N-1:0>.

Incorporated by reference to consulting shown in Fig. 4, this serial/parallel data converting circuit 32 comprises latch, LOGIC CONTROL and BUFFER module, wherein: shift clock SH_CLK<N-1:0>be the output signal from this shift-register circuit 31, and the * 18+17:(N-1 of input data DISP_DATA<(N-1)) * 18>be the parallel output data from SRAM circuit, output data DATA<17:0>be the serial data that will give DAC circuit in SOURCE module, shown in can find out in Fig. 4, latch is used for the parallel data from SRAM circuit at shift clock SH_CLK<N-1:0>be latched in latch while arriving successively, and by LOGIC CONTROL, data are sent through BUFFER.

In sum, only, for the present invention's preferred embodiment, with this, do not limit protection scope of the present invention, all equivalences of doing according to the scope of the claims of the present invention and description change and modify, within being all the scope that patent of the present invention contains.

Claims

1. a serial/parallel row data control circuit, comprises digital circuit, shift LD Date Conversion Unit and the SOURCE circuit by power supply unit, supported, it is characterized in that: this digital circuit is accepted CPU control signal, cpu i/f signal and reset signal; This shift LD Date Conversion Unit connects described digital circuit and comprises shift-register circuit and serial/parallel data converting circuit, and this SOURCE circuit is connected this shift LD Date Conversion Unit and had data-out port by DAC circuit.

2. shift-register circuit as claimed in claim 1, is characterized in that: the input signal of this shift-register circuit comes from digital circuit, and its output signal is exported to this serial/parallel data converting circuit being connected.

3. shift-register circuit as claimed in claim 2, is characterized in that: this shift-register circuit comprises d type flip flop circuit and logic control circuit.

4. shift-register circuit as claimed in claim 3, is characterized in that: this d type flip flop circuit forms the d type flip flop circuit with the rising edge triggering of reset function by transmission gate and basic logic unit.

5. shift-register circuit as claimed in claim 3, is characterized in that: this logic control circuit produces control bus, and described d type flip flop circuit is controlled.

6. shift-register circuit as claimed in claim 2, is characterized in that: this serial/parallel data converting circuit comprises latch circuit and shift control circuit.

7. shift-register circuit as claimed in claim 6, is characterized in that: this shift control circuit produces control signal described latch circuit and data input signal are controlled.

8. shift-register circuit as claimed in claim 6, is characterized in that: this serial/parallel data converting circuit comprises LOGIC CONTROL module and BUFFER module.