CN103529338A - Serial fuse wire power-on state reading circuit and method - Google Patents
Serial fuse wire power-on state reading circuit and method Download PDFInfo
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- CN103529338A CN103529338A CN201310529936.9A CN201310529936A CN103529338A CN 103529338 A CN103529338 A CN 103529338A CN 201310529936 A CN201310529936 A CN 201310529936A CN 103529338 A CN103529338 A CN 103529338A
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Abstract
The invention relates to a serial fuse wire power-on state reading circuit and method. The serial fuse wire power-on state reading circuit comprises a power-on reset and FUSE reading waveform generation circuit, a fuse wire terminal processing module and delay units with the number the same as that of a plurality of fuse wire arrays Fuse_ARRAY, wherein the power-on reset and FUSE reading waveform generation circuit is used for generating a fuse_sense control signal and a fuse_latch control signal used for fuse wire reading and inputting the fuse_sense control signal and the fuse_latch control signal to the input end of the fuse wire array Fuse_ARRAY positioned at the frontmost end; the delay units are arranged between the two adjacent fuse wire arrays; the fuse wire terminal processing module is used for generating a fuse_done signal when receiving a signal sent by the fuse wire array Fuse_ARRAY positioned at the rearmost end and sending the fuse_done signal to the power-on reset and FUSE reading waveform generation circuit. To solve the technical problem of excessively high peak current caused when a chip is electrified and initialized due to a great number of fuse wires in the prior art, the number of the fuse wires in a fuse wire reading process is limited by a serial method, so that the purpose of reducing the peak current in the fuse wire reading process is achieved.
Description
Technical field
The invention belongs to microelectronic circuit designing technique, the application based on laser fuse has proposed a kind of fuse read method of tandem.
Background technology
Complexity day by day along with chip technology, the design objective of modular circuit is also more and more higher, but the existence due to semiconductor process variation, in most cases, the parameter index of circuit design is offset within the specific limits, in order to improve yields, the modes that trim of using in design more, and the net result trimming need to adopt certain form to fix, mostly adopt at present the mode of laser fuse or electric fuse, wherein laser fuse is used the most general.When chip functions is complicated, in order to guarantee the yield of chip, conventionally can use a lot of fuses to trim, state after trimming need to read when chip power initialization, but because fuse quantity is more, although there are means to reduce the power consumption that reads of unit fuse, if thereby reading that the fuse of hundreds of nearly is walked abreast can bring the excessive problem of peak point current to cause: 1, state initialization failure; The problems such as the bolt-lock that 2, peak point current causes or electromigration.
Summary of the invention
More in order to solve existing fuse quantity, when chip power initialization, can bring the excessive technical matters of peak point current, the invention provides a kind of tandem fuse power-up state reading circuit and method, a kind of low-power consumption laser fuse read method, by tandem method restriction fuse, read the fuse number in process, reach and read the object that reduces peak point current in fuse process.
Technical solution of the present invention is:
A kind of fuse power-up state reading circuit of tandem, comprise the delay cell that electrification reset and FUSE read Waveform generating circuit, fuse terminal processing module and equate with a plurality of array of fuses Fuse_ARRAY quantity, wherein array of fuses Fuse_ARRAY is that the electric current reading according to all fuses, the execution efficiency needing and sequencing are divided
Described electrification reset and FUSE read Waveform generating circuit and produce fuse_sense control signal and the fuse_latch control signal reading for fuse, are input to the input end of the array of fuses Fuse_ARRAY being positioned at foremost;
Described delay cell is arranged between two adjacent array of fuses; Described fuse terminal processing module is used for generating fuse_done signal when receiving the signal that is positioned at rearmost end array of fuses Fuse_ARRAY transmission, and sends to electrification reset and FUSE to read Waveform generating circuit.
A fuse power-up state read method, comprises the following steps:
1] electrification reset and fuse read wave generating unit monitoring outer power voltage, first produce the Fuse_latch control signal and the Fuse_sense control signal that for fuse, read when voltage is enough high;
2] Fuse_latch control signal and Fuse_sense control signal enter the first array of fuses FUSE_ARRAY1 that is positioned at front end;
3] state of the first array of fuses FUSE_ARRAY1 generates Fuse_latch2 control signal after reading and finishing and Fuse_sense2 control signal enters into the first delay cell;
4] after Fuse_latch control signal and the delayed cell delay of Fuse_sense control signal, send into the second array of fuses FUSE_ARRAY2;
5] repeating step 2], 3], 4] until Fuse_latch control signal and Fuse_sense control signal enter into last array of fuses FUSE_ARRAYN, reading after end of last array of fuses, Fuse_latch control signal and Fuse_sense control signal enter fuse terminal processing module Fuse_end;
6] fuse terminal processing module Fuse_end produces fuse_done signal, and sends to electrification reset and FUSE to read Waveform generating circuit, represents that whole fuses have read.
Above-mentioned array of fuses Fuse_ARRAY is that the electric current reading according to all fuses, the execution efficiency needing and sequencing are divided.
Advantage that the present invention has is:
1, modularization, is convenient to realize.The present invention uses the unit module of standard to build, and compact conformation and power consumption are little, and area cost is lower.
2, applied range.Of the present inventionly allly need to use the power on field of initial value configuration of laser fuse.
3, the present invention reads for application can significantly reduce the peak point current that fuse causes, and is conducive to the reliably working of chip power init state.
4, the invention provides fuse and read complete indication, can be used for guaranteeing that the state of chip initiation is complete
5, use the present invention's success built-in 138 fuses in certain chip, realize the control of the original state that powers on, the current spike surge current that powers on, work is reliably and with long-term.
Accompanying drawing explanation
Fig. 1 is circuit theory schematic diagram of the present invention; In figure: electrification reset and fuse waveform generation module produce the necessary sequential of read operation; FUSE_ARRAY1/FUSE_ARRAY2/FUSE_ARRAY3 is the array of fuses that tandem connects; Necessity that delay cell produces control signal postpones; FUSE_END is fuse terminal processing module.
Embodiment
The present invention is directed to the application of laser fuse, a kind of low-power consumption has been proposed, the laser fuse state that the powers on reading circuit of tandem, its special character is: in chip power process, by the electrification reset module of chip under the enough state of external voltage, produce the fuse_sense and the fuse_latch signal that for fuse, read, the fuse state that first signal controls first reads, after having read, through one section of delay, the fuse of controlling second portion reads, according to tandem moor, carry out, until last fuse state has read, produce fuse_done, represent that whole fuses have read.
It between array of fuses Fuse_ARRAY, is tandem relation.
The electric current that the arrangement of the fuse of One's name is legion can be read according to fuse and the execution efficiency and the sequencing that need are divided into a plurality of array of fuses Fuse_ARRAY, each array of fuses Fuse_ARRAY comprises one to tens fuse module not waiting, but each array of fuses Fuse_ARRAY) between from signal controlling flow process, be seen as tandem relation.
Between two array of fuses, comprise delay cell.After previous array of fuses Fuse_ARRAY has read, in stable condition for after guaranteeing to read, electric current is got back to normal value simultaneously, before starting next array of fuses Fuse_ARRAY operation, needs delay cell to carry out necessary delay, avoids the stack of electric current.
Fuse terminal processing module (Fuse_end) is placed on after last array of fuses Fuse_ARRAY,
When signal arrives this module, represent that all fuses have read, and module sends fuse_done thus
Signal, indicating fuse reads complete.The generation of fuse terminal processing module is used to indicate fuse state and reads
Complete fuse_done, and feed back to electrification reset and fuse reads wave generating unit.
Circuit theory signal of the present invention is referring to Fig. 1.
Step 1 electrification reset and fuse read wave generating unit monitoring outer power voltage, first produce the control signal Fuse_latch control signal and the Fuse_sense control signal that for fuse, read when voltage is enough high.
Step 2 control signal Fuse_latch control signal and Fuse_sense control signal enter tandem the first array of fuses FUSE_ARRAY1.
The reading of step 3 the first array of fuses FUSE_ARRAY1 finish after Fuse_latch control signal and Fuse_sense control signal enter into delay cell, produce and postpone stable for fuse state.
After step 4Fuse_latch control signal and the delayed cell delay of Fuse_sense control signal control signal, send into the second array of fuses FUSE_ARRAY2.
Step 5 repeating step 2,3,4 is until Fuse_latch control signal and Fuse_sense control signal arrive last array of fuses, reading after end of last array of fuses state, Fuse_latch4 and Fuse_sense4 enter into fuse terminal processing module (Fuse_end).
Step 6 fuse terminal processing module Fuse_end produces fuse_done signal, represents that whole fuse states read complete, and returns to electrification reset and fuse reads wave generating unit.
Of the present inventionly main be specially that the process that reads by array of fuses is that tandem is worked, only have an array to carry out reading of fuse at every turn, after having operated, carry out again next, in the course of work, only read the fuse of limited quantity at every turn, reduced the peak power powering on, meanwhile, can according to the practical application of chip, distinguish the sequencing that reads of fuse state, improve the reliability powering on.
Claims (3)
1. the fuse power-up state reading circuit of a tandem, it is characterized in that: comprise the delay cell that electrification reset and FUSE read Waveform generating circuit, fuse terminal processing module and equate with a plurality of array of fuses Fuse_ARRAY quantity, wherein array of fuses Fuse_ARRAY is that the electric current reading according to all fuses, the execution efficiency needing and sequencing are divided
Described electrification reset and FUSE read Waveform generating circuit and produce fuse_sense control signal and the fuse_latch control signal reading for fuse, are input to the input end of the array of fuses Fuse_ARRAY being positioned at foremost;
Described delay cell is arranged between two adjacent array of fuses; Described fuse terminal processing module is used for generating fuse_done signal when receiving the signal that is positioned at rearmost end array of fuses Fuse_ARRAY transmission, and sends to electrification reset and FUSE to read Waveform generating circuit.
2. a tandem fuse power-up state read method, is characterized in that: comprise the following steps:
1] electrification reset and fuse read wave generating unit monitoring outer power voltage, first produce the Fuse_latch control signal and the Fuse_sense control signal that for fuse, read when voltage is enough high;
2] Fuse_latch control signal and Fuse_sense control signal enter the first array of fuses FUSE_ARRAY1 that is positioned at front end;
3] state of the first array of fuses FUSE_ARRAY1 generates Fuse_latch2 control signal after reading and finishing and Fuse_sense2 control signal enters into the first delay cell;
4] after Fuse_latch control signal and the delayed cell delay of Fuse_sense control signal, send into the second array of fuses FUSE_ARRAY2;
5] repeating step 2], 3], 4] until Fuse_latch control signal and Fuse_sense control signal enter into last array of fuses FUSE_ARRAYN, reading after end of last array of fuses, Fuse_latch control signal and Fuse_sense control signal enter fuse terminal processing module Fuse_end;
6] fuse terminal processing module Fuse_end produces fuse_done signal, and sends to electrification reset and FUSE to read Waveform generating circuit, represents that whole fuses have read.
3. tandem fuse power-up state read method according to claim 2, is characterized in that: described array of fuses Fuse_ARRAY is that the electric current reading according to all fuses, execution efficiency and the sequencing of needs are divided.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310529936.9A CN103529338B (en) | 2013-10-30 | 2013-10-30 | A kind of fuse power-up state reading circuit of tandem and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310529936.9A CN103529338B (en) | 2013-10-30 | 2013-10-30 | A kind of fuse power-up state reading circuit of tandem and method |
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| CN103529338A true CN103529338A (en) | 2014-01-22 |
| CN103529338B CN103529338B (en) | 2016-02-24 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261399A (en) * | 2015-11-16 | 2016-01-20 | 西安华芯半导体有限公司 | Method for improving utilization efficiency of standby storage array |
| CN105281728A (en) * | 2014-06-12 | 2016-01-27 | 华邦电子股份有限公司 | Semiconductor device |
| CN108335717A (en) * | 2018-02-07 | 2018-07-27 | 深圳市创新微源半导体有限公司 | A kind of permanent configuration circuit of novel post package |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994018677A1 (en) * | 1993-02-11 | 1994-08-18 | Creative Intergrated Systems, Inc. | Improvements in a very large scale integrated planar read only memory |
| US6459652B1 (en) * | 2001-07-04 | 2002-10-01 | Samsung Electronics Co., Ltd. | Semiconductor memory device having echo clock path |
| US20050076274A1 (en) * | 2003-10-03 | 2005-04-07 | Takeshi Nagai | Semiconductor integrated circuit |
| CN1941206A (en) * | 2005-09-26 | 2007-04-04 | 旺宏电子股份有限公司 | Method and circuit for reading fuse cells in a nonvolatile memory during power-up |
| CN1945744A (en) * | 2005-10-06 | 2007-04-11 | 国际商业机器公司 | Apparatus and method for using fuse to store PLL configuration data |
| US20070189088A1 (en) * | 2006-02-16 | 2007-08-16 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit and testing method therefor |
| CN101131874A (en) * | 2006-08-22 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and test method thereof |
| CN201392350Y (en) * | 2009-03-18 | 2010-01-27 | 上海华岭集成电路技术有限责任公司 | Probe card for anti-interference asynchronous trimming wafer test |
| CN102749575A (en) * | 2011-04-18 | 2012-10-24 | 安凯(广州)微电子技术有限公司 | Electronic fuse state reader |
| CN103295640A (en) * | 2012-02-27 | 2013-09-11 | 三星电子株式会社 | Semiconductor device capable of rescuing defective characteristics occurring after packaging |
-
2013
- 2013-10-30 CN CN201310529936.9A patent/CN103529338B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994018677A1 (en) * | 1993-02-11 | 1994-08-18 | Creative Intergrated Systems, Inc. | Improvements in a very large scale integrated planar read only memory |
| US6459652B1 (en) * | 2001-07-04 | 2002-10-01 | Samsung Electronics Co., Ltd. | Semiconductor memory device having echo clock path |
| US20050076274A1 (en) * | 2003-10-03 | 2005-04-07 | Takeshi Nagai | Semiconductor integrated circuit |
| CN1941206A (en) * | 2005-09-26 | 2007-04-04 | 旺宏电子股份有限公司 | Method and circuit for reading fuse cells in a nonvolatile memory during power-up |
| CN1945744A (en) * | 2005-10-06 | 2007-04-11 | 国际商业机器公司 | Apparatus and method for using fuse to store PLL configuration data |
| US20070189088A1 (en) * | 2006-02-16 | 2007-08-16 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit and testing method therefor |
| CN101131874A (en) * | 2006-08-22 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and test method thereof |
| CN201392350Y (en) * | 2009-03-18 | 2010-01-27 | 上海华岭集成电路技术有限责任公司 | Probe card for anti-interference asynchronous trimming wafer test |
| CN102749575A (en) * | 2011-04-18 | 2012-10-24 | 安凯(广州)微电子技术有限公司 | Electronic fuse state reader |
| CN103295640A (en) * | 2012-02-27 | 2013-09-11 | 三星电子株式会社 | Semiconductor device capable of rescuing defective characteristics occurring after packaging |
Non-Patent Citations (1)
| Title |
|---|
| 赵聚朝: "反熔丝FPGA的电离总剂量效应与加固技术", 《核电子学与探测技术》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105281728A (en) * | 2014-06-12 | 2016-01-27 | 华邦电子股份有限公司 | Semiconductor device |
| CN105281728B (en) * | 2014-06-12 | 2018-06-15 | 华邦电子股份有限公司 | Semiconductor device |
| CN105261399A (en) * | 2015-11-16 | 2016-01-20 | 西安华芯半导体有限公司 | Method for improving utilization efficiency of standby storage array |
| CN105261399B (en) * | 2015-11-16 | 2018-05-18 | 西安紫光国芯半导体有限公司 | The method for improving slack storage array utilization ratio |
| CN108335717A (en) * | 2018-02-07 | 2018-07-27 | 深圳市创新微源半导体有限公司 | A kind of permanent configuration circuit of novel post package |
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| Publication number | Publication date |
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| CN103529338B (en) | 2016-02-24 |
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Effective date of registration: 20221206 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No.15, Jinye 2nd Road, Xi'an, Shaanxi 710119 Patentee before: 631ST Research Institute OF AVIC |