CN101277027A - Selection circuit for Single-chip integrated power supply - Google Patents
Selection circuit for Single-chip integrated power supply Download PDFInfo
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- CN101277027A CN101277027A CNA2008100206969A CN200810020696A CN101277027A CN 101277027 A CN101277027 A CN 101277027A CN A2008100206969 A CNA2008100206969 A CN A2008100206969A CN 200810020696 A CN200810020696 A CN 200810020696A CN 101277027 A CN101277027 A CN 101277027A
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Abstract
The present invention relates to an integrated power supply selection circuit which is integrated on a single chip together with the integrated circuit. The invention mainly settles the technical problems of no high chip integrity caused by that the adopted electric power source selecting circuit is arranged at the outside of the integrated circuit chip when a non-single power supply source is adopted in the existing integrated circuit chip and the fast battery consumption as the batteries can not be guaranteed to be switched off simultaneously when the electricity is supplied by an USB electric power source. The circuit comprises each power tube integrated on the single chip. The input end of each power tube is respectively connected with each electric power supply source. The output end is respectively connected with the level switching circuit. The control end is respectively connected with a switch control circuit which controls the conducting of a power tube in each power tube. The rest power tubes are closed thereby selecting the power supplying of the power supply source connected with the input end of the conducting power tube. The invention increases the chip integrity and reduces the producing cost. When the USB electric power is selected for power supplying, the battery which is connected with the chip at the same time can be guaranteed to be switched off to avoid the additional consumption of the battery.
Description
Technical field
The present invention relates to the power supply of integrated circuit, relate in particular to the power selection circuit that the non-single power supply of integrated circuit is possessed selection function, and described power selection circuit and described integrated circuit are integrated in the same chip.
Background technology
When integrated circuit (IC) chip adopts non-single power supply to power, generally can power with powered battery or USB power supply, both choose with power selection circuit.The external diode of available technology adopting constitutes power selection circuit, its shortcoming is that power selection circuit places the integrated circuit (IC) chip outside, cause the integrated circuit (IC) chip integrated level not high, and when battery with the USB power supply inserts integrated circuit (IC) chip simultaneously and when being powered by the USB power supply, can not guarantee that this moment, battery was disconnected, cause battery consumption fast.
Summary of the invention
The present invention mainly solve existing power supply select circuit place the integrated circuit (IC) chip outside cause chip integration not high, when powering, can not guarantee that battery is disconnected simultaneously by the USB power supply---cause the fast technical problem of battery consumption, design a kind of power selection circuit that can be integrated in single chip simultaneously with integrated circuit, when integrated circuit (IC) chip was selected a kind of power supply of non-single power supply with this power selection circuit, another kind of power supply can disconnect.
Technical scheme of the present invention is as follows:
Selection circuit for Single-chip integrated power supply, comprise each power tube that is integrated in monolithic, the input of described each power tube is connected with each power supply respectively, the output of each power tube is connected with level shifting circuit respectively, the control end of each power tube is connected with ON-OFF control circuit respectively, described ON-OFF control circuit is controlled a power tube conducting in each power tube, meanwhile controls all the other power tubes and ends, and selects the power supply power supply that is connected with described conducting power tube input thus.
Above described power tube the best be the PMOS power tube.Further, described power tube is two PMOS power tubes, and the source end of two PMOS power tubes is connected with battery and USB power supply respectively, and the drain terminal of two PMOS power tubes is connected with linear voltage-stabilizing circuit and DC converting circuit respectively; The grid end of two PMOS power tubes is connected with ON-OFF control circuit respectively, control a conducting in two PMOS power tubes, meanwhile control another PMOS power tube and end, select the described power supply power supply that is connected with conducting PMOS power tube source end thus.
Above described ON-OFF control circuit be a comparator control circuit, USB electric power output voltage and real-time clock supply voltage pass through electric resistance partial pressure respectively, be connected on the positive and negative input of voltage comparator, the output voltage of voltage comparator is connected on the grid end of a PMOS power tube through the anti-phase control signal that obtains once, and the output voltage of voltage comparator is connected on the grid end of another PMOS power tube through the anti-phase control signal that obtains of secondary.
When above-mentioned real-time clock supply voltage passes through electric resistance partial pressure, dividing point is connected on the negative terminal of voltage comparator, be connected divider resistance between real-time clock supply voltage and the dividing point, be connected divider resistance and NMOS pipe between dividing point and the earth terminal, wherein divider resistance is connected with the drain terminal of NMOS pipe, the source end of NMOS pipe connects earth terminal, and the grid end of NMOS pipe connects USB electric power output voltage end.
The present invention adopts two to be integrated in PMOS power tube and ON-OFF control circuit thereof in the single chip simultaneously with integrated circuit, control two PMOS power tubes conducting or end, realization is to the selection of the power supply that is connected with two PMOS power tubes, improved chip integration thus, reduce the number of chip periphery interface unit, reduced cost, be more suitable in suitability for industrialized production.When selection is powered by the USB power supply, can guarantee that the battery that is connected in chip simultaneously is disconnected, avoid battery consumption.
Description of drawings
Fig. 1 is the block diagram of circuit structure of the present invention;
Fig. 2 is the circuit connection diagram of the embodiment of the invention.
Embodiment
Below in conjunction with description of drawings the specific embodiment of the present invention.
The circuit connection description:
Fig. 1 is the block diagram of circuit structure of the present invention, or the schematic diagram of circuit structure of the present invention, and Fig. 2 is the circuit connection diagram of the embodiment of the invention.See Fig. 1 and Fig. 2, the present invention includes two the PMOS power tubes 6 (Mvbus) and 7 (Mbatt) that are integrated in single-chip 18, PMOS power tube 6 and 7 source end are connected with the USB power supply by chip external pin 1 respectively and pass through chip external pin 2 and be connected with battery 19.PMOS power tube 6,7 grid end is connected with ON-OFF control circuit respectively, described ON-OFF control circuit is the control circuit that a comparator 14 constitutes, the 1.8v power supply RTC_VDD (this power supply exists all the time) of USB electric power output voltage VBUS and real-time clock is respectively by each resistance 1402 dividing potential drop, when wherein USB electric power output voltage VBUS is by resistance 1402 dividing potential drops, dividing point is connected on the positive input terminal of voltage comparator 14, when real-time clock supply voltage RTC_VDD passes through resistance 1402 dividing potential drops, dividing point is connected on the negative input end of voltage comparator, be connected divider resistance between real-time clock supply voltage and the dividing point, be connected divider resistance and NMOS pipe 1401 between dividing point and the earth terminal, wherein divider resistance is connected with the drain terminal of NMOS pipe 1401, the source end of NMOS pipe 1401 connects earth terminal, the grid end of NMOS pipe 1401 connects USB electric power output voltage end, be connected in the divider resistance Rpd of NMOS pipe grid end among Fig. 2, NMOS pipe grid end is applied a normal voltage.Negative input end at voltage comparator 14 by the effect that divider resistance 1402 inserts NMOS pipe 1401 is: have only when USB powers, NMOS pipe 1401 is just opened, this moment, comparator 14 ability operate as normal were carried out voltage ratio, otherwise comparator 14 outputs are always high level.The output voltage of voltage comparator 14 through inverter 17 once the control signal SW_VBUS of anti-phase output be connected on the grid end of PMOS power tube 6, the output voltage of voltage comparator 14 is anti-phase through inverter 15 and 16 secondaries, and the control signal SW_BATT of output is connected on the grid end of another PMOS power tube 7.
See Fig. 1 and Fig. 2, PMOS power tube 6 and 7 drain terminal link together, receive the chip external pin 20 (VDD_OUT) of single-chip 18, be connected with chip external pin 3 (VDD_IN) by the outer connecting line of chip, pin 3 connects linear voltage-stabilizing circuit 8 and the DC converting circuit 9 that is integrated in the single-chip 18 respectively, linear voltage-stabilizing circuit 8 and DC converting circuit 9 all are level shifting circuit, wherein carry out level conversion by linear voltage-stabilizing circuit 8, chip external pin 4 (V30_OUT) output 3.0V DC level by single-chip 18, wherein carry out level conversion, by chip external pin 5 (V18_OUT) the output 1.8V DC level of single-chip 18 by DC converting circuit 9.Linear voltage-stabilizing circuit 8 and DC converting circuit 9 can adopt its prior art to design and make by the requirement of above-mentioned level conversion.In the present embodiment, PMOS power tube 6 and 7 technology routinely designs and makes, and embodiment adopts the PMOS power tube of 3.3V under the 0.18um.Voltage comparator 14 and each inverter 15,16,17 also can design and make by its custom integrated circuit structure.
See Fig. 1 and Fig. 2, the output of voltage comparator 14 and the once anti-phase output of process inverter 15 obtain register controlled signal 12 (BATT_STS) and 13 (VBUS_STS) respectively, insert electric power management circuit 10.When length inserts by start or USB electric power output voltage VBUS, electric power management circuit 10 output control signals, insert the control end of linear voltage-stabilizing circuit 8 and DC converting circuit 9 respectively, the effect of electric power management circuit 10 is the voltage of PMOS power tube 6 and 7 to be exported effectively distribute and control.The hardware of electric power management circuit 10 and software can adopt prior art to design and make.
11 for producing real-time clock 1.8v power supply and linear voltage-stabilizing circuit thereof among Fig. 2, it in fact also is a level shifting circuit, its input inserts power supply of USB power supply or powered battery by the outer pair of diodes of chip, 4.2 volts of voltages for example, output output real-time clock 1.8v voltage, circuit 11 adopts the prior art circuit, and adopts its corresponding integrated circuit prior art to design and make.
Layout design in the embodiment of the invention and manufacture craft are by existing routine techniques.
The explanation of circuit working principle
When battery 19 was powered separately by chip external pin 2, this moment, NMOS managed the access that 1401 grids do not have USB electric power output voltage VBUS, and NMOS pipe 1401 turn-offs.Owing to be connected in the effect of the pull down resistor of comparator 14 anodes, the anode of comparator 14 is always zero level, owing to be connected in the effect of the pull-up resistor of comparator 14 negative terminals, the negative terminal of comparator 14 is a high level, so the output signal of voltage comparator 14 is always zero level, through the level translation of an inverter 17, the output SW_VBUS of inverter 17 is a high level.Meanwhile, the zero level output signal of voltage comparator 14 is through the level translation of inverter 15 and 16 secondary inverters, the output SW_BATT of inverter 16 is a zero level, PMOS power tube 6 turn-offs thus, PMOS power tube 7 is opened, and battery 19 is powered separately by the integrated circuit on chip external pin 2 and 7 pairs of chips 18 of PMOS power tube.In like manner, when the USB power supply inserted by chip external pin 1, USB electric power output voltage VBUS put on NMOS and manages 1401 grids, and NMOS manages 1401 conductings.Comparator 14 negative terminals obtain the negative terminal incoming level by the dividing potential drop of resistance string, anode is also because the access of VBUS, obtain the anode incoming level by the resistance string dividing potential drop, the output level of comparator 14 is positive and negative terminal incoming level result relatively, as long as suitably regulate the ratio of resistance string, make voltage comparator 14 anode incoming levels surpass certain value, voltage comparator 14 is just exported high level, level translation through an inverter 17, the output SW_VBUS of inverter 17 is a zero level, level translation through inverter 15 and 16 secondary inverters, the output SW_BATT of inverter 16 is a high level, and PMOS power tube 6 is opened thus, and PMOS power tube 7 turn-offs, thereby cut off the powered battery that is connected with PMOS power tube 7, the USB power supply is powered separately by the integrated circuit on chip external pin 1 and 6 pairs of chips 18 of PMOS power tube.Thereby finish the selection of the present invention to power supply.
In above-mentioned selection course to power supply, when electric power management circuit 10 has detected the power supply access, produce high-level control signal, control linear voltage-stabilizing circuit 8 and DC converting circuit 9 are opened, respectively by chip external pin 4 and 5 output direct current changing voltages.
Claims (5)
1. selection circuit for Single-chip integrated power supply, it is characterized in that comprising each power tube that is integrated in monolithic, the input of described each power tube is connected with each power supply respectively, the output of each power tube is connected with level shifting circuit respectively, the control end of each power tube is connected with ON-OFF control circuit respectively, described ON-OFF control circuit is controlled a power tube conducting in each power tube, meanwhile control all the other power tubes and end, select the power supply power supply that is connected with described conducting power tube input thus.
2. according to the described selection circuit for Single-chip integrated power supply of claim 1, it is characterized in that described power tube is the PMOS power tube.
3, according to claim 1 or 2 described selection circuit for Single-chip integrated power supply, it is characterized in that described power tube is two PMOS power tubes, the source end of two PMOS power tubes is connected with battery and USB power supply respectively, and the drain terminal of two PMOS power tubes is connected with linear voltage-stabilizing circuit and DC converting circuit respectively; The grid end of two PMOS power tubes is connected with ON-OFF control circuit respectively, control a conducting in two PMOS power tubes, meanwhile control another PMOS power tube and end, select the described power supply power supply that is connected with conducting PMOS power tube source end thus.
4, according to the described selection circuit for Single-chip integrated power supply of claim 3, it is characterized in that described ON-OFF control circuit is a comparator control circuit, USB electric power output voltage and real-time clock supply voltage pass through electric resistance partial pressure respectively, dividing point is connected on the positive and negative input of voltage comparator respectively, the output voltage of voltage comparator is connected on the grid end of a PMOS power tube through the anti-phase control signal that obtains once, and the output voltage of voltage comparator is connected on the grid end of another PMOS power tube through the anti-phase control signal that obtains of secondary.
5, according to the described selection circuit for Single-chip integrated power supply of claim 4, when it is characterized in that described real-time clock supply voltage by electric resistance partial pressure, dividing point is connected on the negative terminal of voltage comparator, be connected divider resistance between real-time clock supply voltage and the dividing point, be connected divider resistance and NMOS pipe between dividing point and the earth terminal, wherein divider resistance is connected with the drain terminal of NMOS pipe, and the source end of NMOS pipe connects earth terminal, and the grid end of NMOS pipe connects USB electric power output voltage end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100206969A CN101277027A (en) | 2008-02-22 | 2008-02-22 | Selection circuit for Single-chip integrated power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100206969A CN101277027A (en) | 2008-02-22 | 2008-02-22 | Selection circuit for Single-chip integrated power supply |
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| CN101277027A true CN101277027A (en) | 2008-10-01 |
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| CNA2008100206969A Pending CN101277027A (en) | 2008-02-22 | 2008-02-22 | Selection circuit for Single-chip integrated power supply |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366214A (en) * | 2012-04-11 | 2013-10-23 | 国民技术股份有限公司 | Power supply control circuit and power supply control method |
| CN103683481A (en) * | 2013-12-27 | 2014-03-26 | 无锡致新电子科技有限公司 | Non-loss monolithic integration power supply selective circuit |
| CN103930848A (en) * | 2011-06-24 | 2014-07-16 | 英特尔公司 | Power management for an electronic device |
| CN114285152A (en) * | 2021-12-27 | 2022-04-05 | 杭州万高科技股份有限公司 | Chip power supply switching circuit with multiple power supplies for power supply |
-
2008
- 2008-02-22 CN CNA2008100206969A patent/CN101277027A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103930848A (en) * | 2011-06-24 | 2014-07-16 | 英特尔公司 | Power management for an electronic device |
| CN103930848B (en) * | 2011-06-24 | 2016-08-24 | 英特尔公司 | Power management for electronic equipment |
| CN103366214A (en) * | 2012-04-11 | 2013-10-23 | 国民技术股份有限公司 | Power supply control circuit and power supply control method |
| CN103366214B (en) * | 2012-04-11 | 2016-08-03 | 国民技术股份有限公司 | Power control circuit and power control method |
| CN103683481A (en) * | 2013-12-27 | 2014-03-26 | 无锡致新电子科技有限公司 | Non-loss monolithic integration power supply selective circuit |
| CN114285152A (en) * | 2021-12-27 | 2022-04-05 | 杭州万高科技股份有限公司 | Chip power supply switching circuit with multiple power supplies for power supply |
| WO2022252714A1 (en) * | 2021-12-27 | 2022-12-08 | 杭州万高科技股份有限公司 | Multi-power-supply chip power supply switching circuit |
| CN114285152B (en) * | 2021-12-27 | 2023-05-16 | 杭州万高科技股份有限公司 | Multi-power-supply chip power supply switching circuit |
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Open date: 20081001 |