CN103515292A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN103515292A CN103515292A CN201210203519.0A CN201210203519A CN103515292A CN 103515292 A CN103515292 A CN 103515292A CN 201210203519 A CN201210203519 A CN 201210203519A CN 103515292 A CN103515292 A CN 103515292A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
A method for forming a semiconductor structure comprises: providing a substrate; forming a dielectric layer on the surface of the substrate; forming a boron nitride layer on the dielectric layer; etching the boron nitride layer and the dielectric layer until the substrate is exposed, thereby forming an opening; back-etching the boron nitride layer at the two sides of the opening, thereby increasing the width on the upper portion of the opening; and filling a metal layer in the opening. According to the method for forming the semiconductor structure, the width of the opening in the semiconductor structure is increased by back-etching the boron nitride layer, so that the metal layer is filled in the opening favorably, the formed metal layer is prevented from containing cavities, and electrical performance of the formed semiconductor device is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of formation method of semiconductor structure.
Background technology
Along with the making of integrated circuit develops to very lagre scale integrated circuit (VLSIC) (ULSI), its inner current densities is increasing, contained number of elements constantly increases, and makes the surface of wafer cannot provide enough areas to make required interconnection line (Interconnect).For co-operating member dwindles rear increased interconnection line demand, utilize the design of the two-layer above multiple layer metal interconnection line that through hole realizes, become the method that very large scale integration technology institute must employing.
Traditional metal interconnectedly realized by aluminium, but along with constantly the dwindling of device feature size in integrated circuit (IC) chip, the current density in metal connecting line constantly increases, the response time constantly shortens, and conventional aluminum interconnection line has reached technological limits.After process is less than 130nm, traditional aluminum interconnecting technology is replaced by copper interconnecting line technology gradually.With aluminum metallic matrix ratio, the resistivity of copper metal is lower, electromigration lifetime is longer, utilizes process for copper to make RC that metal interconnecting wires can reduce interconnection line and postpones, improves the integrity problem that electromigration etc. causes.But, adopt process for copper to make interconnection line and also have two problems: the one, the diffusion velocity of copper is very fast, and the 2nd, the etching difficulty of copper, therefore, its applicable manufacturing process is completely different from aluminium technique, conventionally can adopt mosaic texture to realize in the mode of filling.
Yet, along with constantly reducing of semiconductor technology node, critical size (the CD of the groove in semiconductor device and through hole, critical dimension) also corresponding reducing, while filling copper metal in groove and through hole, easily produce cavity, have a strong impact on the electric property of formed semiconductor device.In addition, existing technique groove and through hole are carried out to copper conventionally can be at groove and through-hole side wall deposited barrier layer and inculating crystal layer, to improve the adhesiveness of copper metal and groove or through-hole side wall and to prevent that copper atom from spreading to dielectric layer by sidewall before metal filled.But when groove and through-hole side wall deposition of adhesion and inculating crystal layer, the adhesion layer depositing and inculating crystal layer easily form projection at groove and via openings place, further reduced the width of the groove that forms and via openings, have a strong impact on the metal filled technique of follow-up copper, cause producing in formed copper metal interconnecting wires empty.
With reference to figure 1, for existing technique forms the cross-sectional view of copper semiconductor structure, the technique that forms copper semiconductor structure is as follows: first, and copper blocking layer 103 and low-k interlayer dielectric layer 105 on substrate 101; Then, etching low dielectric constant interlayer dielectric layer 105, forms through hole; Follow again, in via bottoms and sidewall, form barrier layer 107, to improve the adhesiveness between the copper metal of follow-up filling and the low-k interlayer dielectric layer 105 of through-hole side wall, and prevent that copper atom is generally Ta, TaN or Ta and TaN composition to the interior diffusion ，Gai of low-k interlayer dielectric layer 105 barrier layer 107; Then on ， barrier layer 107, form copper seed layer 109, then in through hole, fill copper metal by physical gas-phase deposition, form copper layer 111.The formation quality of this copper layer is very large to the performance impact of circuit, can directly have influence on a plurality of performance parameters of circuit.
In the forming process of above-mentioned copper layer 111, if the filling quality of copper metal is not good, in the cavity 113 shown in the inner formation Fig. 1 of copper layer 111, to cause formed semiconductor structure electromigration (EM, Electronic Migration) lost efficacy, have a strong impact on the wafer electric performance test (WAT, wafer acceptance test) of the semiconductor device that comprises formed semiconductor structure and the rate of finished products of wafer sort (CP, circuit probing).
In the Chinese patent application that is CN101996924A at publication number, can find more formation methods about semiconductor structure.
Therefore, how in the process that forms semiconductor structure, to avoid producing cavity in copper interconnecting line and just become problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, avoids comprising cavity in formed metal level, improves the electric property of the semiconductor device that forms.
For addressing the above problem, the invention provides a kind of formation method of semiconductor structure, comprising: substrate is provided; At described substrate surface, form dielectric layer; On described dielectric layer surface, form boron nitride layer; Boron nitride layer and dielectric layer described in etching, to exposing substrate, form opening; Boron nitride layer to described opening both sides returns quarter, increases the width of opening top; In described opening, fill full metal level.
Optionally, described dielectric layer is advanced low-k materials or ultra-low dielectric constant material.
Optionally, form boron nitride layer on described dielectric layer before, also comprise: by acetylene plasma, described dielectric layer surface is bombarded, increased the phosphorus content on described dielectric layer surface.
Optionally, the power that forms the radio-frequency power supply of described acetylene plasma is 100～1000W, and pressure is 1～7Torr, and acetylene flow is 150～2000sccm.
Optionally, the boron nitride layer of described opening both sides being returned to the method for carving is dry etching method.
Optionally, the etching gas that described dry etching method adopts is chlorine, and the power of radio-frequency power supply is 100～1000W, and pressure is 1～7Torr, and chlorine flowrate is 50～2000sccm.
Optionally, the material of described metal level is copper.
Optionally, fill full metal level in described opening before, also comprise: bottom and sidewall in described opening form barrier layer; On described barrier layer, form inculating crystal layer.
Optionally, the material on described barrier layer is the composition of tantalum, tantalum nitride or tantalum and tantalum nitride.
Optionally, the material of described inculating crystal layer is copper.
Compared with prior art, technical solution of the present invention has the following advantages:
By forming successively from the bottom to top dielectric layer and boron nitride layer at substrate surface, again boron nitride layer and dielectric layer are carried out to etching formation opening, and pass through back to carve boron nitride layer and increase the width above institute's opening that forms, in filling the process of metal level, avoided sealing in advance the inner cavity that produces of the metal level causing because of opening top, effectively prevent the generation of short circuit and leakage phenomenon, improve the electric property of the semiconductor device that forms.
In possibility; before forming boron nitride layer; by acetylene plasma, dielectric layer surface is bombarded; improve the phosphorus content on dielectric layer surface; because chlorine plasma is lower to the high dielectric layer etching rate of phosphorus content; the dielectric layer that phosphorus content is high can effectively protect that to be positioned at the dielectric layer of its below injury-free, and then improves the electric property of the semiconductor device that forms.
Accompanying drawing explanation
Fig. 1 is the generalized section that existing technique forms copper semiconductor structure;
Fig. 2 is the schematic flow sheet of formation method one execution mode of semiconductor structure of the present invention;
Fig. 3 to Fig. 9 is the generalized section that the formation method of semiconductor structure in one embodiment of the invention forms each stage of semiconductor structure;
Figure 10 to Figure 18 is the generalized section that the formation method of semiconductor structure in another embodiment of the present invention forms each stage of semiconductor structure.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from alternate manner described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, so the present invention is not subject to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the present invention is described in detail in detail, for ease of explanation, described schematic diagram is example, and it should not limit the scope of protection of the invention at this.
Just as described in the background section, along with constantly reducing of semiconductor technology node, the critical size of semiconductor device also constantly reduces, cause the depth-to-width ratio of groove or through hole to become large, when the formation method of existing semiconductor structure is filled metal material with formation metal level in groove or through hole, easily first closed above groove or through hole, and make to form in metal level empty, cause formed semiconductor structure generation electromigration invalidation, the electric property of the impact semiconductor device that forms.
For above-mentioned defect, the invention provides a kind of formation method of semiconductor structure, by forming successively from the bottom to top dielectric layer and boron nitride layer at substrate surface, again boron nitride layer and dielectric layer are carried out to etching formation opening, and pass through back to carve the width that boron nitride layer increases the opening that forms, be beneficial to the filling of metal level in opening, avoid comprising cavity in formed metal level, improve the electric property of the semiconductor device that forms.
With reference to figure 2, show the schematic flow sheet of formation method one execution mode of semiconductor structure of the present invention, comprise the following steps:
Step S1, provides substrate;
Step S2, forms dielectric layer at described substrate surface;
Step S3, forms boron nitride layer on described dielectric layer surface;
Step S4, boron nitride layer and dielectric layer described in etching, to exposing substrate, form opening;
Step S5, returns quarter to the boron nitride layer of described opening both sides, increases the width of opening top;
Step S6 fills full metal level in described opening.
Below in conjunction with accompanying drawing, be elaborated.
Embodiment mono-
The present embodiment provides a kind of formation method of the semiconductor device that comprises through hole, specifically as shown in Fig. 3～Fig. 9:
With reference to figure 3, substrate 301 is provided, on described substrate 301 surfaces, form successively from the bottom to top stop-layer 303 and dielectric layer 305.
In the present embodiment, the material of described substrate 301 is monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or the material that can also comprise other, the present invention does not limit this.
In addition, in described substrate 301, be formed with device architecture (not shown), described device architecture can be the device architecture forming in semiconductor FEOL, such as MOS transistor etc.; In described substrate 301, can also comprise for realizing the metal interconnecting wires of electrical connection.
Described stop-layer 303 diffuses to Semiconductor substrate 301 for preventing the follow-up metallic atom that is formed at through hole, and the method that forms stop-layer 303 is chemical vapour deposition (CVD) (CVD, Chemical Vapor Deposition) technique.Particularly, when the follow-up metal level forming in through hole is copper, the material of described stop-layer 303 is silicon nitride.
It should be noted that, according to the difference of metal level material, the material of stop-layer 303 is also not limited to silicon nitride.
In other embodiments, can also not form described stop-layer 303, on substrate 301 surfaces, directly form dielectric layer 305, the present invention does not limit this.
In the present embodiment, the material of described dielectric layer 305 is advanced low-k materials (low k) or ultra-low dielectric constant material (Ultra low k, ULK), for isolating the metal level of follow-up formation, to reduce the parasitic capacitance between metal level.The method that forms described dielectric layer 305 is chemical vapor deposition method.
Continuation is with reference to figure 3, by acetylene (C
2h
2) plasma bombards described dielectric layer 305 surfaces.
In the present embodiment, the power that forms the radio-frequency power supply of described acetylene plasma is 100～1000W, and pressure is 1～7Torr, and acetylene flow is 150～2000sccm.By acetylene plasma, dielectric layer 305 is bombarded, improve the phosphorus content on dielectric layer 305 surfaces.Because chlorine plasma is less to the etching rate of the higher dielectric layer 305 of phosphorus content; follow-up, to being positioned at boron nitride layer above formed through hole, return while carving, dielectric layer 305 surfaces that phosphorus content is higher can effectively protect that to be positioned at the dielectric layer 305 of its below injury-free.
In other embodiments, can also not comprise by acetylene (C
2h
2) plasma step that described dielectric layer 305 surfaces are bombarded.
With reference to figure 4, on described dielectric layer 305 surfaces, form boron nitride layer 307.
In the present embodiment, the technique that forms described boron nitride (BN) layer 307 is chemical vapor deposition method, but the invention is not restricted to this.
With reference to figure 5, on described boron nitride layer 307 surfaces, form the mask layer 309 that comprises through-hole pattern.
In the present embodiment, described in comprise through-hole pattern the material of mask layer 309 be titanium nitride (TiN), the concrete technology that forms the mask layer 309 that comprises through-hole pattern is as follows:
On described boron nitride layer 307 surfaces, form successively from the bottom to top mask layer and photoresist layer (not shown);
Photoresist layer described in patterning, forms the photoresist layer that comprises through-hole pattern;
The photoresist layer that comprises through-hole pattern of take is mask, and mask layer described in etching forms the mask layer 309 that comprises through-hole pattern;
The photoresist layer that comprises through-hole pattern described in removal.
In the present embodiment, the technique that forms mask layer 309 on described boron nitride layer 307 surfaces is chemical vapor deposition method, but the invention is not restricted to this.
The present invention does not limit the material of photoresist, can be the photoresist of any materials.
With reference to figure 6, the described mask layer that comprises through-hole pattern 309 of take is mask, and boron nitride layer 307 and dielectric layer 305 described in etching, to exposing stop-layer 303, form through hole 321.
In the present embodiment, the technique of boron nitride layer 307 and dielectric layer 305 is dry etching method described in etching, but the present invention is not restricted to this.Follow-up, boron nitride layer 307 above through hole 321 is returned while carving, the stop-layer 303 that is positioned at through hole 321 bottoms can effectively protect substrate 301 injury-free, improves the performance of the semiconductor structure that forms.
With reference to figure 7, the boron nitride layer 307 of described through hole 321 tops is returned to quarter, increase the A/F of boron nitride layer 307.
In the present embodiment, it is dry etching method that the boron nitride layer 307 of described through hole 321 tops is returned to the method for carving.Concrete, the etching gas that described dry etching method adopts is chlorine (Cl
2), the power of radio-frequency power supply is 100～1000W, and pressure is 1～7Torr, and chlorine flowrate is 50～2000sccm.By chlorine plasma, boron nitride layer 307 is returned to quarter, to remove the part boron nitride layer 307 of through hole 321 both sides, increase the A/F of boron nitride layer 307.
With reference to figure 8, remove the stop-layer 303 that is positioned at through hole 321 bottoms, to exposing substrate 301.
In the present embodiment, the technique of removing the stop-layer 303 that is positioned at through hole 321 bottoms is dry etching method, but the invention is not restricted to this.
In other embodiments, when substrate 301 surfaces directly form dielectric layer 305, corresponding, do not need to remove the stop-layer 303 that is positioned at through hole 321 bottoms, directly in the full metal level of the interior filling of described through hole 321 yet.
With reference to figure 8 and Fig. 9, in the full metal level 315 of the interior filling of described through hole 321.
In the present embodiment, the material of described metal level 315 is copper, and the method that expires metal level 315 in the interior filling of described through hole 321 is physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) technique.
In the present embodiment, before the full metal level 315 of the interior filling of described through hole 321, also comprise: remove the mask layer 309 that comprises through-hole pattern, to reduce the depth-to-width ratio of through hole 321, be beneficial to the filling of through hole 321 inner metal layers 315, avoid comprising cavity in formed metal level 315.
In the present embodiment, before the full metal level 315 of the interior filling of described through hole 321, also further comprise: bottom and sidewall in described through hole 321 form barrier layer 311; On described barrier layer 311, form inculating crystal layer 313.
Concrete, the material on described barrier layer 311 is the composition of tantalum (Ta), tantalum nitride (TaN) or tantalum and tantalum nitride; The material of described inculating crystal layer 313 is copper.As described in barrier layer 311 be the composition of tantalum and tantalum nitride, while forming described barrier layer 311, can first carry out tantalum nitride membrane deposition, carry out again metal tantalum deposition, to stop that the metal level 315 of subsequent deposition contacts with dielectric layer 305 the direct of medium layer material, improves the adhesiveness between metal level 315 and dielectric layer 305 simultaneously.Described barrier layer 311 can form by physical gas-phase deposition, also can be undertaken by other method, and the present invention does not limit this.The deposition that described inculating crystal layer 313 is subsequent metal layer 315 provides conductive layer.The concrete formation technique of described barrier layer 311 and inculating crystal layer 313, as those skilled in the art's known technology, does not repeat at this.
In the present embodiment, in the full metal level 315 of the interior filling of described through hole 321, comprise the following steps:
In described through hole 321, fill metal material (not shown), described metal material fills up through hole 321 and covers the boron nitride layer 307 of through hole 321 opening both sides;
Metal material described in planarization, to exposing boron nitride layer 307, forms metal level 315.
Concrete, by metal material described in cmp (CMP, Chemical Mechanical Polishing) technique planarization.
It should be noted that, in the process of metal material described in planarization, also removed and be positioned at boron nitride layer 307Shang barrier layer 311 and inculating crystal layer 313.
The second embodiment
The present embodiment provides a kind of formation method of the semiconductor structure that comprises double damask structure, specifically as shown in Figure 10～Figure 18:
With reference to Figure 10, substrate 201 is provided, on described substrate 201 surfaces, form successively from the bottom to top stop-layer 203 and dielectric layer 205.
In the present embodiment, the material of described substrate 201 is monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or the material that can also comprise other, the present invention does not limit this.
In addition, in described substrate 201, be formed with device architecture (not shown), described device architecture can be the device architecture forming in semiconductor FEOL, such as MOS transistor etc.; In described substrate 201, can also comprise for realizing the plain conductor of electrical connection.
Described stop-layer 203 diffuses to Semiconductor substrate 201 for preventing the follow-up metallic atom that is formed at the second through hole, and the method that forms stop-layer 203 is chemical vapor deposition method.Particularly, when the follow-up metal level depositing in the second through hole is copper, the material of described stop-layer 203 is silicon nitride.
It should be noted that, according to the difference of metal level material, the material of stop-layer 203 is also not limited to silicon nitride.
In other embodiments, described substrate 201 surfaces can also not form stop-layer 203, and directly form dielectric layer 205, and the present invention does not limit this.
In the present embodiment, the material of described dielectric layer 205 is advanced low-k materials or ultra-low dielectric constant material, for isolating the metal level of follow-up formation, to reduce the parasitic capacitance between metal level.The method that forms described dielectric layer 205 is chemical vapor deposition method.
Continuation, with reference to Figure 10, is bombarded described dielectric layer 205 surfaces by acetylene plasma.
In the present embodiment, the power that forms the radio-frequency power supply of described acetylene plasma is 100～1000W, and pressure is 1～7Torr, and acetylene flow is 150～2000sccm.By acetylene plasma, dielectric layer 205 is bombarded, improve the phosphorus content on dielectric layer 205 surfaces.
Because chlorine plasma is less to the etching rate of the higher dielectric layer 205 of phosphorus content; follow-up, to being positioned at boron nitride layer above formed groove, return while carving, dielectric layer 205 surfaces that phosphorus content is higher can effectively protect that to be positioned at the dielectric layer 205 of its below injury-free.
In other embodiments, can also not comprise by acetylene (C
2h
2) plasma step that described dielectric layer 205 surfaces are bombarded.
With reference to Figure 11, on described dielectric layer 205, form boron nitride layer 207.
In the present embodiment, the technique that forms described boron nitride layer 207 is chemical vapor deposition method, but the invention is not restricted to this.
With reference to Figure 12, on described boron nitride layer 207 surfaces, form the mask layer 209 that comprises through-hole pattern.
In the present embodiment, described in comprise through-hole pattern the material of mask layer 209 be titanium nitride, the concrete technology that forms the mask layer 209 that comprises through-hole pattern is as follows:
On described boron nitride layer 207 surfaces, form successively from the bottom to top mask layer and photoresist layer (not shown);
Photoresist layer described in patterning, forms the photoresist layer that comprises through-hole pattern;
The photoresist layer that comprises through-hole pattern of take is mask, and mask layer described in etching forms the mask layer 209 that comprises through-hole pattern;
The photoresist layer that comprises through-hole pattern described in removal.
With reference to Figure 13, the described mask layer that comprises through-hole pattern 209 of take is mask, and boron nitride layer 207 and dielectric layer 205 described in etching, to exposing stop-layer 203, form the first through hole 221.
In the present embodiment, the method for boron nitride layer 207 and dielectric layer 205 is dry etching method described in etching, but the present invention is not restricted to this.
With reference to Figure 14, the mask layer 209 that comprises through-hole pattern described in patterning, forms the mask layer 210 that comprises channel patterns.
In the present embodiment, form the mask layer 210 that comprises channel patterns and comprise the following steps:
On described stop-layer 203 and mask layer 209 surfaces that comprise through-hole pattern, form photoresist layer (not shown);
Photoresist layer described in patterning, forms the photoresist layer that comprises channel patterns;
The described photoresist layer that comprises channel patterns of take is mask, and the mask layer 209 that comprises through-hole pattern described in etching forms the mask layer 210 that comprises channel patterns;
Remove described photoresist layer.
With reference to Figure 15, the mask layer 210 that comprises channel patterns of take is mask, and etching boron nitride layer 207 and part dielectric layer 205, to remainder dielectric layer 205, form groove 223.
With reference to Figure 16, the boron nitride layer 207 of described groove 223 both sides is returned to quarter, to increase the A/F of boron nitride layer 207.
In the present embodiment, it is dry etching method that the boron nitride layer 207 of described groove 223 both sides is returned to the method for carving.Concrete, the etching gas that described dry etching method adopts is chlorine, and the power of radio-frequency power supply is 100～1000W, and pressure is 1～7Torr, and chlorine flowrate is 50～2000sccm.By chlorine plasma, boron nitride layer 207 is returned to quarter, remove the part boron nitride layer 207 of groove 223 tops, increase the A/F of boron nitride layer 207, be beneficial to the filling of subsequent metal layer.
With reference to Figure 17, remove the stop-layer 203 that is positioned at the first through hole 221 bottoms, to exposing substrate 201, form the second through hole 225.The double damask structure that described groove 223 and the second through hole 225 form in semiconductor structure.
In the present embodiment, the method for removing the stop-layer 203 that is positioned at through hole 221 bottoms is dry etching method, but the invention is not restricted to this.
It should be noted that, for not forming the embodiment of stop-layer 203 on substrate 201, do not comprise that above-mentioned removal is positioned at the step of the stop-layer 203 of through hole 221 bottoms.
With reference to Figure 17 and Figure 18, in described groove 223 and the full metal level 219 of the interior filling of the second through hole 225.
In the present embodiment, the material of described metal level 219 is copper, in the method for the full metal level 219 of described groove 223 and the interior filling of the second through hole 225, is physical gas-phase deposition.
In the present embodiment, before described groove 223 and the full metal level 219 of the interior filling of the second through hole 225, also comprise: remove the mask layer 210 that comprises channel patterns, be beneficial to the filling of groove 223 and the second through hole 225 inner metal layers 219, avoid comprising cavity in formed metal level 219.
In the present embodiment, before described groove 223 and the full metal level 219 of the interior filling of the second through hole 225, also further comprise: in the sidewall of described groove 223 and the bottom of described the second through hole 225 and sidewall formation barrier layer 215; On described barrier layer 215, form inculating crystal layer 217.
In the present embodiment, the material of barrier layer 215 and inculating crystal layer 217 and formation technique are identical with inculating crystal layer 313 with embodiment Yi Zhong barrier layer 311 respectively, at this, do not repeat.
In the present embodiment, by first forming through hole, form again the double damask structure in groove (being via-first technique) technique formation semiconductor structure, in other embodiments, also can form the double damask structure in through hole (being trench-first technique) or self-registered technology (being self-aligned technique) formation semiconductor structure by first forming groove, it forms step and does not repeat at this again.
In above-described embodiment, by forming successively from the bottom to top dielectric layer and boron nitride layer at substrate surface, again boron nitride layer and dielectric layer are carried out etching formation through hole or comprise through hole and the double damask structure of groove, and pass through back to carve boron nitride layer increase the A/F of groove in the through hole that forms or double damask structure, be beneficial to through hole or comprise through hole and groove double damask structure in the filling of metal level, avoid comprising cavity in formed metal level, improve the electric property of the semiconductor device that forms.
The method that the present invention forms semiconductor structure is also suitable for forming interconnecting construction.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Substrate is provided;
At described substrate surface, form dielectric layer;
On described dielectric layer surface, form boron nitride layer;
Boron nitride layer and dielectric layer described in etching, to exposing substrate, form opening;
Boron nitride layer to described opening both sides returns quarter, increases the width of opening top;
In described opening, fill full metal level.
2. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, described dielectric layer is advanced low-k materials or ultra-low dielectric constant material.
3. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, before forming boron nitride layer, also comprises on described dielectric layer: by acetylene plasma, described dielectric layer surface is bombarded, increased the phosphorus content on described dielectric layer surface.
4. the formation method of semiconductor structure as claimed in claim 3, is characterized in that, the power that forms the radio-frequency power supply of described acetylene plasma is 100～1000W, and pressure is 1～7Torr, and acetylene flow is 150～2000sccm.
5. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, it is dry etching method that the boron nitride layer of described opening both sides is returned to the method for carving.
6. the formation method of semiconductor structure as claimed in claim 5, is characterized in that, the etching gas that described dry etching method adopts is chlorine, and the power of radio-frequency power supply is 100～1000W, and pressure is 1～7Torr, and chlorine flowrate is 50～2000sccm.
7. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the material of described metal level is copper.
8. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, before filling full metal level, also comprises in described opening: bottom and sidewall in described opening form barrier layer; On described barrier layer, form inculating crystal layer.
9. the formation method of semiconductor structure as claimed in claim 8, is characterized in that, the material on described barrier layer is the composition of tantalum, tantalum nitride or tantalum and tantalum nitride.
10. the formation method of semiconductor structure as claimed in claim 8, is characterized in that, the material of described inculating crystal layer is copper.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633135A (en) * | 2014-11-06 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN109087886A (en) * | 2018-11-05 | 2018-12-25 | 武汉新芯集成电路制造有限公司 | Metal interconnection structure and preparation method thereof |
| CN113380648A (en) * | 2021-05-13 | 2021-09-10 | 中国科学院微电子研究所 | Bonded semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633135A (en) * | 2014-11-06 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN105633135B (en) * | 2014-11-06 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN109087886A (en) * | 2018-11-05 | 2018-12-25 | 武汉新芯集成电路制造有限公司 | Metal interconnection structure and preparation method thereof |
| CN109087886B (en) * | 2018-11-05 | 2019-10-25 | 武汉新芯集成电路制造有限公司 | Metal interconnection structure and preparation method thereof |
| CN113380648A (en) * | 2021-05-13 | 2021-09-10 | 中国科学院微电子研究所 | Bonded semiconductor device and method for manufacturing the same |
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| Publication number | Publication date |
|---|---|
| CN103515292B (en) | 2015-10-14 |
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