CN103515231A - FinFET manufacturing method - Google Patents
FinFET manufacturing method Download PDFInfo
- Publication number
- CN103515231A CN103515231A CN201210206310.XA CN201210206310A CN103515231A CN 103515231 A CN103515231 A CN 103515231A CN 201210206310 A CN201210206310 A CN 201210206310A CN 103515231 A CN103515231 A CN 103515231A
- Authority
- CN
- China
- Prior art keywords
- fin
- semiconductor substrate
- finfet
- manufacture method
- finfet manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 61
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 19
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 10
- 108091006146 Channels Proteins 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 30
- 238000002513 implantation Methods 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 43
- 230000005669 field effect Effects 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 229940090044 injection Drugs 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- -1 preferred Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a FinFET manufacturing method. On the premise of not increasing the device size, trenches are etched on a dielectric layer of a semiconductor substrate, the trenches are filled with stress semiconductor material of which the lattice is different from that of the semiconductor substrate, the dielectric layer is removed, and a fin vertically arranged on the substrate is formed through self alignment. The fin mismatches the lattice of the semiconductor substrate below the fin, which enables stress to be produced in a channel region of the fin, improves the channel carrier mobility and improves the driving current of a FinFET device. Furthermore, carbon and/or nitrogen ion implantation is performed on the fin to reduce the defects of ion implantation during source/drain region and channel region doping carried out on the fin, improve the interface quality of the fin channel region and improve the performance of the FinFET device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of FinFET manufacture method.
Background technology
MOSFET(metal oxide semiconductor field effect is answered transistor) be the main member of most of semiconductor device, when channel length is less than 100nm, in traditional MOSFET, because the semi-conducting material of the Semiconductor substrate around active area makes between source electrode and drain region interactive, drain electrode is also shortened with the distance of source electrode thereupon, produce short-channel effect, so the control ability variation of grid to raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove is also increasing, so just makes sub-threshold values electric leakage (Subthrehhold leakage) phenomenon more easily occur.
Fin formula field-effect transistor (Fin Field effect transistor, FinFET) be that a kind of new metal oxide semiconductor field effect is answered transistor, its structure forms conventionally on silicon-on-insulator (SOI) substrate, comprise that narrow and isolated silicon strip (is the channel structure of vertical-type, also claim fin), fin both sides are with grid structure.FinFET structure makes device less, and performance is higher.
As shown in Figure 1, a kind of structure of FinFET device in prior art, comprise substrate (not shown) and stand on the fin on substrate, described fin generally forms by the silicon epitaxial layers in etched substrate, described fin generally includes the fin channel district 13 between 11He drain region, 12, source region, 11, drain region, source region 12, and the structure of described FinFET device also comprises the grid structure 14 that is centered around 13 both sides, fin channel district and top.Wherein, as thin as a wafer, and its three faces that contact with grid structure 14 are controlled to described fin channel district 13 thickness, are subject to the control of grid structure 14, can construct and entirely exhaust structure, thoroughly cut off the conductive path of raceway groove.
In prior art, a kind of method of the FinFET of raising device drive current is to introduce stress in the FinFET device surface deposition stressor layers Yi Xiang fin channel district 13 shown in Fig. 1, improve the carrier mobility in fin channel district 13, but this method increases the size of the FinFET device of manufacture, can not meet the manufacture requirement of the FinFET device below 22nm technology node.
Summary of the invention
The object of the present invention is to provide a kind of FinFET manufacture method, not increasing under the prerequisite of device size, can increase carrier mobility, improve the drive current of FinFET device.
For addressing the above problem, the present invention proposes a kind of FinFET manufacture method, comprises the following steps:
Provide Semiconductor substrate, metallization medium layer in described Semiconductor substrate;
Described in etching, dielectric layer, to described semiconductor substrate surface, forms at least one groove;
In described groove, fill lattice and be different from the stressed semiconductor material of described Semiconductor substrate;
Remove described dielectric layer;
Formation stands on the fin in described Semiconductor substrate, and described fin comprises source region, drain region and the fin channel district between source region and drain region;
Formation is around the gate stack structure of both sides, described fin channel district and top.
Further, described Semiconductor substrate is silicon-Germanium substrate, and the stressed semiconductor material of filling in described groove is silicon.
Further, described Semiconductor substrate is silicon substrate, and the stressed semiconductor material of filling in described groove is SiGe.
Further, adopt epitaxially grown mode in described groove, to fill stressed semiconductor material.
Further, after formation stands on the fin in described Semiconductor substrate, described fin channel district is carried out to N-type or the injection of P type channel ion.
Further, the dosage that described N-type or P type channel ion inject is 1.0E18/cm
2~ 1.0E20/cm
2.
Further, formation is carried out carbon and/or nitrogen Implantation to described fin after standing on the fin in described Semiconductor substrate.
Further, the energy of described carbon and/or nitrogen Implantation is 0.3KeV ~ 1.5KeV, and dosage is 1E19/cm
2~ 1E21/cm
2.
Further, form around before the gate stack structure of both sides, described fin channel district and top, also comprise:
In described Semiconductor substrate and described fin surface deposition stressor layers;
After annealing, remove described stressor layers.
Further, the deposit thickness of described stressor layers is 20nm ~ 50nm, and stress is 0.7GPa ~ 2GPa.
Further, described dielectric layer is silica or silicon nitride.
Further, described gate stack structure comprises gate dielectric layer and is formed at the grid layer of described gate dielectric layer periphery.
Further, all grooves are completely independent.
Further, each groove comprises source range, drain region section and the channel section between described source range and drain region section, and it is as a whole that fluted source range connects into mutually, and drain region section connects into as a whole mutually, and channel section is separate.
Compared with prior art, FinFET manufacture method provided by the invention, do not increasing under the prerequisite of device size, by the dielectric layer in Semiconductor substrate, etch groove, the stressed semiconductor material that adopts again lattice to be different from described Semiconductor substrate is filled described groove, removal medium layer is that autoregistration has formed the fin standing on substrate, the lattice mismatch of the Semiconductor substrate of fin and its below, make to produce stress in the channel region of fin, improve channel carrier mobility, and then improved the drive current of FinFET device; Further, described fin is carried out to carbon and/or nitrogen Implantation, the Implantation defect while carrying out Yuan/ drain region and channel region doping to reduce is improved the interface quality in fin channel district simultaneously, improves FinFET device performance; Further, before forming gate stack structure, first on fin, form a stressor layers, the mechanical stress of stressor layers is transferred to fin channel district, then remove described stressor layers, the drive current that improves FinFET device, then removes stressor layers, controls FinFET device size.
Accompanying drawing explanation
Fig. 1 is the perspective view of a kind of FinFET of prior art;
Fig. 2 is the FinFET manufacture method flow chart of the specific embodiment of the invention;
Fig. 3 A ~ 3F is the device architecture schematic diagram of the FinFET manufacturing process of the specific embodiment of the invention.
Embodiment
FinFET manufacture method provided by the invention, the mode that forms fin from epitaxial loayer on direct etching substrate in prior art is different, key is to form the fin with substrate lattice mismatch by self-aligned manner, in fin channel district, introduce stress, to improve carrier mobility, and then improve FinFET driveability.
FinFET manufacture method the present invention being proposed below in conjunction with the drawings and specific embodiments is described in further detail.
As shown in Figure 2, the invention provides a kind of FinFET manufacture method, comprise the following steps:
S21, provides Semiconductor substrate, metallization medium layer in described Semiconductor substrate;
S22, dielectric layer, to described semiconductor substrate surface, forms at least one groove described in etching;
S23 fills the stressed semiconductor material that lattice is different from described Semiconductor substrate in described groove;
S24, removes described dielectric layer;
S25, forms and stands on the fin in described Semiconductor substrate, and described fin comprises source region, drain region and the fin channel district between source region and drain region;
S26, forms the gate stack structure around both sides, described fin channel district and top.
Please refer to Fig. 3 A, in step S21, the Semiconductor substrate 300 providing can be silicon-Germanium substrate, can be also silicon substrate, preferred, and Semiconductor substrate 300 is carried out to N-type or P type well region Implantation, forms N-type well region or P type well region; Then, in Semiconductor substrate 300, by techniques such as CVD, form dielectric layer 301, the material of this dielectric layer 301 can be the single layer structure of silicon nitride or silica, can be also the composite construction of silicon nitride and silica.
Please continue to refer to Fig. 3 A, in step S22, can first on dielectric layer 301, form photoresist layer, then adopt the mask plate of manufacturing FinFET fin to expose to photoresistance, without the new mask plate of extra manufacture, then take this photoresistance as mask etching dielectric layer 301 is to exposing described Semiconductor substrate 300 surfaces, form one or more groove 301a, this groove 301a forms FinFET fin for follow-up autoregistration, and this groove 301a comprises source range, drain region section and the channel section (not shown) between source range and drain region section.The all grooves that form are independent (not shown) completely, for the manufacture of separate FinFET; The all grooves that form can be also common source section and drain region section, fluted source range connects into as a wholely mutually, and drain region section connects into as a whole mutually, and channel section is separate, for the manufacture of many raceway grooves, FinFET(is not shown, can be with reference to figure 1).
Please refer to Fig. 3 B, in step S23, can adopt the modes such as epitaxial growth or CVD, in described groove 301a, fill stressed semiconductor material 302.The lattice of stressed semiconductor material 302 is different from Semiconductor substrate 300, to cause lattice mismatch, in the fin channel district of the FinFET of follow-up formation, introduces stress, improves carrier mobility; For example, when described Semiconductor substrate 300 is silicon-Germanium substrate, the stressed semiconductor material 302 of filling in described groove 301a is silicon; When described Semiconductor substrate 300 is silicon substrate, the stressed semiconductor material 302 of filling in described groove 301a is SiGe.
Please refer to Fig. 3 C, in step S24, removal medium layer 301, and then expose the stressed semiconductor material 302 of filling.
Please continue to refer to Fig. 3 C, in step S25, in the semi-conducting material of filling, inject ion, form fin, described fin comprises source region, drain region and the fin channel district (not shown) between source region and drain region, the mode of this formation fin is a kind of self-aligned manner, the lattice of the stressed semiconductor material 302 of fin is different from Semiconductor substrate 300, can cause lattice mismatch, in the fin channel district of the FinFET forming, introduce stress, improve carrier mobility, thereby can improve the drive current of the FinFET device making.
Further, to the fin channel district of described fin, carry out N-type or P type channel ion and inject, to form N fin channel or P fin channel, carry out the dosage that N-type or P type channel ion inject and be preferably 1.0E18/cm
2~ 1.0E20/cm
2.
Please refer to Fig. 3 D, in the present embodiment, after step S25, also described fin is carried out carbon and/or the nitrogen Implantation (as shown by arrows) of multi-angle, carry out short annealing or laser annealing, so that the ion injecting diffusion evenly, the energy of Implantation is preferably 0.3KeV ~ 1.5KeV, and dosage is preferably 1E19/cm
2~ 1E21/cm
2.Carbon and/or nitrogen Implantation, the Implantation defect in the time of can reducing on the one hand Yuan/ drain region that fin is carried out and channel region doping, suppresses to inject the diffusion that N-type or P type channel ion and follow-up heavy-doped source/drain ion are injected; Can also improve the interface quality in fin channel district at the interface formation protective layer 302a in fin channel district on the other hand, reduce leakage current, thereby improve FinFET device performance.
Please refer to Fig. 3 E, in the present embodiment, in order further to increase the stress in fin channel district, after described fin being carried out to the carbon and/or nitrogen Implantation of multi-angle, also in described Semiconductor substrate 300 and described fin surface deposition stressor layers 303, the deposit thickness of described stressor layers 303 is 20nm ~ 50nm, and stress is 0.7GPa ~ 2GPa; Then, carry out annealing process, the mechanical stress of stressor layers 303 is transferred to fin channel district, improve the drive current of FinFET device; Then, please refer to Fig. 3 F, remove described stressor layers 303.
Please continue to refer to Fig. 3 F, after step S26, can form successively around the gate stack structure of both sides, described fin channel district and top by methods such as chemical vapour deposition (CVD)s, this gate stack structure comprises gate dielectric layer 304 and peripheral grid layer 305 thereof.Wherein, grid layer 305 can be polysilicon, and gate dielectric layer 304 can be silica or silicon oxynitride; Grid layer 305 can be also metal material, and gate dielectric layer 304 can be high K dielectric material.
Please continue to refer to Fig. 3 F, after forming gate stack structure, can also carry out the following step:
Take described gate stack structure as mask, light dope (LDD) Implantation is carried out in described source region and drain region;
Sidewall at described gate stack structure forms side wall (not shown);
Take described gate stack structure and side wall as mask, heavy-doped source/drain electrode (S/D) Implantation is carried out in described source region and drain region.
In sum, FinFET manufacture method provided by the invention, do not increasing under the prerequisite of device size, by the dielectric layer in Semiconductor substrate, etch groove, the stressed semiconductor material that adopts again lattice to be different from described Semiconductor substrate is filled described groove, removal medium layer is that autoregistration has formed the fin standing on substrate, the lattice mismatch of the Semiconductor substrate of fin and its below, make to produce stress in the channel region of fin, improve channel carrier mobility, and then improved the drive current of FinFET device; Further, described fin is carried out to carbon and/or nitrogen Implantation, the Implantation defect while carrying out Yuan/ drain region and channel region doping to reduce is improved the interface quality in fin channel district simultaneously, improves FinFET device performance; Further, before forming gate stack structure, first on fin, form a stressor layers, the mechanical stress of stressor layers is transferred to fin channel district, then remove described stressor layers, the drive current that improves FinFET device, then removes stressor layers, controls FinFET device size.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (15)
1. a FinFET manufacture method, is characterized in that, comprising:
Provide Semiconductor substrate, metallization medium layer in described Semiconductor substrate;
Described in etching, dielectric layer, to described semiconductor substrate surface, forms at least one groove;
In described groove, fill lattice and be different from the stressed semiconductor material of described Semiconductor substrate;
Remove described dielectric layer;
Formation stands on the fin in described Semiconductor substrate, and described fin comprises source region, drain region and the fin channel district between source region and drain region;
Formation is around the gate stack structure of both sides, described fin channel district and top.
2. FinFET manufacture method as claimed in claim 1, is characterized in that, described Semiconductor substrate is silicon-Germanium substrate, and the stressed semiconductor material of filling in described groove is silicon.
3. FinFET manufacture method as claimed in claim 1, is characterized in that, described Semiconductor substrate is silicon substrate, and the stressed semiconductor material of filling in described groove is SiGe.
4. FinFET manufacture method as claimed in claim 1, is characterized in that, adopts epitaxially grown mode in described groove, to fill stressed semiconductor material.
5. FinFET manufacture method as claimed in claim 1, is characterized in that, the step that formation stands on the fin in described Semiconductor substrate comprises: described fin channel district is carried out to N-type or the injection of P type channel ion.
6. FinFET manufacture method as claimed in claim 5, is characterized in that, the dosage that described N-type or P type channel ion inject is 1.0E18/cm
2~ 1.0E20/cm
2.
7. FinFET manufacture method as claimed in claim 1, is characterized in that, the step that formation stands on the fin in described Semiconductor substrate also comprises: described fin is carried out to carbon and/or nitrogen Implantation.
8. FinFET manufacture method as claimed in claim 7, is characterized in that, the energy of described carbon and/or nitrogen Implantation is 0.3KeV ~ 1.5KeV, and dosage is 1.0E19/cm
2~ 1.0E21/cm
2.
9. FinFET manufacture method as claimed in claim 1, is characterized in that, forms around before the gate stack structure of both sides, described fin channel district and top, also comprises:
In described Semiconductor substrate and described fin surface deposition stressor layers;
Remove described stressor layers.
10. FinFET manufacture method as claimed in claim 9, is characterized in that, the thickness of described stressor layers is 20nm ~ 50nm, and stress is 0.7GPa ~ 2GPa.
11. FinFET manufacture methods as claimed in claim 1, is characterized in that, described dielectric layer is silica or silicon nitride.
12. FinFET manufacture methods as claimed in claim 1, is characterized in that, described gate stack structure comprises gate dielectric layer and is formed at the grid layer of gate dielectric layer periphery.
13. FinFET manufacture methods as claimed in claim 1, is characterized in that, all grooves are completely independent.
14. FinFET manufacture methods as claimed in claim 1, is characterized in that, each groove comprises source range, drain region section and the channel section between described source range and drain region section.
15. FinFET manufacture methods as claimed in claim 14, is characterized in that, it is as a whole that fluted source range connects into mutually, and drain region section connects into as a whole mutually, and channel section is separate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210206310.XA CN103515231B (en) | 2012-06-20 | 2012-06-20 | FinFET manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210206310.XA CN103515231B (en) | 2012-06-20 | 2012-06-20 | FinFET manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103515231A true CN103515231A (en) | 2014-01-15 |
| CN103515231B CN103515231B (en) | 2016-12-07 |
Family
ID=49897756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210206310.XA Active CN103515231B (en) | 2012-06-20 | 2012-06-20 | FinFET manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103515231B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097536A (en) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN110323136A (en) * | 2018-03-29 | 2019-10-11 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET manufacturing process |
| CN110970300A (en) * | 2018-09-29 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Stacked gate-all-around fin field effect transistor and forming method thereof |
| CN113363145A (en) * | 2020-03-05 | 2021-09-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| WO2023044924A1 (en) * | 2021-09-27 | 2023-03-30 | 西门子股份公司 | Method and apparatus for determining geometric structure of radiator fin, and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060175667A1 (en) * | 2005-02-04 | 2006-08-10 | Kabushiki Kaisha Toshiba | MOSFET-type semiconductor device, and method of manufacturing the same |
| US20070166891A1 (en) * | 2005-12-29 | 2007-07-19 | Jeong-Ho Park | Method of fabricating a fin field effect transistor in a semiconductor device |
| US20070249130A1 (en) * | 2006-04-21 | 2007-10-25 | Anderson Brent A | Finfet/trigate stress-memorization method |
| JP2009200471A (en) * | 2007-12-19 | 2009-09-03 | Interuniv Micro Electronica Centrum Vzw | Method of manufacturing multi-gate semiconductor device with improved carrier mobility |
| CN102347350A (en) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
-
2012
- 2012-06-20 CN CN201210206310.XA patent/CN103515231B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060175667A1 (en) * | 2005-02-04 | 2006-08-10 | Kabushiki Kaisha Toshiba | MOSFET-type semiconductor device, and method of manufacturing the same |
| US20070166891A1 (en) * | 2005-12-29 | 2007-07-19 | Jeong-Ho Park | Method of fabricating a fin field effect transistor in a semiconductor device |
| US20070249130A1 (en) * | 2006-04-21 | 2007-10-25 | Anderson Brent A | Finfet/trigate stress-memorization method |
| JP2009200471A (en) * | 2007-12-19 | 2009-09-03 | Interuniv Micro Electronica Centrum Vzw | Method of manufacturing multi-gate semiconductor device with improved carrier mobility |
| CN102347350A (en) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097536A (en) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN110323136A (en) * | 2018-03-29 | 2019-10-11 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET manufacturing process |
| CN110323136B (en) * | 2018-03-29 | 2023-06-13 | 中芯国际集成电路制造(上海)有限公司 | FinFET manufacturing process |
| CN110970300A (en) * | 2018-09-29 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Stacked gate-all-around fin field effect transistor and forming method thereof |
| CN110970300B (en) * | 2018-09-29 | 2023-09-22 | 中芯国际集成电路制造(上海)有限公司 | Stacked gate-all-around fin field effect transistor and forming method thereof |
| CN113363145A (en) * | 2020-03-05 | 2021-09-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN113363145B (en) * | 2020-03-05 | 2023-12-22 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| WO2023044924A1 (en) * | 2021-09-27 | 2023-03-30 | 西门子股份公司 | Method and apparatus for determining geometric structure of radiator fin, and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103515231B (en) | 2016-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8853008B1 (en) | Counter-doped low-power FinFET | |
| US8062938B2 (en) | Semiconductor device and method of fabricating the same | |
| CN102339859B (en) | Metal-oxide-semiconductor (MOS) transistor and formation method thereof | |
| JP2009532875A (en) | Method of manufacturing a semiconductor using an etching stop layer to optimize the formation of a source / drain stressor | |
| US9679962B2 (en) | FinFET and method of manufacturing the same | |
| US20140097402A1 (en) | Semiconductor structure and method for forming the same | |
| US8957481B2 (en) | Semiconductor structure and method for manufacturing the same | |
| CN104517847B (en) | Nodeless mesh body pipe and forming method thereof | |
| US8828812B2 (en) | Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof | |
| CN104282540A (en) | Transistor and method for forming transistor | |
| CN103594344A (en) | Method for manufacturing multi-height Fin EFT (field effect transistor) devices | |
| CN103035712A (en) | Semiconductor component and manufacture method thereof | |
| CN103515231A (en) | FinFET manufacturing method | |
| CN109148578A (en) | Semiconductor structure and forming method thereof | |
| CN103295899B (en) | FinFET manufacture method | |
| TW200605357A (en) | Thin film transistor structure and method of fabricating the same | |
| US20230014586A1 (en) | Horizontal gaa nano-wire and nano-slab transistors | |
| US20120280326A1 (en) | Method for Manufacturing a Hybrid MOSFET Device and Hybrid MOSFET Obtainable Thereby | |
| CN103123899B (en) | FinFET manufacture method | |
| CN103456638B (en) | Autoregistration GaAs FinFET structure and manufacture method thereof | |
| CN103383961A (en) | Finfet structure and manufacturing method thereof | |
| CN104253090A (en) | Method for forming CMOS (Complementary Metal-Oxide-Semiconductor) transistor | |
| JP5172893B2 (en) | Method for manufacturing transistor | |
| CN106856172B (en) | Method for forming fin field effect transistor | |
| KR20080081550A (en) | Mosfet device and method of mamufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |