CN103493184B - Semiconductor wafer and manufacture method thereof - Google Patents

Semiconductor wafer and manufacture method thereof Download PDF

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CN103493184B
CN103493184B CN201280020389.5A CN201280020389A CN103493184B CN 103493184 B CN103493184 B CN 103493184B CN 201280020389 A CN201280020389 A CN 201280020389A CN 103493184 B CN103493184 B CN 103493184B
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semiconductor wafer
turned
periphery
down edge
shape
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CN103493184A (en
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佐藤三千登
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Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/34—Accessories
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention provides a kind of semiconductor wafer, it is formed with turned-down edge when grinding in periphery, it is characterized in that, between the center of aforesaid semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of aforesaid semiconductor wafer is below 100nm, and the center of aforesaid semiconductor wafer is the shape protruded, the periphery turned-down edge amount of aforesaid semiconductor wafer is below 100nm, and, turned-down edge starting position, aforementioned periphery, it is the position from the outer circumference end of aforementioned semiconductor wafer toward more than central side 20mm, or than the peripheral part as the aforesaid semiconductor wafer of the determination object of ESFQR closer to the position of central side.The object of the invention is to provide a kind of semiconductor wafer and manufacture method thereof thus, this semiconductor wafer, under identical processing conditions, can meet the flatness index of SFQR, ESFQR, ZDD, ROA, GBIR, SBIR etc. more than two kinds simultaneously.

Description

Semiconductor wafer and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor wafer and manufacture method thereof, this semiconductor wafer meets the flatness parameter of more than two kinds.
Background technology
In recent years, along with miniaturization development, also require until semiconductor wafer periphery is all smooth wafer (wafer) shape, except the GBIR (GlobalBacksurface-referencedIdealplane/Range so far as flatness evaluation index, the overall back side-benchmark ideal plane/scope), SFQR (SiteFrontsurfacereferencedleastsQuares/Range, front, position benchmark least square/scope), SBIR (SiteBacksurface-referencedIdealplane/Range, the back side, position-benchmark ideal plane/scope) etc., also following new index is brought into use: the ROA (RollOffAmount of the flatness of assessment semiconductor wafer peripheral part, turned-down edge amount, also referred to as edge turned-down edge amount (EdgeRollOffAmount)), ESFQR (EdgeSiteFrontsurfacereferencedleastsQuares/Range, front, edge benchmark least square/scope), the ZDD (Z-HeightDoubleDifferentiation, the dual differential of Z height) of assessment Curvature varying.
Semiconductor wafer peripheral part after grinding, its stock removal can increase because contacting with abrasive cloth, and with regard to the shape after grinding, periphery turned-down edge can occur.Usually, ROA and ESFQR uses the data till the point of distance semiconductor wafer outer circumference end 1mm to calculate, SFQR and SBIR uses the data till the point of distance semiconductor wafer outer circumference end 2mm to calculate.Therefore, ROA and ESFQR, compared to SFQR and SBIR, can be subject to the impact of periphery turned-down edge more consumingly.Again, the thickness of semiconductor wafer, significantly changing between wafer outer circumference end 0.5 ~ 1mm, in the future, if the periphery exclusionary zone of ROA and ESFQR is less than 1mm, will be subject to the impact of periphery turned-down edge more consumingly.Below, SEMI (SemiconductorEquipmentandMaterialsInternational, the semiconductor equipment material industry association) flatness index shown in specification is described individually.
GBIR is the overall flat degree index of backside reference, for assessment of the flatness of the whole wafer surface of delimiting about eliminating circumference.GBIR is defined as: during with the back side of semiconductor wafer for datum level, and the surface of semiconductor wafer is relative to the scope of maximum, the minimum thickness deviation of this datum level.
SFQR is the position flatness index of reference surface, assesses individually each position.SFQR is defined as: the unit first determining arbitrary dimension (such as 26mm × 8mm) on a surface of a semiconductor wafer, when being datum level for this cell surface according to the face that least square method (leastsquaremethod) is obtained, the scope of the forward counted from this datum level and the deviation of negative sense.Again, the value of SFQR maximum (SFQRmax) is the maximum of the SFQR represented in each position on provided wafer.
SBIR is the position flatness index of backside reference.SBIR be when with the back side of semiconductor wafer for datum level time, the unit of the arbitrary dimension (such as 26mm × 8mm) on semiconductor wafer surface is relative to the thickness deviation of this datum level, and SBIR maximum (SBIRmax) is the maximum of the SBIR represented in each position.SFQR and SBIR is the assessment of the flatness of the discrete cell on regarding wafer surface, and carries out for the unit of the size roughly the same with the region of made semiconductor device.
The definition of ROA is described with reference to Figure 13.In Figure 13, transverse axis represents the distance counted from the outer circumference end of semiconductor wafer, and the longitudinal axis is the displacement of the shape representing wafer surface.In general, so-called ROA is under the state that back surface of semiconductor wafer is corrected to plane, after revising the slope (gradient) of semiconductor wafer surface, with the smooth region (r in Figure 13 apart from semiconductor wafer outer circumference end 3 ~ 6mm 1~ r 2between) be datum level, represent apart from outer circumference end 0.5mm and 1mm (in fig. 13, with r 0represent the distance counted from semiconductor wafer outer circumference end) the change d of the shape displacement counted from said reference face be used as turned-down edge amount.Compare r 0closer to the side of outer circumference end, also referred to as periphery exclusionary zone (also referred to as periphery exclusionary zone, referring to the distance counted from wafer outer circumference end at the position outside the scope of application of flatness specification).
The definition of ZDD is described with reference to Figure 14.In fig. 14, transverse axis represents the distance counted from the outer circumference end of semiconductor wafer, and the longitudinal axis is the displacement of the shape representing wafer surface.In general, so-called ZDD is the meaning of semiconductor wafer relative to the second-order differential of the surface displacement amount of semiconductor wafer radius.When ZDD be on the occasion of time, presentation surface toward tilt direction displacement (displacement), on the contrary, when ZDD is negative value, presentation surface is toward the displacement of turned-down edge direction.
Again, ESFQR is the above-mentioned SFQR at edge (peripheral part), represents the flatness index of the flatness of peripheral part.The deciding means of the unit of ESFQR is described with reference to Figure 15.Figure 15 (a) is the top plane view representing semiconductor wafer, illustrates the position that its outer peripheral portion is slit into 72 rectangular areas (unit).Figure 15 (b) is the enlarged drawing of one of them representing this rectangular area, and as shown in Figure 15 (b), rectangular area is by the straight line L of 35mm extended from outer circumference end toward diametric(al) 2, and the arc L suitable with the circumferencial direction 5 ° of semiconductor wafer peripheral part 1surrounded, do not comprised the L extending 1mm from outer circumference end toward diametric(al) 3region.Herein, so-called ESFQR, refers to the SFQR value (in region least square plane to the forward and the scope of the deviation of negative sense) of this rectangular area (unit).The situation of ESFQR is with L 3shown side, periphery is as periphery exclusionary zone.
Prior art document
Patent documentation
Patent documentation 1: Japanese Unexamined Patent Publication 8-257893 publication
Summary of the invention
[inventing problem to be solved]
Aforementioned periphery turned-down edge, is because grinding pressure increases because of abrasive cloth distortion, makes the position, periphery of wafer be subject to overmastication and not form plane, thus have the position of circularity, curvature.The object of the known impact in order to reduce abrasive cloth as above distortion, and use one to have the grinding head (patent documentation 1) of retainer (retainer) mechanism.But, in order to reduce the scar of wafer surface, is use soft abrasive cloth at present, but is difficult to suppress abrasive cloth distortion, and in principle, the improvement of periphery turned-down edge has its limit.
On the other hand, there are the flatness specification of reference surface (Frontside) and the flatness specification of backside reference (Backside), and are difficult under identical manufacturing condition, meet two kinds of different indexs of this datum level simultaneously.Therefore, need the program change that manufacturing condition changes, and have the problem that therefore productivity can reduce.
Further, even if identical reference surface, the value of ESFQR etc. also can change, so also there is the problem that therefore productive rate can reduce because periphery exclusionary zone is different.In order to solve problem as above, and have employed following gimmick, such as: in order to improve the object of ESFQR, and grinding in the mode making peripheral part tilt a little, reducing the maximum displacement counted from the least square plane (leastsquareplane) in outer region.But so also cannot improve the turned-down edge of the outermost perimembranous of wafer, and can produce the point of inflexion along with change of shape, this change of shape is from according to carrying out grinding formed shape in the mode making it tilt, and is changed to turned-down edge.Result, although the variable quantity being applicable to the thickness improving wafer larger to EE (EdgeExclusion, periphery exclusionary zone) value of ROA and ESFQR till 1mm, but be not suitable for improving SFQR and ZDD that EE belongs to the 2mm of main flow, and be difficult to the flatness index simultaneously meeting more than two kinds.
The present invention grinds to solve the problem to create, object is to provide a kind of semiconductor wafer and manufacture method thereof, this semiconductor wafer, under identical processing conditions, can meet the flatness index of SFQR, ESFQR, ZDD, ROA, GBIR, SBIR etc. more than two kinds simultaneously.
[solving the method for problem]
In order to solve the problem, the invention provides a kind of semiconductor wafer, it is formed with turned-down edge when grinding in periphery, it is characterized in that:
Between the center of aforesaid semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of aforesaid semiconductor wafer is below 100nm, and the center of aforesaid semiconductor wafer is the shape protruded,
The periphery turned-down edge amount of aforesaid semiconductor wafer is below 100nm, and,
Turned-down edge starting position, aforementioned periphery, be position from the outer circumference end of aforementioned semiconductor wafer toward more than central side 20mm or than the peripheral part as the aforesaid semiconductor wafer of the determination object of ESFQR closer to the position of central side.
If the shape of semiconductor wafer as above, in the flatness index of different SFQR, ESFQR, the ROA etc. more than two kinds of periphery exclusionary zone, just can the deviation counted from datum level be reduced to minimum simultaneously, and according to by the center of semiconductor wafer be protrude shape (hereinafter also referred to center protrude shape), with periphery turned-down edge combination of shapes, the Curvature varying that also can simultaneously suppress peripheral part to produce.Further, be made into the semiconductor wafer of shape as above, not only reference surface, also can meet the evaluation index of the flatness index (GBIR, SBIR etc.) of backside reference and the curvature as ZDD so simultaneously.Thereby, it is possible to correspond to all customer requirements under identical grinding condition, and multiple customer requirement can be met.Again, because correspondence can be carried out under identical processing conditions, so productivity and the productive rate of semiconductor wafer can be improved.
Again, preferred aforementioned periphery turned-down edge amount is below 70nm.
Thereby, it is possible to be made into a kind of semiconductor wafer, it improves the flatness indexes such as SFQR, ESFQR, ZDD, ROA, GBIR, SBIR more.
And, the invention provides a kind of manufacture method of semiconductor wafer, monocrystal rod microsection manufacture is being become semiconductor wafer by it, and this semiconductor wafer is chamfered, and after making its planarization, comprise the grinding step being carried out by aforesaid semiconductor wafer grinding, the feature of the manufacture method of described semiconductor wafer is:
In aforementioned grinding step, to make between the center of aforesaid semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of aforesaid semiconductor wafer becomes below 100nm, and the center of aforesaid semiconductor wafer becomes the mode of the shape of protrusion, aforesaid semiconductor wafer is carried out two-sided lapping
Then, in the mode making the periphery turned-down edge amount of aforesaid semiconductor wafer become below 100nm, and, to make turned-down edge starting position, aforementioned periphery, become position from the outer circumference end of aforementioned semiconductor wafer toward more than central side 20mm or than the peripheral part as the aforesaid semiconductor wafer of the determination object of ESFQR closer to the mode of the position of central side, the one side of aforesaid semiconductor wafer is carried out cmp.
According to two-sided lapping semiconductor wafer as described above, just can easily make a kind of semiconductor wafer, between its center at semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of semiconductor wafer is below 100nm, and the center of semiconductor wafer becomes the shape of protrusion.And, the one side of semiconductor wafer is carried out cmp, just can easily make a kind of semiconductor wafer, its periphery turned-down edge amount becomes below 100nm, and, turned-down edge starting position, periphery, become position from the outer circumference end of semiconductor wafer toward more than central side 20mm or than the peripheral part as the semiconductor wafer of the determination object of ESFQR closer to the position of central side.
Again, in aforementioned grinding step, preferably in the mode making periphery turned-down edge amount become below 70nm, semiconductor wafer is ground.
Thereby, it is possible to manufacture a kind of semiconductor wafer, it improves the flatness indexes such as SFQR, ESFQR, ZDD, ROA, GBIR, SBIR more.
And, carrying out in afore mentioned chemical mechanical lapping, preferably use A Si card C(Asker-C) hardness (use the spring hardness tester C type according to JISK6301 and record hardness) is abrasive cloth or the shore D(Shore-D of the nonwoven fabrics system of more than 60) hardness (use the rebounding type hardness tester D type of foundation JISZ2246 and record hardness) be more than 55 polyurethane (polyurethane) abrasive cloth that is, aforesaid semiconductor wafer is ground.
The turned-down edge amount of cmp, although also can change because of grinding condition, but because the degree relevant to the deflection of abrasive cloth is large, as long as so the abrasive cloth selecting hardness as above harder, the turned-down edge amount of expectation just can be obtained according to adjustment grinding condition.Again, can be more prone to make a kind of semiconductor wafer, its periphery turned-down edge amount becomes below 100nm, and, turned-down edge starting position, periphery, become position from the outer circumference end of semiconductor wafer toward more than central side 20mm or than the peripheral part as the semiconductor wafer of the determination object of ESFQR closer to the position of central side.
[effect of invention]
If the shape of semiconductor wafer of the present invention, in the flatness index of different SFQR, ESFQR, the ROA etc. more than two kinds of periphery exclusionary zone, just can the deviation counted from datum level be reduced to minimum simultaneously, and according to center being protruded shape and periphery turned-down edge combination of shapes, the Curvature varying that also can peripheral part be suppressed to produce simultaneously.Further, be made into the semiconductor wafer of shape as above, not only reference surface, also can meet the evaluation index of the flatness index (GBIR, SBIR etc.) of backside reference and the curvature as ZDD so simultaneously.Thereby, it is possible to correspond to all customer requirements under identical grinding condition, and multiple customer requirement can be met.Again, because correspondence can be carried out under identical processing conditions, so productivity and the productive rate of semiconductor wafer can be improved.
Accompanying drawing explanation
Fig. 1 (a) is the summary section of semiconductor wafer of the present invention; Fig. 1 (b) is the outline amplification profile of the peripheral part of semiconductor wafer.
Fig. 2 (a) is the figure of the first scheme of the section shape representing previous silicon wafer; Fig. 2 (b) is the figure of the section shape of the peripheral part representing this silicon wafer and the datum line of SFQR, ESFQR.
Fig. 3 (a) is the figure of the alternative plan of the section shape representing previous silicon wafer; Fig. 3 (b) is the figure of the section shape of the peripheral part representing this silicon wafer and the datum line of SFQR, ESFQR.
Fig. 4 (a) is the figure of the third program of the section shape representing previous silicon wafer; Fig. 4 (b) is the figure of the section shape of the peripheral part representing this silicon wafer and the datum line of SFQR, ESFQR.
Fig. 5 (a) represents that the figure of the section shape of the silicon wafer of shape (△) is protruded at central concave shape (◇), even shape (zero) and center; Fig. 5 (b) is the figure of the section shape of the peripheral part of the silicon wafer representing central concave shape and the datum line of SFQR, ESFQR; Fig. 5 (c) is the figure of the section shape of the peripheral part of the silicon wafer representing even shape and the datum line of SFQR, ESFQR; Fig. 5 (d) represents that the section shape of peripheral part of silicon wafer and the figure of the datum line of SFQR, ESFQR of shape are protruded in center.
Fig. 6 (a) represents that shape is protruded at the center change of shape amount till periphery being set to 200nm, and when the position (turned-down edge starting position, periphery) by the change of shape that turned-down edge causes being set to the position apart from outer circumference end 5mm (apart from center 145mm) (◇), when being set to the position apart from outer circumference end 10mm (distance center 140mm) (zero) and when till periphery with same curvature to change time (△) the figure of section shape of silicon wafer; Fig. 6 (b) is the figure of the section shape of the peripheral part representing the silicon wafer shown in ◇ and the datum line of SFQR, ESFQR; Fig. 6 (c) is the figure of the section shape of the peripheral part representing the silicon wafer shown in zero and the datum line of SFQR, ESFQR; Fig. 6 (d) is the figure of the section shape of the peripheral part representing the silicon wafer shown in △ and the datum line of SFQR, ESFQR.
Fig. 7 (a) represents that shape (the position 100nm thinner than center of periphery 10mm) is protruded at the center change of shape amount till periphery being set to 300nm, and when position change of shape started (turned-down edge starting position, periphery) is set to the position apart from outer circumference end 10mm (apart from center 140mm) (zero), when relative to the wafer shape shown in zero turned-down edge amount being set to the 200nm of half (◇), the figure of the section shape of the silicon wafer of (△) when relative to the wafer shape shown in zero turned-down edge starting position, periphery being set to the position apart from outer circumference end 20mm (apart from center 130mm), Fig. 7 (b) is the figure of the section shape of the peripheral part representing the silicon wafer shown in zero and the datum line of SFQR, ESFQR, Fig. 7 (c) is the figure of the section shape of the peripheral part representing the silicon wafer shown in ◇ and the datum line of SFQR, ESFQR, Fig. 7 (d) is the figure of the section shape of the peripheral part representing the silicon wafer shown in △ and the datum line of SFQR, ESFQR.
Fig. 8 (a) is the figure of the dependency relation representing turned-down edge starting position, periphery and turned-down edge amount and SFQR; Fig. 8 (b) is the figure of the dependency relation representing turned-down edge starting position, periphery and turned-down edge amount and ESFQR.
Fig. 9 (a) represents according to the figure of embodiment 1 with the SFQR maximum (SFQRmax) of the silicon wafer obtained by comparative example 1; Fig. 9 (b) represents according to the figure of embodiment 1 with the ESFQR mean value (ESFQRave) of the silicon wafer obtained by comparative example 1; Fig. 9 (c) represents according to the figure of embodiment 1 with the GBIR of the silicon wafer obtained by comparative example 1.
Figure 10 (a) represents according to the figure of embodiment 1 with the SBIR maximum (SBIRmax) of the silicon wafer obtained by comparative example 1; Figure 10 (b) represents according to the figure of embodiment 1 with the ZDD of the silicon wafer obtained by comparative example 1; Figure 10 (c) represents according to the figure of embodiment 1 with the ROA of the silicon wafer obtained by comparative example 1.
Figure 11 (a) represents according to the figure of embodiment 2 with the SFQR maximum (SFQRmax) of the silicon wafer obtained by comparative example 1; Figure 11 (b) represents according to the figure of embodiment 2 with the ESFQR mean value (ESFQRave) of the silicon wafer obtained by comparative example 1; Figure 11 (c) represents according to the figure of embodiment 2 with the GBIR of the silicon wafer obtained by comparative example 1.
Figure 12 (a) represents according to the figure of embodiment 2 with the SBIR maximum (SBIRmax) of the silicon wafer obtained by comparative example 1; Figure 12 (b) represents according to the figure of embodiment 2 with the ZDD of the silicon wafer obtained by comparative example 1; Figure 12 (c) represents according to the figure of embodiment 2 with the ROA of the silicon wafer obtained by comparative example 1.
Figure 13 is the profile of the ROA illustrated in semiconductor wafer.
Figure 14 is the profile of the ZDD illustrated in semiconductor wafer.
Figure 15 is the vertical view of the ESFQR illustrated in semiconductor wafer.
Embodiment
Below, be described in more detail the present invention, but the present invention not limited by following.The present invention is applicable to the situation that semiconductor wafer is silicon wafer, and is specially adapted to the silicon wafer that diameter is more than 300mm, below, with semiconductor wafer be silicon wafer (silicon chip, siliconwafer) situation centered by illustrate.But, the invention is not restricted to these situations, also can be applicable to the semiconductor wafer beyond silicon wafer.
[shape of previous silicon wafer and the relation of SFQR and ESFQR]
Fig. 2 ~ Fig. 4 illustrates first ~ third program that diameter is the section shape of the previous silicon wafer of 300mm.In Fig. 2 (a), Fig. 3 (a) and Fig. 4 (a), represent a kind of silicon wafer, it is the shape (hereinafter also referred to wing shape (wing shapes)) tilted to suppress turned-down edge to be ground into periphery.So-called wing shape, refers to such as: as the shape shown in H in Fig. 3 (a).Herein, as shown in Figure 2 to 4, wing becomes large according to the order of Fig. 2, Fig. 3, Fig. 4.In Fig. 2 (b), Fig. 3 (b) and Fig. 4 (b), represent the datum line (solid line) of the section shape of peripheral part of silicon wafer, the datum line (dotted line) of SFQR and ESFQR.Originally, SFQR and ESFQR calculates according to the datum level of cell size, herein, in order to make to be easier to understand the impact that SFQR and ESFQR causes by the section shape of silicon wafer, and use with least square method from the datum line calculated by the data of the section shape of silicon wafer, calculate SFQR, ESFQR of hypothesis.
Herein, the periphery exclusionary zone of SFQR is set to apart from wafer outer circumference end 2mm, cell size is assumed to be 26mm × 8mm, and obtains datum line (dotted line) according to least square method.Similarly, the periphery exclusionary zone of ESFQR is set to apart from wafer outer circumference end 1mm, using be assumed to be as the minor axis region of determination object apart from wafer outer circumference end 1mm ~ 35mm, 5 degree, and obtain datum line (solid line) according to least square method.In the mode making the difference of SFQR and ESFQR more easily manifest, with the datum line of SFQR (dotted line) be the length of 8mm, the datum line (solid line) of ESFQR is that the length of 35mm calculates.
Result is as shown in table 1.The SFQR of the silicon wafer shown in Fig. 2 and Fig. 3 is approximately 40nm and is same degree, and the displacement (ROA) apart from the position of position and the distance outer circumference end 1mm (distance center 149mm) of outer circumference end 2mm (apart from center 148mm) is also all approximately 130nm and is same degree.But, the silicon wafer of Fig. 3 that periphery tilts more, ESFQR about 30nm better in the silicon wafer of Fig. 2.Therefore known, in order to improve ESFQR, to make a little grinding becoming the mode of wing shape of peripheral part be effective as Fig. 3 (b).And known, in order to improve the silicon wafer of Fig. 4 that ESFQR makes peripheral part amplitude peak tilt, although ESFQR improves, be subject to the impact of the point of inflexion becoming turned-down edge from wing shape, SFQR does not almost improve.That is, the manufacture method of the previous wafer ground in the mode tilted, is difficult to correspond to flatness requirement more harsh from now on.Particularly, when requiring to improve SFQR and ESFQR simultaneously, can be difficult to respond requirement.
Table 1
[impact that the concaveconvex shape of silicon wafer causes flatness index]
The present inventor improves the method for SFQR and ESFQR both sides simultaneously in order to find out, and based on the shape of current silicon wafer, the concavo-convex impact caused flatness for silicon wafer emulates (Simulation).The section shape of the three kinds of silicon wafers used when emulating is as shown in Fig. 5 (a).Represent when being even shape (zero) in Figure 5, the section shape of silicon wafer of (△) when (◇), Ji Dangshi center protrusion shape (the position 100nm thinner than center of periphery 10mm) when being central concave shape (the position 100nm thicker in center of periphery 10mm).In this emulation, the distance of the ratio in these 3 kinds of silicon wafers outer circumference end 10mm (apart from center 140mm) is made to become identical closer to the turned-down edge shape in outside.Moreover the diameter of silicon wafer is set to 300mm.
The section shape of peripheral part and the datum line of SFQR, ESFQR of the silicon wafer of each shape is represented in Fig. 5 (b) ~ (d).SFQR and the ESFQR of each silicon wafer shown in Fig. 5 is calculated based on this datum line.Moreover datum line specifies in the same manner as the situation of Fig. 2, Fig. 3, SFQR and ESFQR obtains in the same manner as the situation of Fig. 2, Fig. 3.
Result is as shown in table 2.When being central concave shape, SFQR is intermediate grade, but ESFQR the poorest (Fig. 5 (b)).When being even shape, ESFQR is the best, but SFQR the poorest (Fig. 5 (c)).When being center protrusion shape, SFQR is the best and ESFQR is good, and becomes the grade (Fig. 5 (d)) close to even shape.It can thus be appreciated that shape matching is protruded at center easily makes SFQR and ESFQR coexist.That is, in order to improve SFQR and ESFQR both sides, more satisfactory with the shape (protrusion shape) that the imaginary line that SFQR and ESFQR is respective becomes identical slope so as far as possible.
Table 2
[impact from the change of shape of center wafer to periphery causes flatness index]
Secondly, the present inventor is conceived to from the change of shape of center wafer to periphery, emulates the impact that flatness index causes for from the change of shape of center wafer to periphery.The section shape of the three kinds of silicon wafers used when emulating is as shown in Fig. 6 (a).Represent that shape is protruded at the center change of shape amount till periphery being set to 200nm in figure 6, and when the position (turned-down edge starting position, periphery) by the change of shape that turned-down edge causes being set to the position apart from outer circumference end 10mm (apart from center 140mm) (zero), when turned-down edge starting position, periphery being set to the position apart from outer circumference end 5mm (distance center 145mm) (◇) and when till periphery with same curvature to change time (△) the section shape of silicon wafer.Moreover the diameter of silicon wafer is set to 300mm.
The section shape of peripheral part and the datum line of SFQR, ESFQR of the silicon wafer of each shape is represented in Fig. 6 (b) ~ (d).SFQR and the ESFQR of each silicon wafer shown in Fig. 6 is calculated based on this datum line.Moreover datum line specifies in the same manner as the situation of Fig. 2, Fig. 3, SFQR and ESFQR obtains in the same manner as the situation of Fig. 2, Fig. 3.
Result is as shown in table 3.Compare from by Fig. 6 (b) and Fig. 6 (c), even if make turned-down edge starting position move toward wafer outer circumference end side increase smooth position, SFQR, ESFQR also do not improve.But shape is protruded at the center changed with same curvature from center, and the value of SFQR, ESFQR all significantly reduces (Fig. 6 (d)).It can thus be appreciated that desirable wafer shape is the center protrusion shape changed with same curvature till periphery.But, because be in fact not easy to obtain shape as above, emulate for the silicon wafer with the shape that can manufacture.
Table 3
[there is the emulation of the silicon wafer of the shape that can manufacture]
Then, the present inventor emulates for the silicon wafer with the shape that can manufacture.The section shape of the three kinds of silicon wafers used when emulating is as shown in Fig. 7 (a).Represent that shape (the position 100nm thinner than center of periphery 10mm) is protruded at the center change of shape amount till periphery being set to 300nm in the figure 7, and when position change of shape started (turned-down edge starting position, periphery) is set to the position apart from outer circumference end 10mm (apart from center 140mm) (zero), when turned-down edge amount being set to the 100nm of half in the wafer shape shown in zero (◇), the section shape of the silicon wafer of (△) when turned-down edge starting position, periphery being set to the position apart from outer circumference end 20mm (apart from center 130mm) in the wafer shape shown in zero.Moreover the diameter of silicon wafer is set to 300mm.
The section shape of peripheral part and the datum line of SFQR, ESFQR of the silicon wafer of each shape is represented in Fig. 7 (b) ~ (d).SFQR and the ESFQR of each silicon wafer shown in Fig. 7 is calculated based on this datum line.Moreover datum line specifies in the same manner as the situation of Fig. 2, Fig. 3, SFQR and ESFQR obtains in the same manner as the situation of Fig. 2, Fig. 3.
Result is as shown in table 4.Compare from by Fig. 7 (b) and Fig. 7 (c), if make turned-down edge amount be reduced to half, SFQR and ESFQR just can improve.But, compare from by Fig. 7 (b) and Fig. 7 (d), turned-down edge starting position, periphery moved toward central side, improves effectiveness comparison large.
Table 4
[turned-down edge starting position, periphery and the correlation between turned-down edge amount and SFQR and ESFQR]
Then, wafer shape is selected to be that shape and turned-down edge starting position, periphery and the different wafer of turned-down edge amount are protruded in center, use SFQR and ESFQR calculated from section shape, carry out multiple regression analysis for turned-down edge starting position, periphery and the correlation between turned-down edge amount and SFQR and ESFQR.The data used when resolving is as shown in table 5.Moreover turned-down edge starting position, periphery, turned-down edge amount are with the next value read from section shape of naked eyes.SFQR obtains the high correlation of coefficient R=0.82.Similarly, ESFQR obtains the high correlation of coefficient R=0.85.Be as shown in Fig. 8 (a) by the turned-down edge starting position, periphery of multiple regression analysis gained and the relation between turned-down edge amount and SFQR, turned-down edge starting position, periphery and the relation between turned-down edge amount and ESFQR are as shown in Fig. 8 (b).
Table 5
It can thus be appreciated that if turned-down edge starting position, periphery is from outer circumference end toward more than central side 20mm, and turned-down edge amount is below 100nm, just can obtain a kind of wafer, and its SFQR becomes below 25nm and ESFQR becomes below 70nm.Again, if the semiconductor wafer of shape as above, the evaluation index ZDD of curvature can also be improved.Further, backside reference SBIR, because the difference (turned-down edge amount is main degradation factors) being the thickness of peripheral part, so can suppress to improve at below 100nm via by turned-down edge amount.
The present inventor finds from the above results, be made into a kind of semiconductor die plate shape, no matter just can periphery exclusionary zone, datum level how, meet SFQR all simultaneously, SBIR, ESFQR, ZDD, the indexs such as ROA, this semiconductor die plate shape is: shape is protruded at center, and turned-down edge amount (displacement from turned-down edge starting position, periphery to the position apart from outer circumference end 1mm) is set to below 100nm, preferably below 70nm, the starting position of periphery turned-down edge is set to the position from outer circumference end toward central side 20mm, preferably than the wafer peripheral part of the determination object as ESFQR closer to central side (when the cell size of ESFQR is 1 ~ 35mm, the position from outer circumference end toward central side 36mm).Again, find following true and complete the present invention: if be below 100nm from the displacement of central part to turned-down edge starting position, periphery, just when not impacting SFQR, SBIR, ESFQR, ZDD, ROA etc., overall flatness index GBIR can be suppressed.Below describe in detail.
[semiconductor wafer]
The invention provides a kind of semiconductor wafer, it is formed with turned-down edge when grinding in periphery, it is characterized in that:
Between the center of aforesaid semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of aforesaid semiconductor wafer is below 100nm, and the center of aforesaid semiconductor wafer is the shape protruded,
The periphery turned-down edge amount of aforesaid semiconductor wafer is below 100nm, and,
Turned-down edge starting position, aforementioned periphery, be position from the outer circumference end of aforementioned semiconductor wafer toward more than central side 20mm or than the peripheral part as the aforesaid semiconductor wafer of the determination object of ESFQR closer to the position of central side.
First, in Fig. 1 (a), represent the summary section of semiconductor wafer of the present invention; The outline amplification profile of the peripheral part of semiconductor wafer is represented in Fig. 1 (b).The periphery section of semiconductor wafer 11 is made up of (Fig. 1 (b)) straight line and Curves, and this curve has approximately certain curvature.Specifically, semiconductor wafer 11 Shi You center 12, periphery turned-down edge 13, turned-down edge starting position, periphery 14, outer circumference end 15, surface 16 and the back side 17 formed.Again, between the center of semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of semiconductor wafer is as indicated at a, the periphery turned-down edge amount of semiconductor wafer is as shown in B, the distance counted from outer circumference end of turned-down edge starting position, periphery is as shown at c, as shown atd between the center of semiconductor wafer and turned-down edge starting position, periphery, periphery exclusionary zone is as shown in E, and the peripheral part as the semiconductor wafer of the determination object of ESFQR is as shown in F (Fig. 1 (b)).
Semiconductor wafer 11 of the present invention, between the center 12 of semiconductor wafer and turned-down edge starting position, periphery 14, the displacement A of the thickness direction of semiconductor wafer is below 100nm, and the center 12 of semiconductor wafer is the shape (Fig. 1 (a), (b)) protruded.If the displacement A till turned-down edge starting position, 12 to periphery, center 14 is below 100nm, overall flatness index GBIR just can be suppressed.Again, if shape is protruded at center as above, because the respective imaginary line of SFQR and ESFQR is close to identical slope, so SFQR and ESFQR can coexist (compatibility).
Again, semiconductor wafer of the present invention, the periphery turned-down edge amount B being preferably semiconductor wafer 11 is below 100nm, particularly preferably below 70nm (Fig. 1 (b)).And, semiconductor wafer 11 of the present invention, with turned-down edge starting position, periphery 14, be position from the outer circumference end 15 of semiconductor wafer toward more than central side 20mm or than the peripheral part F as the semiconductor wafer of the determination object of ESFQR closer to the position (Fig. 1 (b)) of central side.If the peripheral part of shape as above, just can be made into a kind of semiconductor wafer, and also GBIR can be suppressed at below 250nm, the SFQR of this semiconductor wafer becomes below 25nm and ESFQR becomes below 70nm, and improves the flatness index of more than two kinds simultaneously.Particularly, if periphery turned-down edge amount becomes below 70nm, just can be made into a kind of semiconductor wafer, it improves the flatness indexes such as SFQR, ESFQR, ZDD, ROA, GBIR, SBIR more.
Moreover semiconductor wafer of the present invention, as long as meet above-mentioned center to protrude shape, periphery turned-down edge amount, turned-down edge starting position, periphery, being just not particularly limited, can be semiconductor silicon wafer or compound semiconductor wafer.
And, after the present inventor studies for the method obtaining above-mentioned semiconductor wafer, found that the following fact, and complete the manufacture method of semiconductor wafer of the present invention, this fact is: according to grinding condition, can manufacture the semiconductor wafer having center and protrude of the present invention fairly simplely; And select the abrasive cloth not allowing yielding hardness, just can control the periphery turned-down edge occurred because of abrasive cloth distortion, and obtain the turned-down edge amount of target.Below, the method for the silicon wafer stably obtaining above-mentioned shape is described.
[manufacture method of semiconductor wafer]
In order to manufacture semiconductor wafer as above, the invention provides a kind of manufacture method of semiconductor wafer, monocrystal rod microsection manufacture is being become semiconductor wafer, and this semiconductor wafer is chamfered, and after making its planarization, comprise the grinding step being carried out by aforesaid semiconductor wafer grinding, the feature of the manufacture method of described semiconductor wafer is:
In aforementioned grinding step, to make between the center of aforesaid semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of aforesaid semiconductor wafer becomes below 100nm, and the center of aforesaid semiconductor wafer becomes the mode of the shape of protrusion, aforesaid semiconductor wafer is carried out two-sided lapping
Then, in the mode making the periphery turned-down edge amount of aforesaid semiconductor wafer become below 100nm, and, become position from the outer circumference end of aforementioned semiconductor wafer toward more than central side 20mm to make turned-down edge starting position, aforementioned periphery or than the peripheral part as the aforesaid semiconductor wafer of the determination object of ESFQR closer to the mode of the position of central side, the one side of aforesaid semiconductor wafer is carried out cmp.
[preparing the semiconductor wafer that will be polished]
The manufacture method of semiconductor wafer of the present invention is not particularly limited, and can prepare the semiconductor wafer that will be polished according to following methods.First, carry out slicing process, this slicing process is that monocrystal rod section is obtained semiconductor wafer.The manufacture method of semiconductor crystal bar is not particularly limited, and can use: the method that Cai's method (Czochralskiprocess, CZ method) and floating zone melting method (floatingzonemeltingprocess, FZ method) etc. are previous.Dicing method is also not particularly limited, and inner circumferential blade and multi-wire saw etc. can be used to cut into slices.Secondly, carry out chamfering (chamfering) operation, this is chamfered operation and is chamfered by this peripheral part according to the semiconductor wafer of slicing process gained, and is formed and chamfer portion's (chamfered section).Then, carry out planarization process, this planarization process makes through according to chamfering operation and semiconductor wafer planarization after chamfering.Following operation can be comprised: polishing operation, grinding process and etching work procedure in planarization process.According to above-mentioned operation, the semiconductor wafer that will be polished just can be prepared.
[grinding step]
When being the silicon wafer of diameter 300mm, in general adopt according to two-sided lapping and one side being ground the Ginding process combining to carry out.The turned-down edge amount caused to suppress cmp, with use twin grinder to make center protrude shape be preferred.According to two-sided lapping, just can make fairly simplely and there is the silicon wafer that shape is protruded at center.Specifically, as long as use the method as Japanese Unexamined Patent Publication 2003-285262.Again, even if a kind of double-side polishing apparatus, its rotating disk (platform) does not have Adjusting Shape mechanism, can adjust finishing condition to obtain the silicon wafer that shape is protruded at center yet.Although center also can be obtained according to the cmp of one side protrude shape, if the shape after two-sided lapping is unstable, be just difficult to the shape and the turned-down edge amount that stably obtain expectation.Again, coordinate the shape after two-sided lapping to change grinding condition, the related reduction productivity of meeting, so not preferred.Therefore, preferably make overall shape according to two-sided lapping and suppress the method for periphery turned-down edge according to the cmp of one side.
So, as mentioned above, in grinding step, to make between the center of semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of semiconductor wafer becomes below 100nm, and the center of semiconductor wafer becomes the mode of the shape of protrusion, two-sided lapping semiconductor wafer.As mentioned above, utilize two-sided lapping to make the shape of wafer entirety, the imaginary line making SFQR and ESFQR respective is close to identical slope, so SFQR and ESFQR can coexist.
And, as mentioned above, in the mode making the periphery turned-down edge amount of semiconductor wafer become below 100nm, and, to make turned-down edge starting position, periphery, become position from the outer circumference end of semiconductor wafer toward more than central side 20mm or than the peripheral part as the semiconductor wafer of the determination object of ESFQR closer to the mode of central side, the one side of semiconductor wafer is carried out cmp.Carry out cmp and become the peripheral part of shape as above, just can obtain a kind of semiconductor wafer, its SFQR becomes below 25nm and ESFQR becomes below 70nm, and can manufacture a kind of semiconductor wafer, and it improves the flatness index of more than two kinds simultaneously.Particularly, if periphery turned-down edge amount is below 70nm, just can manufacture a kind of semiconductor wafer, it improves the flatness indexes such as SFQR, ESFQR, ZDD, ROA, GBIR, SBIR more.
Again, in the cmp carrying out one side, preferably use A Si card C hardness to be the abrasive cloth of the nonwoven fabrics system of more than 60 or shore D hardness to be the abrasive cloth that the hardness of the polyurethane series of more than 55 is harder, aforesaid semiconductor wafer is carried out one side grinding.The turned-down edge amount of cmp, although also can change because of grinding condition, but because the degree relevant to the deflection of abrasive cloth is large, as long as so the abrasive cloth selecting hardness as above harder, the turned-down edge amount of expectation just can be obtained via adjustment grinding condition.Again, according to making grinding load or revolution optimization, turned-down edge amount also can be made to become below 70nm.
[embodiment]
Below, enumerate embodiment, comparative example to further illustrate the present invention, but the present invention not limited by following examples.
(embodiment 1)
Monocrystal rod microsection manufacture is become the silicon wafer of diameter 300mm, and this silicon wafer is chamfered (chamfering), and make its planarization.Then, use described twin grinder in Japanese Unexamined Patent Publication 2003-285262 publication and be adjusted to following condition to carry out two-sided lapping: between the center of semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of semiconductor wafer becomes below 100nm, and the center of semiconductor wafer becomes the shape of protrusion.At this moment, because the situation that periphery turned-down edge occurs because of two-sided lapping is not preferred, so abrasive cloth uses hard foamed amine ester pad, NittaHaas MH-S15A is used specifically.Grinding milk is after the abrasive grains be made up of cataloid of granularity 0.05 μm is adjusted to pH10.5, to grind load 200g/cm 2grind.The wafer of shape is protruded in order to stably obtain center, and use rotating disk shape adjusting mechanism, the shape of top rotary table is set to top and protrudes shape (shape that the position outside rotating disk is lower than center of turntable), and initial stage slurries quantity delivered is set to 4L/min, and coordinate the life-span of abrasive cloth, adjust slurry flow on one side in good time, grind.Then, in the mode making the periphery turned-down edge amount of semiconductor wafer become 100nm, and, to make turned-down edge starting position, periphery, become from the outer circumference end of semiconductor wafer toward the mode of the position of central side 20mm, the one side of semiconductor wafer is carried out cmp.At this moment, the abrasive cloth of cmp uses nonwoven fabrics, uses NittaHaas Suba800 (A Si card C hardness is 82) specifically.Grinding milk, after the abrasive grains be made up of cataloid of granularity 0.05 μm is adjusted to pH10.5, grinding load is set to 150g/cm 2, and slurries quantity delivered is set to 3L/min, and grind with rotating disk revolution 30rpm, grinding pad revolution 30rpm.Then, carry out fine finishining grinding, and make the silicon wafer of embodiment 1.Moreover although also can there is periphery turned-down edge because carrying out fine finishining grinding, because the stock removal of grinding is few, and cmp is about 10% on the impact that periphery turned-down edge causes, so do not change condition especially, and carries out with general condition.
(embodiment 2)
Abrasive cloth surface temperature in grinding, because heating can be accumulated in grinding, so the temperature of abrasive cloth central part relatively can raise more than peripheral part.This temperature difference, because can impact grinding rate, so via the scope controlling this region, just can control turned-down edge starting position.In example 2, except adjusting grinding load, grinding head revolution, slurries supplying temperature in the mode of average cut amount in the face not changing wafer, and region high for temperature is increased to is greater than embodiment 1, and to make turned-down edge starting position, periphery, become peripheral part than the semiconductor wafer of the determination object as ESFQR closer to the mode of central side (from outer circumference end toward central side 35mm), the one side of silicon wafer is carried out beyond cmp, all the other carry out similarly to Example 1, and make the silicon wafer of embodiment 2.
(comparative example 1)
Further, except carrying out adjustment in the mode that can form wing shape in the same manner as previously, and carry out beyond two-sided lapping, cmp, all the other carry out similarly to Example 1, and the silicon wafer of comparison example 1.
In order to the embodiment 1 obtained by carrying out in the above described manner compares with the silicon wafer of comparative example 1, and the SFQR maximum (SFQRmax) after the cmp of these silicon wafers is represented at Fig. 9 (a), ESFQR mean value (ESFQRave) after the cmp of these silicon wafers is represented at Fig. 9 (b), GBIR after the cmp of these silicon wafers is represented at Fig. 9 (c), SBIR maximum (SBIRmax) after the cmp of these silicon wafers is represented at Figure 10 (a), ZDD after the cmp of these silicon wafers is represented at Figure 10 (b), ROA after the cmp of these silicon wafers is represented at Figure 10 (c).In Fig. 9 and Figure 10, with ● represent embodiment 1, represent comparative example 1 with zero.Again, the bar chart filled is embodiment 1, and the bar chart do not filled is comparative example 1.Compared with comparative example 1, in embodiment 1, flatness is all improved in all quality projects, and SFQR and the ESFQR being particularly difficult to coexist significantly improves.
In order to the embodiment 2 obtained by carrying out in the above described manner compares with the silicon wafer of comparative example 1, and the SFQR maximum (SFQRmax) after the cmp of these silicon wafers is represented at Figure 11 (a), ESFQR mean value (ESFQRave) after the cmp of these silicon wafers is represented at Figure 11 (b), GBIR after the cmp of these silicon wafers is represented at Figure 11 (c), SBIR maximum (SBIRmax) after the cmp of these silicon wafers is represented at Figure 12 (a), ZDD after the cmp of these silicon wafers is represented at Figure 12 (b), ROA after the cmp of these silicon wafers is represented at Figure 12 (c).In Figure 11 and Figure 12, with ● represent embodiment 2, represent comparative example 1 with zero.Again, the bar chart filled is embodiment 2, and the bar chart do not filled is comparative example 1.Compared with comparative example 1, in example 2, similarly to Example 1, flatness is all improved in all quality projects, and SFQR and the ESFQR being particularly difficult to coexist significantly improves.
Shown by above-mentioned explanation, according to the present invention, a kind of semiconductor wafer can be provided, it is in the flatness index of different SFQR, ESFQR, the ROA etc. more than two kinds of periphery exclusionary zone, can the deviation counted from datum level be reduced to minimum simultaneously, and via center being protruded shape and periphery turned-down edge combination of shapes, the Curvature varying that also can peripheral part be suppressed to produce simultaneously.Again, demonstrate: the semiconductor wafer being made into shape as above, not only reference surface, also can meet the evaluation index of the flatness index (GBIR, SBIR) of backside reference and the curvature as ZDD so simultaneously.And show, all customer requirements can be corresponded under identical grinding condition, and multiple customer requirement can be met.Again, because correspondence can be carried out under identical processing conditions thus, so productivity and the productive rate of semiconductor wafer can be improved.
Moreover the present invention is not limited to above-mentioned execution mode.Above-mentioned execution mode just illustrates, as long as have the formation identical in fact with technological thought described in claims of the present invention and produce same action effect, no matter which kind of is, is included in technical scope of the present invention.

Claims (4)

1. a semiconductor wafer, it is formed on the outer periphery turned-down edge when grinding, and it is characterized in that,
Between the center of aforesaid semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of aforesaid semiconductor wafer is below 100nm, and the center of aforesaid semiconductor wafer is the shape protruded,
The periphery turned-down edge amount of the displacement of the thickness direction as the aforesaid semiconductor wafer from turned-down edge starting position, periphery to the position apart from outer circumference end 1mm of aforesaid semiconductor wafer is below 100nm,
Further, turned-down edge starting position, aforementioned periphery, be position from the outer circumference end of aforementioned semiconductor wafer toward more than central side 20mm or than the peripheral part as the aforesaid semiconductor wafer of the determination object of ESFQR closer to the position of central side.
2. semiconductor wafer as claimed in claim 1, wherein, aforementioned periphery turned-down edge amount is below 70nm.
3. a manufacture method for semiconductor wafer, monocrystal rod microsection manufacture is being become semiconductor wafer by it, and is chamfered by this semiconductor wafer, and after making this semiconductor wafer planarization, comprise the grinding step being carried out by aforesaid semiconductor wafer grinding, it is characterized in that
In aforementioned grinding step, the shape of the top rotary table with two surface grindings of upper lower rotary table is set to top and protrudes shape, and two sides grinding is carried out to aforesaid semiconductor wafer, thus, to make between the center of aforesaid semiconductor wafer and turned-down edge starting position, periphery, the displacement of the thickness direction of aforesaid semiconductor wafer becomes below 100nm, and the center of aforesaid semiconductor wafer becomes the mode of the shape of protrusion, aforesaid semiconductor wafer is carried out two-sided lapping
Then, by the abrasive cloth that use A Si card C hardness is the nonwoven fabrics system of more than 60, or shore D hardness is the abrasive cloth of the polyurethane series of more than 55, while the scope in the region that the surface temperature controlling this abrasive cloth relatively raises than abrasive cloth peripheral part, cmp is carried out to the one side of aforesaid semiconductor wafer, thus, the mode of below 100nm is become using the periphery turned-down edge amount of the displacement making the thickness direction as the aforesaid semiconductor wafer from turned-down edge starting position, periphery to the position apart from outer circumference end 1mm of aforesaid semiconductor wafer, and, to make turned-down edge starting position, aforementioned periphery, become the position from the outer circumference end of aforementioned semiconductor wafer toward more than central side 20mm, or than the peripheral part as the aforesaid semiconductor wafer of the determination object of ESFQR closer to the mode of the position of central side, the one side of aforesaid semiconductor wafer is carried out cmp.
4. the manufacture method of semiconductor wafer as claimed in claim 3, wherein, in aforementioned grinding step, in the mode making aforementioned periphery turned-down edge amount become below 70nm, grinds aforesaid semiconductor wafer.
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6180873B2 (en) * 2013-08-30 2017-08-16 株式会社クラレ Fiber composite sheet, polishing pad and manufacturing method thereof
WO2015167826A1 (en) * 2014-04-30 2015-11-05 1366 Technologies, Inc. Methods and apparati for making thin semi-conductor wafers with locally controlled regions that are relatively thicker than other regions and such wafers
DE102015220924B4 (en) 2015-10-27 2018-09-27 Siltronic Ag Susceptor for holding a semiconductor wafer with orientation notch, method for depositing a layer on a semiconductor wafer and semiconductor wafer
JP6406238B2 (en) * 2015-12-18 2018-10-17 株式会社Sumco Wafer polishing method and polishing apparatus
KR101810643B1 (en) * 2016-02-02 2017-12-19 에스케이실트론 주식회사 Method of controling a flatness of a epitaxial wafer
WO2018198718A1 (en) * 2017-04-28 2018-11-01 Ｊｘ金属株式会社 Semiconductor wafer, and method for polishing semiconductor wafer
DE102017210450A1 (en) 2017-06-21 2018-12-27 Siltronic Ag Method, control system and plant for processing a semiconductor wafer and semiconductor wafer
DE102017210423A1 (en) * 2017-06-21 2018-12-27 Siltronic Ag Method, control system and plant for processing a semiconductor wafer and semiconductor wafer
JP6799509B2 (en) * 2017-07-21 2020-12-16 クラリオン株式会社 Association system, association method
JP6750592B2 (en) * 2017-08-15 2020-09-02 信越半導体株式会社 Method and apparatus for evaluating edge shape of silicon wafer, silicon wafer, and method for selecting and manufacturing the same
WO2019035336A1 (en) * 2017-08-15 2019-02-21 信越半導体株式会社 Evaluation method and evaluation device of edge shape of silicon wafer, silicon wafer, and selection method and manufacturing method thereof
JP6451825B1 (en) * 2017-12-25 2019-01-16 株式会社Sumco Wafer double-side polishing method
DE102018200415A1 (en) * 2018-01-11 2019-07-11 Siltronic Ag Semiconductor wafer with epitaxial layer
KR102518971B1 (en) * 2018-04-13 2023-04-05 가부시키가이샤 사무코 Semiconductor wafer evaluation method and semiconductor wafer manufacturing method
JP7067524B2 (en) * 2019-04-15 2022-05-16 信越半導体株式会社 Wafer flatness measuring machine selection method and measuring method
KR102413432B1 (en) * 2020-08-28 2022-06-27 에스케이실트론 주식회사 Wafer and method for analyzing shape of the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101047144A (en) * 2006-03-31 2007-10-03 硅绝缘体技术有限公司 Method for fabricating a compound-material and method for choosing a wafer

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3341258B2 (en) 1992-11-27 2002-11-05 株式会社東芝 Polishing equipment
JPH08257893A (en) 1995-03-29 1996-10-08 Mitsubishi Materials Corp Device and method for polishing wafer
JP2001326197A (en) 2000-03-10 2001-11-22 Mitsubishi Materials Silicon Corp Polishing method of semiconductor wafer and polishing apparatus thereof
JP2002064071A (en) * 2000-06-09 2002-02-28 Sumitomo Osaka Cement Co Ltd Polishing plate for mirror polishing silicon wafer and method thereof
WO2001096065A1 (en) 2000-06-13 2001-12-20 Shin-Etsu Handotai Co., Ltd. Method for polishing work
WO2002035593A1 (en) * 2000-10-26 2002-05-02 Shin-Etsu Handotai Co.,Ltd. Wafer manufacturing method, polishing apparatus, and wafer
JP3612708B2 (en) 2001-11-29 2005-01-19 信越半導体株式会社 Grooved polishing cloth, workpiece polishing method and polishing apparatus
JP3935757B2 (en) 2002-03-28 2007-06-27 信越半導体株式会社 Wafer double-side polishing apparatus and double-side polishing method
KR20060038612A (en) * 2004-10-30 2006-05-04 주식회사 하이닉스반도체 Method for detection edge roll-off of wafer
JP4881590B2 (en) * 2005-07-27 2012-02-22 ニッタ・ハース株式会社 Polishing cloth
JP2007067179A (en) * 2005-08-31 2007-03-15 Shin Etsu Handotai Co Ltd Mirror-finished surface polishing method and system for semiconductor wafer
JP2007173815A (en) 2005-12-20 2007-07-05 Siltron Inc Silicon wafer polishing machine, retaining assembly used for same, and method of correcting flatness of silicon wafer
KR100841094B1 (en) 2005-12-20 2008-06-25 주식회사 실트론 Silicon wafer grinding apparatus, retaining assembly, and silicon wafer flatness correcting method
JP4904960B2 (en) * 2006-07-18 2012-03-28 信越半導体株式会社 Carrier for double-side polishing apparatus, double-side polishing apparatus and double-side polishing method using the same
JP2008254124A (en) * 2007-04-05 2008-10-23 Toray Ind Inc Grinding pad
JP2009090397A (en) * 2007-10-05 2009-04-30 Nitta Haas Inc Polishing pad
DE102009009497A1 (en) * 2009-02-18 2010-07-08 Siltronic Ag Runner disk for holding conductive disks during reciprocal polish, has recesses for supporting conductive disks and depressing openings for polishing agent supplying polish
JP2011079076A (en) * 2009-10-05 2011-04-21 Toshiba Corp Polishing device and polishing method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101047144A (en) * 2006-03-31 2007-10-03 硅绝缘体技术有限公司 Method for fabricating a compound-material and method for choosing a wafer

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