CN103491320A - Image sensing circuit and method - Google Patents
Image sensing circuit and method Download PDFInfo
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- CN103491320A CN103491320A CN201310400274.5A CN201310400274A CN103491320A CN 103491320 A CN103491320 A CN 103491320A CN 201310400274 A CN201310400274 A CN 201310400274A CN 103491320 A CN103491320 A CN 103491320A
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Abstract
The invention provides an image sensing circuit and method. The image sensing circuit comprises a sensor, an optical signal amplification unit and a sampling and holding unit. The sensor is used for collecting optical signals of incident light rays and converting the optical signals into electrical signals. The optical signal amplification unit integrates the electrical signals to generate integrated signals. The sampling and holding unit comprises at least two parallel signal sampling assemblies and is used for sampling the integrated signals through the at least one signal sampling assembly to generate sampling signals and outputting the generated sampling signals through the at least one signal sampling assembly. The image sensing circuit is used for simultaneously supporting signal conversion and signal output, therefore, the structure of the circuit is simplified, power consumption of the circuit is reduced, and manufacturing cost is reduced.
Description
Technical field
The present invention relates to the electronic circuit technology field, particularly relate to a kind of image sensing circuit and method.
Background technology
Along with scientific and technological progress and development, the image sensing technology is increasingly mature, and the element circuit wherein be connected with transducer is the key factor of the whole image sensing performance of impact, therefore more and more stricter for the designing requirement of element circuit.At first, circuit structure needs simple as far as possible, is convenient in the scope in maximum exposure district integrated more massive pattern matrix; Secondly, the power consumption of circuit is low as far as possible, because, in extensive image chip, the quantity of element circuit is very large, if the element circuit power consumption is large, will be unfavorable for the large-scale integrated of image chip; Again, the noise of circuit is as far as possible little, and the noise of element circuit can reduce signal to noise ratio, and subsequent conditioning circuit also is difficult to eliminate this noise; Finally, for faint light signal, the mode that usually can adopt light signal conversion and signal output simultaneously to carry out, can employ one's time to the best advantage, and efficiency is high, but the more complicated that element circuit often designs causes the element circuit area large, and power consumption is large, and cost is high.Image sensing circuit with reference to a kind of prior art shown in Fig. 1, comprise direct injecting structure (DI), source follower (SF) and sampling hold circuit (SH), this circuit can realize that in unit, sampling keeps, thereby can the supporting signal conversion export the pattern (IWR pattern) of simultaneously carrying out with signal.Because this circuit structure has been introduced source follower SF, so the power consumption of element circuit and area all can increase, perhaps must be in limited area, the size of compression integrating capacitor Cint, not only reduced the charge handling capacity of element circuit, also can reduce signal to noise ratio, simultaneously due to the introducing of source follower SF, increase the noise of circuit.
Therefore, one of problem that those skilled in the art are in the urgent need to address is, a kind of image sensing cell circuit and method of low-power consumption is provided, in order to supporting signal conversion and signal output, carry out simultaneously, simplify circuit structure, reduce the power consumption of circuit, reduce manufacturing cost.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of image sensing circuit and method, in order to the integration of supporting signal and the output of signal, carries out simultaneously, simplifies circuit structure, reduces the power consumption of circuit, reduces manufacturing cost.
In order to address the above problem, the invention discloses a kind of image sensing circuit, comprising:
Transducer, for gathering the light signal of incident ray, and convert described light signal to the signal of telecommunication;
The optical signal amplifying big unit, carry out integration to the described signal of telecommunication, the formation product sub-signal;
Sample holding unit, the signal sampling assembly that comprises at least two parallel connections, for by described at least one signal sampling assembly, described integrated signal being sampled and generated sampled signal, and, by at least one other signal sampling assembly, the sampled signal that output has generated.
Preferably, the input of described transducer is connected and fixed voltage, and output connects described optical signal amplifying big unit.
Preferably, described optical signal amplifying big unit comprises the first transistor M1, transistor seconds M2, and, integrating capacitor Cint; The grid of described the first transistor M1 connects controls voltage VR1, source electrode connects the output of described transducer, drain electrode connects the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 connects resetting voltage VR2, grid connects reset signal RST, described integrating capacitor Cint ground connection;
When described reset signal RST is low level, described transistor seconds M2 cut-off, described integrating capacitor Cint carries out integration formation product sub-signal to the described signal of telecommunication;
When described reset signal RST is high level, described transistor seconds M2 conducting, described integrating capacitor Cint is resetted removes described integrated signal.
Preferably, described optical signal amplifying big unit also comprises operational amplifier, the positive pole of the input of described operational amplifier connects described control voltage VR1, the negative pole of input connects the output of described transducer and the source electrode of described the first transistor M1, output connects the grid of described the first transistor M1, the drain electrode of described the first transistor M1 connects the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 connects resetting voltage VR2, grid connects reset signal RST, described integrating capacitor Cint ground connection.
Preferably, described sampling component comprises the first sampling component and the second sampling component, and described the first sampling component comprises the 3rd transistor M3, the 4th transistor M4, and, the first sampling capacitance Cs1; Described the second sampling component comprises the 5th transistor M5, the 6th transistor M6, and, the second sampling capacitance Cs2; The grid of described the 3rd transistor M3 connects the first control signal S1, the grid of described the 4th transistor M4 connects the second control signal S2, the grid of described the 5th transistor M5 connects the 3rd control signal S3, and the grid of described the 6th transistor M6 connects the 4th control signal S4; The drain electrode of described the 3rd transistor M3 is connected with the source electrode of described the 4th transistor M4, and is connected with described the first sampling capacitance Cs1; The drain electrode of described the 5th transistor M5 is connected with the source electrode of the 6th transistor M6, and is connected with described the second sampling capacitance Cs2, and the drain electrode of described the 4th transistor M4 is connected with the drain electrode of described the 6th transistor M6; Described the first sampling capacitance Cs1 and the second sampling capacitance Cs2 ground connection;
Before described reset signal RST transfers low level to from high level for the first time, described the first control signal S1 transfers high level to, described the 3rd transistor M3 conducting, and described the first sampling capacitance Cs1 samples and generates the first sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the first time, described the first control signal S1 transfers low level to, described the 3rd transistor M3 cut-off;
Before described reset signal RST transfers low level to from high level for the second time, described the second control signal S2 transfers high level to, and described the 4th transistor M4 conducting is also exported described the first sampled signal; Described the 3rd control signal S3 transfers high level to, described the 5th transistor M5 conducting, and described the second sampling capacitance Cs2 samples and generates the second sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the second time, described the 3rd control signal S3 transfers low level to, described the 5th transistor M5 cut-off;
Before described reset signal RST transfers low level to from high level for the third time, described the 4th control signal S4 transfers high level to, and described the 6th transistor M6 conducting is also exported described the second sampled signal.
The embodiment of the invention also discloses a kind of method of image sensing, comprising:
Gather the light signal of incident ray, and convert described light signal to the signal of telecommunication;
The described signal of telecommunication is carried out to integration, the formation product sub-signal;
By described at least one signal sampling assembly, described integrated signal is sampled and generated sampled signal, and, by least one other signal sampling assembly, the sampled signal that output has generated.
Preferably, the described signal of telecommunication is generated by transducer, and integrated signal is generated by the optical signal amplifying big unit; The input of described transducer is connected and fixed voltage, and output connects described optical signal amplifying big unit.
Preferably, described optical signal amplifying big unit comprises the first transistor M1, transistor seconds M2, and, integrating capacitor Cint; The grid of described the first transistor M1 connects controls voltage VR1, source electrode connects the output of described transducer, drain electrode connects the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 connects resetting voltage VR2, grid connects reset signal RST, described integrating capacitor Cint ground connection;
When described reset signal RST is low level, described transistor seconds M2 cut-off, described integrating capacitor Cint carries out integration formation product sub-signal to the described signal of telecommunication;
When described reset signal RST is high level, described transistor seconds M2 conducting, described integrating capacitor Cint is resetted removes described integrated signal.
Preferably, described optical signal amplifying big unit also comprises operational amplifier, the positive pole of the input of described operational amplifier connects described control voltage VR1, the negative pole of input connects the output of described transducer and the source electrode of described the first transistor M1, output connects the grid of described the first transistor M1, the drain electrode of described the first transistor M1 connects the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 connects resetting voltage VR2, grid connects reset signal RST, described integrating capacitor Cint ground connection.
Preferably, described sampled signal is generated by the Sampling hold unit, and described sample holding unit comprises sampling component, described sampling component comprises the first sampling component and the second sampling component, and described the first sampling component comprises the 3rd transistor M3, the 4th transistor M4, and, the first sampling capacitance Cs1; Described the second sampling component comprises the 5th transistor M5, the 6th transistor M6, and, the second sampling capacitance Cs2; The grid of described the 3rd transistor M3 connects the first control signal S1, the grid of described the 4th transistor M4 connects the second control signal S2, the grid of described the 5th transistor M5 connects the 3rd control signal S3, and the grid of described the 6th transistor M6 connects the 4th control signal S4; The drain electrode of described the 3rd transistor M3 is connected with the source electrode of described the 4th transistor M4, and is connected with described the first sampling capacitance Cs1; The drain electrode of described the 5th transistor M5 is connected with the source electrode of the 6th transistor M6, and is connected with described the second sampling capacitance Cs2, and the drain electrode of described the 4th transistor M4 is connected with the drain electrode of described the 6th transistor M6; Described the first sampling capacitance Cs1 and the second sampling capacitance Cs2 ground connection;
Before described reset signal RST transfers low level to from high level for the first time, described the first control signal S1 transfers high level to, described the 3rd transistor M3 conducting, and described the first sampling capacitance Cs1 samples and generates the first sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the first time, described the first control signal S1 transfers low level to, described the 3rd transistor M3 cut-off;
Before described reset signal RST transfers low level to from high level for the second time, described the second control signal S2 transfers high level to, and described the 4th transistor M4 conducting is also exported described the first sampled signal; Described the 3rd control signal S3 transfers high level to, described the 5th transistor M5 conducting, and described the second sampling capacitance Cs2 samples and generates the second sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the second time, described the 3rd control signal S3 transfers low level to, described the 5th transistor M5 cut-off;
Before described reset signal RST transfers low level to from high level for the third time, described the 4th control signal S4 transfers high level to, and described the 6th transistor M6 conducting is also exported described the second sampled signal.
Compared with prior art, the present invention includes following advantage:
The light signal that the embodiment of the present invention will gather incident ray by transducer is converted to the signal of telecommunication, again by optical signal amplifier to described signal of telecommunication integration formation product sub-signal, by the sample holding unit that comprises at least two signal sampling assemblies in parallel, described integrated signal is sampled again, and, the sampled signal that output has generated.With respect to the image sensing circuit of prior art, if will realize the integration of while supporting signal and the output of signal, need to introduce active device.And the embodiment of the present invention does not need to increase any active device integration of supporting signal and the output of signal simultaneously, thereby reduce the power consumption of circuit, simplified circuit structure simultaneously.
Due to the circuit structure of the embodiment of the present invention, do not introduce extra noise source, improved signal to noise ratio.And, due to sampling capacitance with reset and integration together with integrating capacitor is, integrating capacitor has also played the effect of stored charge, thereby can improve the charge handling capacity of optical signal amplifying big unit.
The sample holding unit that the embodiment of the present invention proposes, do not have specific (special) requirements to light signal amplification circuit, therefore be applicable to various signal sample circuits.
The accompanying drawing explanation
Fig. 1 is a kind of image sensing circuit of prior art;
Fig. 2 is the structure chart of a kind of image sensing circuit embodiments 1 of the present invention;
Fig. 3 is the structure chart of a kind of image sensing circuit embodiments 2 of the present invention;
Fig. 4 is the sequential chart of the concrete example of a kind of image sensing circuit of the present invention;
Fig. 5 is the structural representation of a kind of image sensing circuit of the present invention;
Fig. 6 is the structure chart of a kind of image sensing circuit embodiments 3 of the present invention;
Fig. 7 is the flow chart of steps of the embodiment of a kind of image sensing method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
One of core idea of the embodiment of the present invention is, the light signal that at first by transducer, will gather incident ray is converted to the signal of telecommunication, and by optical signal amplifier to described signal of telecommunication integration formation product sub-signal, by the sample holding unit that comprises at least two signal sampling assemblies in parallel, described integrated signal is sampled again, and, the sampled signal that output has generated, supporting signal conversion simultaneously and signal output, owing to not needing to increase any active device, thereby reduced the power consumption of circuit, simplified circuit structure simultaneously.
Embodiment mono-
With reference to Fig. 2, show the structure chart of a kind of image sensing circuit embodiments 1 of the present invention, specifically can comprise:
Transducer 101, for gathering the light signal of incident ray, and convert described light signal to the signal of telecommunication;
In a preferred embodiment of the present invention, the input of described transducer can connect operating voltage, and output can connect described optical signal amplifying big unit.
Optical signal amplifying big unit 102, carry out integration to the described signal of telecommunication, the formation product sub-signal;
In embodiments of the present invention, the signal sampling assembly that at least comprises two parallel connections in sample holding unit, when the optical signal amplifying big unit carries out integration formation product sub-signal to the signal of telecommunication by the transducer conversion, in sample holding unit wherein one group of sampling component can sample and generate sampled signal integrated signal, other sampling component can be by the sampled signal output generated, make the image sensing circuit support the IWR pattern, can carry out the output of integration and the signal of signal simultaneously.
It should be noted that, described transducer can be photodiode or photo resistance, certainly, also can select other transducer, and the embodiment of the present invention is without this is restricted.
Embodiment bis-
With reference to Fig. 3, show the structure chart of the embodiment 2 of a kind of image sensing circuit of the present invention, specifically can comprise:
Transducer 201, for gathering the light signal of incident ray, and convert described light signal to the signal of telecommunication;
Optical signal amplifying big unit 202, carry out integration to the described signal of telecommunication, the formation product sub-signal;
In a preferred embodiment of the present invention, described optical signal amplifying big unit 202 can comprise the first transistor M1, transistor seconds M2, and, integrating capacitor Cint; The grid of described the first transistor M1 can connect controls voltage VR1, source electrode can connect the output of described transducer, drain electrode can connect the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 can connect resetting voltage VR2, grid can connect reset signal RST, and described integrating capacitor Cint can ground connection;
When described reset signal RST is low level, described transistor seconds M2 cut-off, described integrating capacitor Cint carries out integration formation product sub-signal to the described signal of telecommunication;
When described reset signal RST is high level, described transistor seconds M2 conducting, described integrating capacitor Cint is resetted removes described integrated signal.
Sample holding unit 203, the signal sampling assembly that comprises at least two parallel connections, for by described at least one signal sampling assembly, described integrated signal being sampled and generated sampled signal, and, by at least one other signal sampling assembly, the sampled signal that output has generated.
In a preferred embodiment of the present invention, sampling component in described sample holding unit 203 can comprise the first sampling component and the second sampling component, and described the first sampling component can comprise the 3rd transistor M3, the 4th transistor M4, and, the first sampling capacitance Cs1; Described the second sampling component can comprise the 5th transistor M5, the 6th transistor M6, and, the second sampling capacitance Cs2; The grid of described the 3rd transistor M3 can connect the first control signal S1, the grid of described the 4th transistor M4 can connect the second control signal S2, the grid of described the 5th transistor M5 can connect the 3rd control signal S3, and the grid of described the 6th transistor M6 can connect the 4th control signal S4; The drain electrode of described the 3rd transistor M3 can be connected with the source electrode of described the 4th transistor M4, and is connected with described the first sampling capacitance Cs1; The drain electrode of described the 5th transistor M5 can be connected with the source electrode of the 6th transistor M6, and is connected with described the second sampling capacitance Cs2, and the drain electrode of described the 4th transistor M4 can be connected with the drain electrode of described the 6th transistor M6; Described the first sampling capacitance Cs1 and the second sampling capacitance Cs2 can ground connection;
Before described reset signal RST transfers low level to from high level for the first time, described the first control signal S1 transfers high level to, described the 3rd transistor M3 conducting, and described the first sampling capacitance Cs1 samples and generates the first sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the first time, described the first control signal S1 transfers low level to, described the 3rd transistor M3 cut-off;
Before described reset signal RST transfers low level to from high level for the second time, described the second control signal S2 transfers high level to, and described the 4th transistor M4 conducting is also exported described the first sampled signal; Described the 3rd control signal S3 transfers high level to, described the 5th transistor M5 conducting, and described the second sampling capacitance Cs2 samples and generates the second sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the second time, described the 3rd control signal S3 transfers low level to, described the 5th transistor M5 cut-off;
Before described reset signal RST transfers low level to from high level for the third time, described the 4th control signal S4 transfers high level to, and described the 6th transistor M6 conducting is also exported described the second sampled signal.
In embodiments of the present invention, the image sensing circuit is by transducer, optical signal amplifying big unit (DI) and sampling hold circuit (SH) form, control voltage VR1 in the optical signal amplifying big unit is for controlling the pressure drop of external sensor, its size is determined by the input current potential of transducer, the action that reset signal RST controls integrating capacitor Cint integration and resets.Sample holding unit consists of sampling capacitance Cs1～2,4 transistor M3～6 and 2, and 4 transistors are controlled by control signal S1～4 respectively, to control sampling hold circuit, completes sampling and reads action.
Particularly, with reference to the sequential chart of the concrete example of the of the present invention a kind of image sensing circuit shown in Fig. 4, the work schedule of reset signal RST is identical with the work schedule of Fig. 4.
1, when reset signal RST is high level for the first time, transistor seconds M2 conducting, the optical signal amplifying big unit resets for the first time, removes integrated signal formerly on integrating capacitor Cint.Now the current potential of integrating capacitor Cint is VR1.
2, when reset signal RST will be converted to low level by high level for the first time, at Δ T1 before this time period, the first control signal S1 is converted to high level, the 3rd transistor M3 conducting, and the first sampling capacitance Cs1 resets together with integrating capacitor Cint.
3, when reset signal RST is low level for the first time, the first sampling capacitance Cs1 and integrating capacitor Cint for the first time together with integration.Wherein, integrating capacitor Cint generates the first integral signal, and sampling capacitance Cs1 samples and generates the first sampled signal described first integral signal.
4, when reset signal RST will be high level by low transition for the first time, at Δ T2 in this time period, the first control signal S1 is converted to low level, the 3rd transistor M3 cut-off, and the first sampled signal has been saved in the first sampling capacitance Cs1.
5, when reset signal RST is high level for the second time, transistor seconds M2 conducting, the optical signal amplifying big unit resets for the second time, removes the first integral signal on integrating capacitor Cint.When the second control signal S2 is converted to high level, the 4th transistor M4 conducting, read the first sampled signal on the first sampling capacitance Cs1 export.Wherein, can be set to continue to approach the cycle of 1 reset signal RST the readout time of the second control signal S2.
6, when reset signal RST will be converted to low level by high level for the second time, at Δ T1 before this time period, the 3rd control signal S3 is converted to high level, the 5th transistor M5 conducting, the second sampling capacitance Cs2 and integrating capacitor Cint reset together with for the second time.
7, when reset signal RST is low level for the second time, the second sampling capacitance Cs2 and integrating capacitor Cint for the second time together with integration.Wherein, integrating capacitor Cint generates the second integral signal, and the second sampling capacitance Cs2 samples and generates the second sampled signal described second integral signal.
8, when reset signal RST will be high level by low transition for the second time, at Δ T2 before this time period, the 3rd control signal S3 is converted to low level, the 5th transistor cut-off, and the second sampled signal has been saved in the second sampling capacitance Cs2.
9, when reset signal RST is high level for the third time, reset switch SW
rSTclosure, the optical signal amplifying big unit resets for the third time; Remove the second integral signal of integrating capacitor Cint.When the 4th control signal S4 is converted to high level, the 6th transistor turns, read the second sampled signal on the second sampling capacitance Cs2 export.Wherein, can be set to continue to approach the cycle of 1 reset signal RST the readout time of the 4th control signal S4.
The image sensing circuit can continue according to the work schedule in Fig. 4, and the output of integration and the signal of signal is carried out in realization simultaneously, makes the image sensing circuit support the IWR pattern.
With respect to the image sensing circuit of realizing the IWR pattern in prior art, do not increase any active device due to the circuit structure in the embodiment of the present invention, therefore reduced the power consumption of circuit, circuit structure is simple simultaneously, does not have extra noise source and introduces.In addition, due to sampling capacitance and integrating capacitor, jointly carry out integration, so integrating capacitor has also played the effect of stored charge, thereby can improve the charge handling capacity of optical signal amplifying big unit.
It should be noted that, transistor has in embodiments of the present invention played on-off action, under the sequential of setting, can carry out the output of integration and the signal of signal by conducting and the cut-off realization of circuit so simultaneously.For example, yet can use such as cmos switch and replace transistor, the embodiment of the present invention is not restricted this.
Realize carrying out the integration of signal and the principle of signal output in order to make those skilled in the art further understand the embodiment of the present invention simultaneously, below adopt a concrete example to illustrate.
With reference to the structural representation of the of the present invention a kind of image sensing circuit shown in Fig. 5, reset switch SWRST is controlled by reseting controling signal RST, and 4 control switch SW1～4 are controlled by control signal S1～4 respectively.The specific implementation process is as follows:
When light signal amplification circuit resets fast the end for the first time, the first control signal S1 controls the first switch SW 1 closure, the first sampling capacitance Cs1 resets and integration together with light signal amplification circuit, when light signal amplification circuit when integration finishes soon for the first time, the first control signal S1 controls the first switch SW 1 and disconnects, the integrated signal of light signal amplification circuit is sampled on the first sampling capacitance Cs1, when needs are read, the second control signal S2 controls second switch SW2 closure, and the integrated signal on the first sampling capacitance Cs1 is read;
When light signal amplification circuit resets fast the end for the second time, the 3rd control signal S3 controls the 3rd switch SW 3 closures, the second sampling capacitance Cs2 resets and integration together with light signal amplification circuit, when light signal amplification circuit when integration finishes soon for the second time, the 3rd control signal S3 controls the 3rd switch SW 3 and disconnects, the integrated signal of light signal amplification circuit is sampled on the second sampling capacitance Cs2, after the second control signal S2 controls second switch SW2 disconnection, the 4th control signal S4 just can control the 4th switch SW 4 closures, sampled signal on the second sampling capacitance Cs2 is read, the first sampling capacitance Cs1 and the second sampling capacitance Cs2 can hocket and sample and read action according to the sequential such as Fig. 4 or other settings, make the image sensing circuit support the IWR pattern.
Embodiment tri-
With reference to Fig. 6, show the structure chart of the embodiment 3 of a kind of image sensing circuit of the present invention,
In a preferred embodiment of the present invention, the input of described transducer can connect operating voltage, and output can connect described optical signal amplifying big unit.
Optical signal amplifying big unit 302, carry out integration to the described signal of telecommunication, the formation product sub-signal;
In a preferred embodiment of the present invention, described optical signal amplifying big unit can also comprise operational amplifier, the positive pole of the input of described operational amplifier can connect described control voltage VR1, the negative pole of input can connect the output of described transducer and the source electrode of described the first transistor M1, output can connect the grid of described the first transistor M1, the drain electrode of described the first transistor M1 can connect the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 can connect resetting voltage VR2, grid can connect reset signal RST, described integrating capacitor Cint can ground connection.
In specific implementation, the optical signal amplifying big unit can also add operational amplifier OPA, forms the optical signal amplifying big unit (BDI) of band buffering, can control better thus the pressure drop of external sensor, thereby can improve the injection efficiency of transducer.
Certainly, the structure of optical signal amplifying big unit is only as example, and it is all feasible that those skilled in the art adopt other corresponding constructions according to the actual requirements, the present invention to this without being limited.
Sample holding unit 303, the signal sampling assembly that comprises at least two parallel connections, for by described at least one signal sampling assembly, described integrated signal being sampled and generated sampled signal, and, by at least one other signal sampling assembly, the sampled signal that output has generated.
Because the work schedule that adds the image sensing circuit after operational amplifier OPA can be identical with the work schedule in Fig. 4, implementation procedure is also identical, therefore do not repeat at this.
Embodiment tetra-
With reference to Fig. 7, show the flow chart of steps of the embodiment of the method for a kind of image sensing of the present invention, specifically can comprise the steps:
Step 401, gather the light signal of incident ray, and convert described light signal to the signal of telecommunication;
In a preferred embodiment of the present invention, the described signal of telecommunication can be generated by transducer, and integrated signal can be generated by the optical signal amplifying big unit; The input of described transducer can connect operating voltage, and output can connect described optical signal amplifying big unit.
Step 402, carry out integration to the described signal of telecommunication, the formation product sub-signal;
In a preferred embodiment of the present invention, described optical signal amplifying big unit can comprise the first transistor M1, transistor seconds M2, and, integrating capacitor Cint; The grid of described the first transistor M1 connects controls voltage VR1, source electrode can connect the output of described transducer, drain electrode can connect the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 can connect resetting voltage VR2, grid can connect reset signal RST, and described integrating capacitor Cint can ground connection;
When described reset signal RST is low level, described transistor seconds M2 cut-off, described integrating capacitor Cint carries out integration formation product sub-signal to the described signal of telecommunication;
When described reset signal RST is high level, described transistor seconds M2 conducting, described integrating capacitor Cint is resetted removes described integrated signal.
In a preferred embodiment of the present invention, described optical signal amplifying big unit can also comprise operational amplifier, the positive pole of the input of described operational amplifier can connect described control voltage VR1, the negative pole of input can connect the output of described transducer and the source electrode of described the first transistor M1, output connects the grid of described the first transistor M1, the drain electrode of described the first transistor M1 can connect the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 can connect resetting voltage VR2, grid can connect reset signal RST, described integrating capacitor Cint can ground connection.
Step 403, sample and generate sampled signal described integrated signal by described at least one signal sampling assembly, and, by least one other signal sampling assembly, the sampled signal that output has generated.
In a preferred embodiment of the present invention, described sampled signal is by generating the Sampling hold unit, described sample holding unit can comprise sampling component, described sampling component can comprise the first sampling component and the second sampling component, described the first sampling component can the 3rd transistor M3, the 4th transistor M4, and, the first sampling capacitance Cs1; Described the second sampling component can comprise the 5th transistor M5, the 6th transistor M6, and, the second sampling capacitance Cs2; The grid of described the 3rd transistor M3 can connect the first control signal S1, the grid of described the 4th transistor M4 can connect the second control signal S2, the grid of described the 5th transistor M5 can connect the 3rd control signal S3, and the grid of described the 6th transistor M6 can connect the 4th control signal S4; The drain electrode of described the 3rd transistor M3 can be connected with the source electrode of described the 4th transistor M4, and can be connected with described the first sampling capacitance Cs1; The drain electrode of described the 5th transistor M5 can be connected with the source electrode of the 6th transistor M6, and can be connected with described the second sampling capacitance Cs2, and the drain electrode of described the 4th transistor M4 can be connected with the drain electrode of described the 6th transistor M6; Described the first sampling capacitance Cs1 and the second sampling capacitance Cs2 can ground connection;
Before described reset signal RST transfers low level to from high level for the first time, described the first control signal S1 transfers high level to, described the 3rd transistor M3 conducting, and described the first sampling capacitance Cs1 samples and generates the first sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the first time, described the first control signal S1 transfers low level to, described the 3rd transistor M3 cut-off;
Before described reset signal RST transfers low level to from high level for the second time, described the second control signal S2 transfers high level to, and described the 4th transistor M4 conducting is also exported described the first sampled signal; Described the 3rd control signal S3 transfers high level to, described the 5th transistor M5 conducting, and described the second sampling capacitance Cs2 samples and generates the second sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the second time, described the 3rd control signal S3 transfers low level to, described the 5th transistor M5 cut-off;
Before described reset signal RST transfers low level to from high level for the third time, described the 4th control signal S4 transfers high level to, and described the 6th transistor M6 conducting is also exported described the second sampled signal.
It should be noted that, for embodiment of the method, for simple description, therefore it all is expressed as to a series of combination of actions, but those skilled in the art should know, the present invention is not subject to the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in specification all belongs to preferred embodiment, and related action and unit might not be that the present invention is necessary.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment that between each embodiment, identical similar part is mutually referring to getting final product.
Above to a kind of image sensing circuit provided by the present invention and method, be described in detail, applied specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention simultaneously.
Claims (10)
1. an image sensing circuit, is characterized in that, comprising:
Transducer, for gathering the light signal of incident ray, and convert described light signal to the signal of telecommunication;
The optical signal amplifying big unit, carry out integration to the described signal of telecommunication, the formation product sub-signal;
Sample holding unit, the signal sampling assembly that comprises at least two parallel connections, for by described at least one signal sampling assembly, described integrated signal being sampled and generated sampled signal, and, by at least one other signal sampling assembly, the sampled signal that output has generated.
2. image sensing circuit according to claim 1, is characterized in that, the input of described transducer is connected and fixed voltage, and output connects described optical signal amplifying big unit.
3. image sensing circuit according to claim 1, is characterized in that, described optical signal amplifying big unit comprises the first transistor M1, transistor seconds M2, and, integrating capacitor Cint; The grid of described the first transistor M1 connects controls voltage VR1, source electrode connects the output of described transducer, drain electrode connects the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 connects resetting voltage VR2, grid connects reset signal RST, described integrating capacitor Cint ground connection;
When described reset signal RST is low level, described transistor seconds M2 cut-off, described integrating capacitor Cint carries out integration formation product sub-signal to the described signal of telecommunication;
When described reset signal RST is high level, described transistor seconds M2 conducting, described integrating capacitor Cint is resetted removes described integrated signal.
4. image sensing circuit according to claim 3, it is characterized in that, described optical signal amplifying big unit also comprises operational amplifier, the positive pole of the input of described operational amplifier connects described control voltage VR1, the negative pole of input connects the output of described transducer and the source electrode of described the first transistor M1, output connects the grid of described the first transistor M1, the drain electrode of described the first transistor M1 connects the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 connects resetting voltage VR2, grid connects reset signal RST, described integrating capacitor Cint ground connection.
5. according to the described image sensing circuit of claim 3 or 4, it is characterized in that, described sampling component comprises the first sampling component and the second sampling component, and described the first sampling component comprises the 3rd transistor M3, the 4th transistor M4, and, the first sampling capacitance Cs1; Described the second sampling component comprises the 5th transistor M5, the 6th transistor M6, and, the second sampling capacitance Cs2; The grid of described the 3rd transistor M3 connects the first control signal S1, the grid of described the 4th transistor M4 connects the second control signal S2, the grid of described the 5th transistor M5 connects the 3rd control signal S3, and the grid of described the 6th transistor M6 connects the 4th control signal S4; The drain electrode of described the 3rd transistor M3 is connected with the source electrode of described the 4th transistor M4, and is connected with described the first sampling capacitance Cs1; The drain electrode of described the 5th transistor M5 is connected with the source electrode of the 6th transistor M6, and is connected with described the second sampling capacitance Cs2, and the drain electrode of described the 4th transistor M4 is connected with the drain electrode of described the 6th transistor M6; Described the first sampling capacitance Cs1 and the second sampling capacitance Cs2 ground connection;
Before described reset signal RST transfers low level to from high level for the first time, described the first control signal S1 transfers high level to, described the 3rd transistor M3 conducting, and described the first sampling capacitance Cs1 samples and generates the first sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the first time, described the first control signal S1 transfers low level to, described the 3rd transistor M3 cut-off;
Before described reset signal RST transfers low level to from high level for the second time, described the second control signal S2 transfers high level to, and described the 4th transistor M4 conducting is also exported described the first sampled signal; Described the 3rd control signal S3 transfers high level to, described the 5th transistor M5 conducting, and described the second sampling capacitance Cs2 samples and generates the second sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the second time, described the 3rd control signal S3 transfers low level to, described the 5th transistor M5 cut-off;
Before described reset signal RST transfers low level to from high level for the third time, described the 4th control signal S4 transfers high level to, and described the 6th transistor M6 conducting is also exported described the second sampled signal.
6. the method for an image sensing, is characterized in that, comprising:
Gather the light signal of incident ray, and convert described light signal to the signal of telecommunication;
The described signal of telecommunication is carried out to integration, the formation product sub-signal;
By described at least one signal sampling assembly, described integrated signal is sampled and generated sampled signal, and, by least one other signal sampling assembly, the sampled signal that output has generated.
7. method according to claim 6, is characterized in that, the described signal of telecommunication is generated by transducer, and integrated signal is generated by the optical signal amplifying big unit; The input of described transducer is connected and fixed voltage, and output connects described optical signal amplifying big unit.
8. method according to claim 6, is characterized in that, described optical signal amplifying big unit comprises the first transistor M1, transistor seconds M2, and, integrating capacitor Cint; The grid of described the first transistor M1 connects controls voltage VR1, source electrode connects the output of described transducer, drain electrode connects the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 connects resetting voltage VR2, grid connects reset signal RST, described integrating capacitor Cint ground connection;
When described reset signal RST is low level, described transistor seconds M2 cut-off, described integrating capacitor Cint carries out integration formation product sub-signal to the described signal of telecommunication;
When described reset signal RST is high level, described transistor seconds M2 conducting, described integrating capacitor Cint is resetted removes described integrated signal.
9. method according to claim 8, it is characterized in that, described optical signal amplifying big unit also comprises operational amplifier, the positive pole of the input of described operational amplifier connects described control voltage VR1, the negative pole of input connects the output of described transducer and the source electrode of described the first transistor M1, output connects the grid of described the first transistor M1, the drain electrode of described the first transistor M1 connects the drain electrode of described integrating capacitor Cint and described transistor seconds M2, the source electrode of described transistor seconds M2 connects resetting voltage VR2, grid connects reset signal RST, described integrating capacitor Cint ground connection.
10. method according to claim 8 or claim 9, it is characterized in that, described sampled signal is generated by the Sampling hold unit, described sample holding unit comprises sampling component, described sampling component comprises the first sampling component and the second sampling component, and described the first sampling component comprises the 3rd transistor M3, the 4th transistor M4, and, the first sampling capacitance Cs1; Described the second sampling component comprises the 5th transistor M5, the 6th transistor M6, and, the second sampling capacitance Cs2; The grid of described the 3rd transistor M3 connects the first control signal S1, the grid of described the 4th transistor M4 connects the second control signal S2, the grid of described the 5th transistor M5 connects the 3rd control signal S3, and the grid of described the 6th transistor M6 connects the 4th control signal S4; The drain electrode of described the 3rd transistor M3 is connected with the source electrode of described the 4th transistor M4, and is connected with described the first sampling capacitance Cs1; The drain electrode of described the 5th transistor M5 is connected with the source electrode of the 6th transistor M6, and is connected with described the second sampling capacitance Cs2, and the drain electrode of described the 4th transistor M4 is connected with the drain electrode of described the 6th transistor M6; Described the first sampling capacitance Cs1 and the second sampling capacitance Cs2 ground connection;
Before described reset signal RST transfers low level to from high level for the first time, described the first control signal S1 transfers high level to, described the 3rd transistor M3 conducting, and described the first sampling capacitance Cs1 samples and generates the first sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the first time, described the first control signal S1 transfers low level to, described the 3rd transistor M3 cut-off;
Before described reset signal RST transfers low level to from high level for the second time, described the second control signal S2 transfers high level to, and described the 4th transistor M4 conducting is also exported described the first sampled signal; Described the 3rd control signal S3 transfers high level to, described the 5th transistor M5 conducting, and described the second sampling capacitance Cs2 samples and generates the second sampled signal described integrated signal;
Before described reset signal RST transfers high level to from low level for the second time, described the 3rd control signal S3 transfers low level to, described the 5th transistor M5 cut-off;
Before described reset signal RST transfers low level to from high level for the third time, described the 4th control signal S4 transfers high level to, and described the 6th transistor M6 conducting is also exported described the second sampled signal.
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