CN103475354A - Pull-up terminal resistor detecting circuit of high-speed interface - Google Patents
Pull-up terminal resistor detecting circuit of high-speed interface Download PDFInfo
- Publication number
- CN103475354A CN103475354A CN2013104099238A CN201310409923A CN103475354A CN 103475354 A CN103475354 A CN 103475354A CN 2013104099238 A CN2013104099238 A CN 2013104099238A CN 201310409923 A CN201310409923 A CN 201310409923A CN 103475354 A CN103475354 A CN 103475354A
- Authority
- CN
- China
- Prior art keywords
- terminal resistance
- detection signal
- inverter
- transistor
- speed interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a pull-up terminal resistor detecting circuit of a high-speed interface. The circuit is used for detecting a pull-up terminal resistor of the high-speed interface. The pull-up terminal resistor detecting circuit of the high-speed interface comprises a detection signal generating module and an input module, wherein the detection signal generating module is electrically connected with the pull-up terminal resistor and the input module and is controlled by an enable signal, and detection signals output by the detection signal generating module are input into the input module; when the pull-up terminal resistor works, the output signal of the input module is logic 1; when the pull-up terminal resistor is idle, the output signal of the input module is logic 0. According to the pull-up terminal resistor detecting circuit of the high-speed interface, the problem that sink currents are input into a local power supply by the high-speed interface when the local power supply is invalid is effectively solved, and a transistor is prevented from being damaged; load capacitance of the high-speed interface is minimum, and therefore normal working speed of the high-speed interface is guaranteed.
Description
Technical field
The present invention relates to the testing circuit technical field, particularly relate to high-speed interface on draw the terminal resistance testing circuit.
Background technology
Interconnect interface agreement between current device and equipment emerges in an endless stream, whether some protocol requirement source equipment can detect on high-speed interface in real time to drawing terminal resistance to exist on method, apparatus, whether generally adopt as shown in Figure 1 testing circuit figure to detect high-speed interface the other side exists and draws terminal resistance, circuit to comprise P-channel field-effect transistor (PEFT) transistor, N slot field-effect transistor and Schmidt trigger.P-channel field-effect transistor (PEFT) transistor source connecting interface, grid connects enable signal, and drain electrode connects the drain electrode of N slot field-effect transistor.N slot field-effect transistor source ground, grid connects input signal, and drain electrode is connected detection signal is passed to Schmidt trigger with the P-channel field-effect transistor (PEFT) transistor drain.
Due to when preventing that local power supply is invalid, the anti-filling electricity of interface end to local power supply, the transistorized substrate electric potential of transistor P-channel field-effect transistor (PEFT) must connect together with interface, and whole like this capacitance to substrate has become the load capacitance of interface, affects the speed of high-speed interface normal operation.If the ceiling voltage of interface end is higher than the highest withstand voltage of transistorized any two ports of P-channel field-effect transistor (PEFT), the P-channel field-effect transistor (PEFT) transistor will damage under in working order.
Summary of the invention
Based on this, be necessary for above drawing the terminal resistance testing circuit to affect the problem of high-speed interface operating rate, provide a kind of high-speed interface on draw the terminal resistance testing circuit.For realizing above-mentioned target, the invention provides following technical scheme:
Draw the terminal resistance testing circuit on a kind of high-speed interface, for to drawing the detection of terminal resistance on high-speed interface, draw the terminal resistance testing circuit to comprise detection signal generation module and input module on described;
Described detection signal generation module respectively with described on draw terminal resistance and described input module to be electrically connected to;
Described detection signal generation module is controlled by enable signal, and the detection signal of described detection signal generation module output inputs to described input module;
While drawing terminal resistance in running order on described, the output signal of described input module is logical one; While drawing terminal resistance in idle state on described, the output signal of described input module is logical zero.
More preferably, described detection signal generation module comprises the first transistor and transistor seconds;
Described enable signal comprises bias voltage and input signal;
The grid of described the first transistor is coupled to described input signal, the source ground of described the first transistor;
The grid of described transistor seconds is coupled to described biased electrical pressure side, the drain coupled of described transistor seconds is drawn terminal resistance on described, the source-coupled of described transistor seconds is to the drain electrode of described the first transistor, the source electrode of described transistor seconds also is coupled to described input module, for exporting described detection signal;
The substrate of described transistor seconds and the substrate of described the first transistor connect rear ground connection altogether.
More preferably, described input module comprises the first inverter and the second inverter;
The input of described the first inverter is coupled to the source electrode of described transistor seconds, the input coupling of output and described the second inverter, and the output of described the second inverter is exported described output signal.
More preferably, described the first inverter and described the second inverter form by the CMOS transistor;
The voltage that any two ports of described the first inverter can bear is greater than the voltage of described detection signal.
More preferably, the voltage that any two ports of described the second inverter can bear is less than any two voltages that port can bear of described the first inverter.
More preferably, when described detection signal generation module is high level with the interface that above draws terminal resistance to be connected, the voltage of described detection signal is greater than the turn threshold voltage of described the first inverter and is less than described detection signal generation module and the interface voltage that above draws terminal resistance to be connected;
When described detection signal generation module is low level with the interface that above draws terminal resistance to be connected, the voltage of described detection signal is less than the turn threshold voltage of described the first inverter.
More preferably, the supply voltage of described input module is lower than the voltage of described detection signal.
More preferably, described the first transistor and described transistor seconds are enhancement mode NMOS pipe.
The invention has the beneficial effects as follows:
Draw the terminal resistance testing circuit on high-speed interface of the present invention, efficiently solve when local power supply is invalid, the anti-filling electric problem of high-speed interface to local power supply makes transistor not damaged simultaneously; In the load capacitance minimum of high-speed interface introducing, guaranteed the normal operation speed of high-speed interface.
The accompanying drawing explanation
Fig. 1 be prior art on draw terminal resistance testing circuit schematic diagram;
Fig. 2 be high-speed interface of the present invention on draw the schematic diagram of terminal resistance testing circuit one embodiment.
Embodiment
In order to make technical scheme of the present invention clearer, below in conjunction with accompanying drawing, to drawing the terminal resistance testing circuit on high-speed interface of the present invention, be described in further detail.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
As shown in Figure 2, draw terminal resistance testing circuit one embodiment on a kind of high-speed interface, for to drawing the detection of terminal resistance on high-speed interface;
On draw the terminal resistance testing circuit to comprise detection signal generation module and input module, the detection signal generation module respectively with on draw terminal resistance and described input module to be electrically connected to, the detection signal generation module is controlled by enable signal, and the detection signal of detection signal generation module output inputs to described input module; When on while drawing terminal resistance in running order, the output signal of described input module is logical one; When on while drawing terminal resistance in idle state, the output signal of described input module is logical zero.
More preferably, as a kind of embodiment, the detection signal generation module comprises the first transistor M1 and transistor seconds M2, and described enable signal comprises bias voltage and input signal; Preferably, the first transistor M1 and transistor seconds M2 are enhancement mode NMOS pipe.
The grid of the first transistor M1 is coupled to described input signal, the source ground of the first transistor M1, the grid of transistor seconds M2 is coupled to described biased electrical pressure side, the drain electrode of transistor seconds M2 is by the supreme terminal resistance that draws of the interface coupling in Fig. 2, the source-coupled of transistor seconds M2 is to the drain electrode of the first transistor M1, the source electrode of transistor seconds M2 also is coupled to input module, for exporting described detection signal, the substrate of the substrate of transistor seconds M2 and the first transistor M1 connects rear ground connection altogether.The supreme terminal resistance that draws of the drain coupled of transistor seconds M2, in the load capacitance minimum of interface introducing, guaranteed the normal operation speed of high-speed interface; The substrate of the substrate of the first transistor M1 and transistor seconds M2 connects rear ground connection altogether, has solved when local power supply is invalid the anti-filling electric problem of interface end to local power supply.
Input module comprises the first inverter and the second inverter;
The input of the first inverter is coupled to the source electrode of transistor seconds M2, the input coupling of output and the second inverter, and the output of the second inverter is exported described output signal.
Preferably, the first inverter and the second inverter form by the CMOS transistor; The voltage that any two ports of the first inverter can bear is greater than the voltage of described detection signal; Make when detection signal is input to the first inverter, the CMOS pipe of the first inverter is not damaged.Further, the voltage that any two ports of the second inverter can bear is less than any two voltages that port can bear of the first inverter, makes in the situation that guarantee circuit normal operation, and the designing requirement of the second inverter reduces, thereby cost-saving.
When on while drawing terminal resistance in running order, the voltage of described detection signal is greater than the turn threshold voltage of the first inverter and is less than detection signal generation module and the interface voltage that above draws terminal resistance to be connected; When on while drawing terminal resistance in idle state, the voltage of described detection signal is less than the turn threshold voltage of the first inverter.Preferably, the supply voltage Vdd of input module is lower than the voltage of described detection signal.
The supply voltage Vdd of input module is the supply voltage Vdd of the first inverter and the second inverter, the supply voltage Vdd of the first inverter and the second inverter is low-tension supply, the maximum amplitude of oscillation that makes described output signal is Vdd, and in prior art, the supply voltage VCC of Schmidt trigger is high voltage source, the maximum amplitude of oscillation of output signal is VCC, so the present invention has saved the level shifting circuit of high voltage to low-voltage in output signal with respect to prior art to the transmission path of system.
Below illustrate above embodiment on draw the terminal resistance testing circuit course of work:
For example, the first transistor M1, transistor seconds M2 and the highest withstand voltage that forms transistorized any two ports of CMOS of the first inverter are 3.3V, during this circuit working, input signal is constant is high level 3.3V, bias voltage is set to high level 3.3V, the first transistor M1 and the equal conducting of transistor seconds M2; When interface end by above drawing terminal resistance to be connected to the 3.3V voltage source or when interface end exists high level to be 3.3V, the low level single-ended amplitude of oscillation signal that is about 2.7V, size (such as the conducting resistance by the first transistor M1 designs very greatly) by rational design the first transistor M1 and transistor seconds M2, can guarantee that detection signal is output as lower than 3.3V but is greater than some level of the first inverter turn threshold, the second inverter output signal is logical one; When interface end not by while drawing terminal resistance to be connected to the 3.3V voltage source, detection signal is bound to be pulled down to and approach 0 level because of the conducting of the first transistor M1, the output signal of the second inverter is logical zero.
If the first transistor M1 and transistor seconds M2 and the highest withstand voltage that forms transistorized any two ports of CMOS of the first inverter are 1.8V, when this circuit working, input signal is constant is high level 1.8V, bias voltage is set to a level higher than 1.8V (such as the 2.5V left and right), the first transistor M1 and the equal conducting of transistor seconds M2; When interface end by above drawing terminal resistance to be connected to the 3.3V voltage source or when interface end exists high level to be 3.3V, the low level single-ended amplitude of oscillation signal that is about 2.7V, size (such as the conducting resistance by the first field-effect transistor NMOS0 designs very greatly) by rational design the first transistor M1 and transistor seconds M2, can guarantee that detection signal is output as lower than 1.8V but is greater than some level of the first inverter turn threshold, the output signal of the second inverter is logical one.When interface end not by while drawing terminal resistance to be connected to the 3.3V voltage source, detection signal is bound to be pulled down to and approach 0 level because of the conducting of the first transistor M1, output signal is logical zero.
If interface voltage is higher than the CMOS the highest transistorized withstand voltage in the first inverter or the second inverter, can change detection signal by the size that transistor seconds M2 gate bias voltage is set, prevent that the first inverter and the second inverter from damaging because voltage is excessive.
More preferably, as a kind of embodiment, when interface end by while drawing terminal resistance to be connected to 5V voltage source or 3.3V voltage source, by the size (such as the conduction resistance value by transistor NMOS1 and NMOS0 designs very littlely) of rational design the first transistor M1 and transistor seconds M2, this circuit also can be realized the imput output circuit function.When input signal is logical one, form the very strong pull down resistor of driving force, interface level and detection signal can be pulled down to and approach 0V, and output signal is logical zero; When input signal is logical zero, the first transistor M1 closes, and interface level is pulled to 5V or 3.3V, and detection signal is output as lower than 3.3V but is greater than some level of inverter turn threshold, and output signal is logical one.
While on interface connects, drawing terminal resistance, the long-term conducting power supply of the first transistor M1 and transistor seconds M2, the mode of the long-term conducting of transistor increases energy consumption; Can control by system the break-make of the first transistor M1 and transistor seconds M2, for example, after system detects the information that the output signal of the second inverter is logical one, bias voltage and/or output signal can be pulled to 0 level, transistor seconds M2 and/or the first transistor M1 close, while on to be detected, drawing terminal resistance, again bias voltage and output signal are pulled to high level, thereby reduce the consumption of the energy.
When interface exists high level to be the single-ended amplitude of oscillation signal about 3.3V, low level are 2.7V, detection signal is higher than VDD/2, such the first inverter just has the function of the trap signal level shake that Schmidt trigger is equal to, but circuit area is less than Schmidt trigger.
Draw the terminal resistance testing circuit on high-speed interface in above embodiment, the direct ground connection of the substrate of transistor seconds M2, efficiently solve when local power supply is invalid, and the anti-filling electric problem of interface end to local power supply guarantees that transistor seconds M2 is not damaged simultaneously.High-speed interface only is connected with the drain electrode of transistor seconds M2, in the load capacitance minimum of high-speed interface introducing, has guaranteed the normal operation speed of high-speed interface.
That by the conducting resistance by the first transistor M1, designs is very large, guaranteed that high-speed interface is when existing high level to be the single-ended amplitude of oscillation signal about 3.3V, low level are 2.7V, detection signal all the time far above Vdd/2 even higher than Vdd, such the first inverter just has the function of the trap signal level shake that Schmidt trigger is equal to, and circuit area is less than Schmidt trigger.
The supply voltage Vdd of the first inverter and the second inverter is low-tension supply, the maximum amplitude of oscillation that makes the second inverter output signal is Vdd, and in prior art, the supply voltage VCC of Schmidt trigger is high voltage source, the maximum amplitude of oscillation of output signal is VCC, so the present invention has saved the level shifting circuit of high voltage to low-voltage in output signal with respect to prior art to the transmission path of system.
If the ceiling voltage of high-speed interface (as 3.3V), higher than the highest withstand voltage (as 1.8V) of any two ports of transistor CMOS, by the appropriate design bias voltage, can guarantee that the CMOS transistor can not damage.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (8)
- A high-speed interface on draw the terminal resistance testing circuit, for to drawing the detection of terminal resistance on high-speed interface, it is characterized in that:On described, draw the terminal resistance testing circuit to comprise detection signal generation module and input module;Described detection signal generation module respectively with described on draw terminal resistance and described input module to be electrically connected to;Described detection signal generation module is controlled by enable signal, and the detection signal of described detection signal generation module output inputs to described input module;While drawing terminal resistance in running order on described, the output signal of described input module is logical one; While drawing terminal resistance in idle state on described, the output signal of described input module is logical zero.
- High-speed interface according to claim 1 on draw the terminal resistance testing circuit, it is characterized in that:Described detection signal generation module comprises the first transistor M1 and transistor seconds M2;Described enable signal comprises bias voltage and input signal;The grid of described the first transistor M1 is coupled to described input signal, the source ground of described the first transistor M1;The grid of described transistor seconds M2 is coupled to described biased electrical pressure side, the drain coupled of described transistor seconds M2 is drawn terminal resistance on described, the source-coupled of described transistor seconds M2 is to the drain electrode of described the first transistor M1, the source electrode of described transistor seconds M2 also is coupled to described input module, for exporting described detection signal;The substrate of the substrate of described transistor seconds M2 and described the first transistor M1 connects rear ground connection altogether.
- High-speed interface according to claim 2 on draw the terminal resistance testing circuit, it is characterized in that:Described input module comprises the first inverter and the second inverter;The input of described the first inverter is coupled to the source electrode of described transistor seconds, the input coupling of output and described the second inverter, and the output of described the second inverter is exported described output signal.
- High-speed interface according to claim 3 on draw the terminal resistance testing circuit, it is characterized in that:Described the first inverter and described the second inverter form by the CMOS transistor;The voltage that any two ports of described the first inverter can bear is greater than the voltage of described detection signal.
- High-speed interface according to claim 4 on draw the terminal resistance testing circuit, it is characterized in that:The voltage that any two ports of described the second inverter can bear is less than any two voltages that port can bear of described the first inverter.
- High-speed interface according to claim 3 on draw the terminal resistance testing circuit, it is characterized in that:When described detection signal generation module is high level with the interface that above draws terminal resistance to be connected, the voltage of described detection signal is greater than the turn threshold voltage of described the first inverter and is less than described detection signal generation module and the interface voltage that above draws terminal resistance to be connected;When described detection signal generation module is low level with the interface that above draws terminal resistance to be connected, the voltage of described detection signal is less than the turn threshold voltage of described the first inverter.
- High-speed interface according to claim 6 on draw the terminal resistance testing circuit, it is characterized in that:The supply voltage of described input module is lower than the voltage of described detection signal.
- 8. according on the described high-speed interface of claim 1-7 any one, drawing the terminal resistance testing circuit, it is characterized in that:Described the first transistor M1 and described transistor seconds M2 are enhancement mode NMOS pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310409923.8A CN103475354B (en) | 2013-09-10 | 2013-09-10 | The pull-up terminal resistance testing circuit of high-speed interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310409923.8A CN103475354B (en) | 2013-09-10 | 2013-09-10 | The pull-up terminal resistance testing circuit of high-speed interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103475354A true CN103475354A (en) | 2013-12-25 |
| CN103475354B CN103475354B (en) | 2016-06-22 |
Family
ID=49800082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310409923.8A Active CN103475354B (en) | 2013-09-10 | 2013-09-10 | The pull-up terminal resistance testing circuit of high-speed interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103475354B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117013996A (en) * | 2023-09-27 | 2023-11-07 | 江苏帝奥微电子股份有限公司 | IO switching circuit for high-speed interface transmission system and control method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06318852A (en) * | 1993-05-07 | 1994-11-15 | Toshiba Corp | Semiconductor integrated circuit device |
| CN101795132A (en) * | 2010-04-02 | 2010-08-04 | 日银Imp微电子有限公司 | Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit |
| CN102636676A (en) * | 2011-02-12 | 2012-08-15 | 中兴通讯股份有限公司 | Bridge-type current detecting circuit |
| CN103051325A (en) * | 2012-12-10 | 2013-04-17 | 珠海全志科技股份有限公司 | Pull-up resistance circuit for preventing reverse current filling |
-
2013
- 2013-09-10 CN CN201310409923.8A patent/CN103475354B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06318852A (en) * | 1993-05-07 | 1994-11-15 | Toshiba Corp | Semiconductor integrated circuit device |
| CN101795132A (en) * | 2010-04-02 | 2010-08-04 | 日银Imp微电子有限公司 | Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit |
| CN102636676A (en) * | 2011-02-12 | 2012-08-15 | 中兴通讯股份有限公司 | Bridge-type current detecting circuit |
| CN103051325A (en) * | 2012-12-10 | 2013-04-17 | 珠海全志科技股份有限公司 | Pull-up resistance circuit for preventing reverse current filling |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117013996A (en) * | 2023-09-27 | 2023-11-07 | 江苏帝奥微电子股份有限公司 | IO switching circuit for high-speed interface transmission system and control method thereof |
| CN117013996B (en) * | 2023-09-27 | 2023-12-01 | 江苏帝奥微电子股份有限公司 | IO switching circuit for high-speed interface transmission system and control method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103475354B (en) | 2016-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102655409B (en) | Two-stage rear-end driver | |
| CN203481783U (en) | Short circuit and overcurrent protection circuit and mass production test equipment | |
| CN101860188B (en) | Switch power supply circuit | |
| CN203537358U (en) | One-key switching circuit | |
| CN103490374A (en) | Mass production test device and short-circuit current foldback circuit thereof | |
| CN108322034A (en) | A kind of soft starting device and method of Switching Power Supply | |
| CN107181482A (en) | input and output receiving circuit | |
| CN103217615B (en) | Output short-circuit detection circuit | |
| CN103018588B (en) | Low-power-consumption anti-interference three-state input detection circuit | |
| CN103051325B (en) | Pull-up resistance circuit for preventing reverse current filling | |
| CN204425299U (en) | Power on/off detects reset circuit | |
| CN103746681A (en) | Power-on/power-down output tri-state control circuit for CMOS device power supply | |
| CN104270138B (en) | Input/output buffer of multiple voltage domains | |
| CN104883172A (en) | Analog switch circuit structure | |
| CN110308759A (en) | A kind of novel level shifter circuit | |
| CN103475354A (en) | Pull-up terminal resistor detecting circuit of high-speed interface | |
| CN208608973U (en) | A kind of current foldback circuit | |
| CN208797824U (en) | Output driving circuit and chip | |
| CN109104182A (en) | A kind of quick low-power consumption single ended interfaces | |
| CN106059553B (en) | Device for realizing Ra resistance in USB Type-C EMCA cable | |
| CN103795396A (en) | Circuit structure for eliminating short circuit currents | |
| CN109149913A (en) | Metal-oxide-semiconductor driving circuit | |
| CN205071002U (en) | Light module power supply circuit and communications facilities | |
| CN106774795A (en) | Mobile terminal and its power-supply management system | |
| CN209267548U (en) | A kind of quick low-power consumption single ended interfaces |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |