CN103474028B - 一种像素电路、驱动电路、阵列基板及显示设备 - Google Patents

一种像素电路、驱动电路、阵列基板及显示设备 Download PDF

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CN103474028B
CN103474028B CN201310407319.1A CN201310407319A CN103474028B CN 103474028 B CN103474028 B CN 103474028B CN 201310407319 A CN201310407319 A CN 201310407319A CN 103474028 B CN103474028 B CN 103474028B
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input end
film transistor
tft
thin film
preliminary filling
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CN103474028A (zh
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段立业
王俪蓉
吴仲远
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BOE Technology Group Co Ltd
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明实施例提供一种像素电路、驱动电路、阵列基板及显示设备，涉及有机发光二极管显示技术，通过在发光工作电压输入端输入与预充控制电压同步反向的信号，使像素电路进入发光阶段时，由发光工作电压为电路提供电压，保证电路在发光阶段的电流的稳定输出，并且不需要设置影响开口率的外接电压输入端，从而在保证电流驱动电路的电流的稳定输出的同时增大了使用电流驱动像素电路的OLED的开口率，进而增大了使用电流驱动像素电路的OLED的使用寿命。

Description

一种像素电路、驱动电路、阵列基板及显示设备
技术领域
本发明涉及有机发光显示技术，尤其涉及一种像素电路、驱动电路、阵列基板及显示设备。
背景技术
有机发光显示器（Organic Light Emitting Display，OLED）像素电路驱动方式可分为电流驱动和电压驱动，图1为电压驱动像素电路，图2为电流驱动像素电路。在电压驱动像素电路中，输出电流IOLED公式为： I OLED = 1 2 μ n · Cox · W L · ( Vdata - Voled - Vth ) 2 , 其中μn为载流子迁移率，COX为栅氧化层电容，W/L为晶体管宽长比，Vdata为数据电压，Voled为所有像素单元共享的OLED发光工作电压，Vth为晶体管的阈值电压，对于增强型TFT，Vth为正值，对于耗尽型TFT，Vth为负值。由此可知，如果一个像素的Vth随时间发生变化，则会造成该像素不同时间的输出电流IOLED不同，会出现残影现象，也就不能保证液晶显示器在时间上的稳定显示。电流驱动相比电压驱动的优点为输出电流IOLED始终与输入电流Idata相等，电流驱动像素电路中，即使像素的阈值电压Vth随着时间发生变化，电流驱动像素电路也能够自主调整，保证输出电流IOLED始终与输入电流Idata相等，从而实现液晶显示器在空间上均匀显示和时间上稳定的显示。这是由于电流驱动像素电路的工作过程通常可以分为两个阶段，第一阶段为预充阶段，第二阶段为发光阶段。在预充阶段，输出电流IOLED与输入电流Idata相等，同时电流驱动像素电路中的电容储存电荷，在发光阶段，由于电流驱动电路中的电容存储了电荷，因此可以保证电流驱动电路中的输出电流IOLED依然与预充阶段的输出电流IOLED相等，即依然与预充阶段的输入电流Idata相等。一种具体的电流驱动像素电路如图3所示，电路中存在一条用于在发光阶段为电路提供电压的外接控制电压Vctrl输入端，连接在一个薄膜晶体管的栅极处，而该电路的工作电压VDD输入端连接在该薄膜晶体管的源漏两极中的一极处，该电路的仿真图如图4所示，外接控制电压Vctrl输入端输入与用于在预充阶段为电路提供电压的预充控制电压Vselect输入端输入的信号同步反向信号，实现在预充阶段由预充控制电压Vselect为驱动电路提供电压，在发光阶段由外接控制电压Vctrl及工作电压VDD通过其连接的薄膜晶体管合成的电压为电路提供电压，保证电流驱动电路在发光阶段存在输出电流IOLED。然而，外接的Vctrl输入端的存在会减小各像素的开口率，而像素的开口率越小，OLED的使用寿命就会越短。
发明内容
本发明实施例提供一种像素电路、驱动电路、阵列基板及显示设备，以增大使用电流驱动像素电路的OLED的使用寿命。
一种像素电路，包括：
第一薄膜晶体管，栅极连接预充控制电压输入端及电流输入端，漏极连接预充控制电压输入端、电流输入端及发光工作电压输入端，发光工作电压输入端用于输入与预充控制电压同步反向的信号；
电容，两端分别连接于第一薄膜晶体管的源极和栅极；
有机发光二极管，正极连接第一薄膜晶体管的漏极，负极连接接地电压输入端。
一种驱动电路，由多个本发明实施例提供的像素电路组成，多个本发明实施例提供的像素电路构成矩阵；
多个本发明实施例提供的像素电路中位于矩阵中同一行的像素电路，连接同一个发光工作电压输入端，连接同一个预充控制电压输入端；
多个本发明实施例提供的像素电路中位于矩阵中同一列的像素电路，连接同一个电流输入端。
一种阵列基板，包括本发明实施例提供的驱动电路。
一种显示设备，包括本发明实施例提供的驱动电路。
本发明实施例提供一种像素电路、驱动电路、阵列基板及显示设备，通过在发光工作电压输入端输入与预充控制电压同步反向的信号，使像素电路进入发光阶段时，由发光工作电压为电路提供电压，保证电路在发光阶段的电流的稳定输出，且无需设置会减小开口率的外接电压输入端，从而在保证电流驱动电路的电流的稳定输出的同时增大了使用电流驱动像素电路的OLED的开口率，进而增大了使用电流驱动像素电路的OLED的使用寿命。
附图说明
图1为现有技术提供的一种电压驱动像素电路图；
图2为现有技术提供的一种电流驱动像素电路图；
图3为现有技术提供的一种较佳的电流驱动像素电路图；
图4为现有技术提供的较佳的电流驱动像素电路的仿真图；
图5为本发明实施例提供的像素电路图之一；
图6为本发明实施例提供的像素电路图之二；
图7为本发明实施例提供的像素电路图之三；
图8为本发明实施例提供的像素电路图之四；
图9为本发明实施例提供的像素电路图之五；
图10为本发明实施例提供的一种驱动电路图；
图11为本发明实施例提供的一种较佳的驱动电路图；
图12为本发明实施例提供的输入电压仿真图；
图13为本发明实施例提供驱动电路预充阶段电路示意图；
图14为本发明实施例提供的驱动电路发光阶段电路示意图；
图15为本发明实施例提供的驱动电路仿真图。
具体实施方式
本发明实施例提供一种像素电路、驱动电路、阵列基板及显示设备，通过在发光工作电压输入端输入与预充控制电压Vselect同步反向的信号，使像素电路进入发光阶段时，由发光工作电压为电路提供电压，保证电路在发光阶段的电流的稳定输出，且无需设置会减小开口率的外接电压输入端，从而在保证电流驱动电路的电流的稳定输出的同时增大了使用电流驱动像素电路的OLED的开口率，进而增大了使用电流驱动像素电路的OLED的使用寿命。
如图5所示，本发明实施例提供一种像素电路，包括：
第一薄膜晶体管501，栅极连接预充控制电压Vselect输入端及电流输入端，漏极连接预充控制电压Vselect输入端、电流输入端及发光工作电压Vdd输入端，发光工作电压Vdd输入端用于输入与预充控制电压Vselect同步反向的信号；
电容502，两端分别连接于第一薄膜晶体管501的源极和栅极；
有机发光二级管503，正极连接第一薄膜晶体管501的漏极，负极连接接地电压Vss输入端。
发光工作电压Vdd输入端输入与预充控制电压Vselect同步反向的信号，因此，在预充阶段，由预充控制电压Vselect输入端输入的信号提供电路的电压，在发光阶段，由发光工作电压Vdd输入的信号提供电压，从而保证了在发光阶段电路存在电流输出。而电容502保证了在发光阶段输出的电流与预充阶段相同，电路中不存在影响开口率的外接信号端，从而增大了使用电流驱动像素电路的OLED的开口率，进而增大了使用电流驱动像素电路的OLED的使用寿命。
实际应用中，由于当同一行相邻像素的电流输入端输入的电流不同时，会导致相邻像素的第一薄膜晶体管501的漏极电压不相同，容易导致漏极电压较高的像素的驱动电路中电流方向与正常工作需要的电流方向相反，影响OLED的正常显示，因此，为了避免各像素中驱动电路中的电流方向与正常工作需要的电流方向相反，可以令像素电路的第一薄膜晶体管501的漏极通过二极管与发光工作电压Vdd输入端相连，保证驱动电路发光阶段时的电流是由有驱动电压输入端流向第一薄膜晶体管501的漏极。
较佳的，为了方便OLED的制作，连接第一薄膜晶体管501的漏极和发光工作电压Vdd输入端的二极管可以替换为薄膜晶体管，具体的，如图6所示，第一薄膜晶体管501的漏极通过第二薄膜晶体管504与发光工作电压Vdd输入端相连；
第一薄膜晶体管501的漏极可以通过第二薄膜晶管504与发光工作电压VDD输入端相连，第二薄膜晶体管504的栅极及源漏两极中的一极与发光工作电压VDD输入端相连，源漏两极中的另一极与第一薄膜晶体管501的漏极相连。
图6中的第二薄膜晶体管504可以看做一个正极连接发光工作电压Vdd输入端，负极连接第一薄膜晶体管501的漏极的二极管，从而保证驱动电路中电流的方向是由发光工作电压Vdd输入端流向第一薄膜晶体管501的漏极。
当然，本领域的技术人员也可以采用其他可行方式避免由于同一行相邻像素的电流输入端输入的电流不同，而影响OLED的正常显示，此处仅提供一种较佳的实现方式，不再一一叙述。
进一步，若各像素的驱动电路需要逐行进行驱动，即在前一行完成预充后才能对下一行进行预充，本发明实施例还提供一种较佳的实现逐行驱动的方式。即可以令第一薄膜晶体管501的栅极和/或漏极通过作为开关的薄膜晶体管与预充控制电压Vselect输入端及电流输入端相连，作为开关的薄膜晶体管在高电平时打开，在低电平时关闭，从而通过各行像素电路的预充控制电压Vselect输入端输入不同的信号，实现逐行驱动。
具体的，可以令第一薄膜晶体管501的栅极通过作为开关的薄膜晶体管与预充控制电压Vselect输入端及电流输入端相连，如图7所示，第一薄膜晶体管501的栅极通过作为开关的薄膜晶体管与预充控制电压Vselect输入端及电流输入端相连，具体为：
第一薄膜晶体管501的栅极通过第三薄膜晶体管505与预充控制电压Vselect输入端及电流输入端相连，第三薄膜晶体管505的栅极与预充控制电压Vselect输入端相连，源漏两极中的一极与第一薄膜晶体管501的栅极相连，源漏两极中的另一极与电流输入端相连；
进一步，可以令第一薄膜晶体管501的漏极也通过作为开关的薄膜晶体管与预充控制电压Vselect输入端及电流输入端相连，如图8所示，第一薄膜晶体管501的漏极通过作为开关的薄膜晶体管与预充控制电压Vselect输入端及电流输入端相连，具体为：
第一薄膜晶体管的漏极通过第四薄膜晶体管506与预充控制电压Vselect输入端及电流输入端相连，第四薄膜晶体管506的栅极与预充控制电压Vselect输入端相连，源漏两极中的一极与第一薄膜晶体管501的漏极相连，源漏两极中的另一极与电流输入端相连。
当然，本领域的技术人员也可以采用其他可行方式实现驱动各像素电路的逐行驱动，此处仅提供一种较佳的实现方式，不再一一叙述。
如图9所示，本发明实施例提供一种较佳的像素电路，包括：
第一薄膜晶体管501，第二薄膜晶体管504，第三薄膜晶体管505，第四薄膜晶体管506，还包括电容502和有机发光二极管503。
其中，电容502的两端分别连接于第一薄膜晶体管501的源极和栅极；
有机发光二极管503的正极连接第一薄膜晶体管501的漏极，负极连接接地电压Vss输入端；
第二薄膜晶体管504的栅极及源漏两极中的一极与发光工作电压Vdd输入端相连，源漏两极中的另一极与第一薄膜晶体管501的漏极相连。
第三薄膜晶体管505的栅极与预充控制电压Vselect输入端相连，源漏两极中的一极与第一薄膜晶体管501的栅极相连，源漏两极中的另一极与电流输入端相连；
第四薄膜晶体管506的栅极与预充控制电压Vselect输入端相连，源漏两极中的一极与第一薄膜晶体管501的漏极相连，源漏两极中的另一极与电流输入端相连。
其中，发光工作电压Vdd输入端输入的是与预充控制电压Vselect同步反向的信号，当像素电路进入预充阶段时，由预充控制电压Vselect为电路提供电压，当像素电路进入发光阶段时，由发光工作电压Vdd为电路提供电压，保证电路在预充阶段和发光阶段的电流输出，并且没有影响开口率的外接电压输入端，从而增大了使用电流驱动像素电路的OLED的开口率，进而增大了使用电流驱动像素电路的OLED的使用寿命。第二薄膜晶体管504可以看做一个正极连接发光工作电压Vdd输入端，负极连接第一薄膜晶体管501的漏极的二极管，从而保证驱动电路中电流的方向是由发光工作电压Vdd输入端流向第一薄膜晶体管501的漏极，第三薄膜晶体管505与第四薄膜晶体管506为作为开关的薄膜晶体管，第三薄膜晶体管505与第四薄膜晶体管506在高电平时打开，在低电平时关闭，从而通过各行像素电路的预充控制电压Vselect输入端输入不同的信号，实现逐行驱动。
本发明实施例还提供一种驱动电路，该驱动电路为由多个本发明实施例提供的像素电路组成，多个本发明实施例提供的像素电路构成矩阵；
多个本发明实施例提供的像素电路中位于矩阵中同一行的像素电路，连接同一个发光工作电压输入端，连接同一个预充控制电压输入端；
多个本发明实施例提供的像素电路中位于矩阵中同一列的像素电路，连接同一个电流输入端。
较佳的，如图10所示，多个本发明实施例提供的像素电路中位于矩阵中第一列的像素电路中包括第五薄膜晶体管507；
第五薄膜晶体管507的源漏两极分别连接发光工作电压Vdd输入端及工作电压VDD输入端，栅极连接信号输入端Input，信号输入端Input用于输入与预充控制电压Vselect同步反向的信号，第五薄膜晶体管507为N型薄膜晶体管。
在多个本发明实施例提供的像素电路中位于矩阵中第一列的像素电路中设置第五薄膜晶体管507，通过在第五薄膜晶体管507的栅极输入与预充控制电压Vselect同步反向的信号，在源漏两极分别连接发光工作电压Vdd输入端及工作电压VDD输入端，则，第五薄膜晶体管507源漏两极中连接发光工作电压Vdd输入端的一极输出信号即为发光工作电压Vdd输入端向各像素电路输入的信号。在工作电压VDD输入端和预充控制电压Vselect输入端输入信号后，第五薄膜晶体管507源漏两极中连接发光工作电压Vdd输入端的一极输出信号是与预充控制电压Vselect同步反向的信号，从而保证发光工作电压Vdd输入端向各像素电路输入的是与预充控制电压Vselect同步反向的信号。
当然，本领域的技术人员可以采用其他可行的方式保证发光工作电压Vdd输入端向各像素电路输入的是与预充控制电压Vselect同步反向的信号，此处仅提供一种较佳的实现方式，不再一一叙述。
如图11所示，本发明实施例提供一种较佳的驱动电路，该驱动电路为由多个像素电路组成，多个像素电路构成矩阵；
其中，像素电路包括：
第一薄膜晶体管501，第二薄膜晶体管504，第三薄膜晶体管505，第四薄膜晶体管506，第五薄膜晶体管507，还包括电容502和有机发光二极管503。
其中，电容502的两端分别连接于第一薄膜晶体管501的源极和栅极；
第一薄膜晶体管501，第二薄膜晶体管504，第三薄膜晶体管505，第四薄膜晶体管506，第五薄膜晶体管507，还包括电容502和有机发光二极管503。
其中，电容502的两端分别连接于第一薄膜晶体管501的源极和栅极；
有机发光二极管503的正极连接第一薄膜晶体管501的漏极，负极连接接地电压Vss输入端；
第二薄膜晶体管504的栅极及源漏两极中的一极与发光工作电压Vdd输入端相连，源漏两极中的另一极与第一薄膜晶体管501的漏极相连。
第三薄膜晶体管505的栅极与预充控制电压Vselect输入端相连，源漏两极中的一极与第一薄膜晶体管501的栅极相连，源漏两极中的另一极与电流输入端相连；
第四薄膜晶体管506的栅极与预充控制电压Vselect输入端相连，源漏两极中的一极与第一薄膜晶体管501的漏极相连，源漏两极中的另一极与电流输入端相连。
多个像素电路中位于矩阵中第一列的像素电路的第五薄膜晶体管507的源漏两极分别连接发光工作电压Vdd输入端及工作电压VDD输入端。栅极连接信号输入端Input，信号输入端Input用于输入与预充控制电压Vselect同步反向的信号，第五薄膜晶体管507为N型薄膜晶体管。较佳的，如图12所示，可以令工作电压VDD输入端输入的信号也与预充控制电压Vselect控制端输入的信号相反。
多个像素电路中位于矩阵中同一行的像素电路，连接同一个发光工作电压输入端，连接同一个预充控制电压输入端；
多个像素电路中位于矩阵中同一列的像素电路，连接同一个电流输入端。
下面具体介绍图11所示驱动电路的工作原理。如图13所示，在预充阶段，预充控制电压Vselect为高电平，发光工作电压Vdd为低电平，此时第五薄膜晶体管507和第二薄膜晶体管504关闭，第三薄膜晶体管505和第四薄膜晶体管506打开，第一薄膜晶体管501的栅极（A点）和漏极（B点）电压相等，Vds>Vgs-Vth，其中Vds为源漏极电压，Vgs为源栅极电压。此时第一薄膜晶体管501处于饱和区，电流Idata通过第四薄膜晶体管506流入第一薄膜晶体管501，电容502储存电荷以维持第一薄膜晶体管501的源栅极电压Vgs，此时输出电流IOLED=Idata。
如图14所示，在发光阶段，预充控制电压Vselect为低电平，发光工作电压Vdd也为高电平，此时第三薄膜晶体管505和第四薄膜晶体管506关闭，第二薄膜晶体管504和第五薄膜晶体管507打开。第一薄膜晶体管501的漏极（B点）为高电平，第一薄膜晶体管501仍保持在饱和区，此时晶体管的输出电流将保持进入饱和区时的数值，因此发光阶段的输出电流IOLED依然为预充阶段的Idata，输出电流保持不变。
由此可知，图11所示的驱动电路的输出电流只跟输入电流有关，与阈值电压Vth无关，因此基本消除了阈值电压非均匀性对显示的影响，输出电流稳定，易于实现显示的高亮度和高分辨率。
图15为对图11所示的驱动电路的仿真结果，该仿真显示的是单个子像素工作的两个周期。在第一个周期中，把2uA的电流写入像素，第二个周期中把3uA的电流写入像素。从波形图可以明显看到，在对电路进行预充之后，像素的输出电流IOLED很好地跟随了输入电流Idata的变化。
本发明实施例还提供一种阵列基板，包括本发明实施例提供的驱动电路。
本发明实施例还提供一种显示设备，包括本发明实施例提供的驱动电路。
本发明实施例提供一种像素电路、驱动电路、阵列基板及显示设备，通过在发光工作电压Vdd输入端输入与预充控制电压Vselect同步反向的信号，使像素电路进入发光阶段时，由发光工作电压Vdd为电路提供电压，保证电路在发光阶段的电流输出，并且没有影响开口率的外接电压输入端，从而在保证电流驱动电路的电流的稳定输出的同时增大了使用电流驱动像素电路的OLED的开口率，进而增大了使用电流驱动像素电路的OLED的使用寿命。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

1.一种像素电路，其特征在于，包括：
第一薄膜晶体管，栅极连接预充控制电压输入端及电流输入端，漏极连接所述预充控制电压输入端、所述电流输入端及发光工作电压输入端，所述发光工作电压输入端用于输入与预充控制电压同步反向的信号；
电容，两端分别连接于所述第一薄膜晶体管的源极和栅极；
有机发光二级管，正极连接所述第一薄膜晶体管的源极，负极连接接地电压输入端。
2.如权利要求1所述的电路，其特征在于，所述第一薄膜晶体管的漏极通过二极管与所述发光工作电压输入端相连。
3.如权利要求1所述的电路，其特征在于，所述第一薄膜晶体管的漏极通过第二薄膜晶体管与所述发光工作电压输入端相连；
所述第二薄膜晶体管的栅极及源漏两极中的一极与所述发光工作电压输入端相连，源漏两极中的另一极与所述第一薄膜晶体管的漏极相连。
4.如权利要求1所述的电路，其特征在于，所述第一薄膜晶体管的栅极和/或漏极通过作为开关的薄膜晶体管与预充控制电压输入端及电流输入端相连。
5.如权利要求4所述的电路，其特征在于，所述第一薄膜晶体管的栅极和/或漏极通过作为开关的薄膜晶体管与预充控制电压输入端及电流输入端相连，具体为：
所述第一薄膜晶体管的栅极通过第三薄膜晶体管与所述预充控制电压输入端及所述电流输入端相连，所述第三薄膜晶体管的栅极与所述预充控制电压输入端相连，源漏两极中的一极与所述第一薄膜晶体管的栅极相连，源漏两极中的另一极与所述电流输入端相连；或者
所述第一薄膜晶体管的漏极通过第四薄膜晶体管与所述预充控制电压输入端及所述电流输入端相连，所述第四薄膜晶体管的栅极与所述预充控制电压输入端相连，源漏两极中的一极与所述第一薄膜晶体管的漏极相连，源漏两极中的另一极与所述电流输入端相连。
6.如权利要求4所述的电路，其特征在于，所述第一薄膜晶体管的栅极和/或漏极通过作为开关的薄膜晶体管与预充控制电压输入端及电流输入端相连，具体包括：
所述第一薄膜晶体管的栅极通过第三薄膜晶体管与所述预充控制电压输入端及所述电流输入端相连，所述第三薄膜晶体管的栅极与所述预充控制电压输入端相连，源漏两极中的一极与所述第一薄膜晶体管的栅极相连，源漏两极中的另一极与所述电流输入端相连；
所述第一薄膜晶体管的漏极通过第四薄膜晶体管与所述预充控制电压输入端及所述电流输入端相连，所述第四薄膜晶体管的栅极与所述预充控制电压输入端相连，源漏两极中的一极与所述第一薄膜晶体管的漏极相连，源漏两极中的另一极与所述电流输入端相连。
7.一种驱动电路，其特征在于，所述驱动电路由多个如权利要求1-6任一所述的像素电路组成，所述多个如权利要求1-6任一所述的像素电路构成矩阵；
所述多个如权利要求1-6任一所述的像素电路中位于所述矩阵中同一行的像素电路，连接同一个发光工作电压输入端，连接同一个预充控制电压输入端；
所述多个如权利要求1-6任一所述的像素电路中位于所述矩阵中同一列的像素电路，连接同一个电流输入端。
8.如权利要求7所述的驱动电路，其特征在于，所述多个如权利要求1-6任一所述的像素电路中位于所述矩阵中第一列的像素电路中包括第五薄膜晶体管；
所述第五薄膜晶体管的源漏两极分别连接所述发光工作电压输入端及工作电压输入端，栅极连接信号输入端，所述信号输入端用于输入与所述预充控制电压同步反向的信号，所述第五薄膜晶体管为N型薄膜晶体管。
9.一种阵列基板，其特征在于，包括如权利要求7或8所述的驱动电路。
10.一种显示设备，其特征在于，包括如权利要求7或8所述的驱动电路。
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