CN103472635B - Array substrate, manufacturing method of array substrate, and display device - Google Patents
Array substrate, manufacturing method of array substrate, and display device Download PDFInfo
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- CN103472635B CN103472635B CN201310401531.7A CN201310401531A CN103472635B CN 103472635 B CN103472635 B CN 103472635B CN 201310401531 A CN201310401531 A CN 201310401531A CN 103472635 B CN103472635 B CN 103472635B
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Abstract
The invention provides an array substrate. The array substrate comprises a plurality lines of grid lines and a plurality rows of data lines. The grid lines and the data lines cross to separate the array substrate into a plurality of pixel units. Each pixel unit comprises a thin film transistor, a pixel electrode and a public electrode corresponding to the pixel electrode. In each line of the pixel units, each public electrode is connected with the upper line of every two adjacent lines of grid lines limiting the line of the pixel units, and each pixel unit is connected with the lower line of every two adjacent lines of grid lines limiting the line of the pixel units. The invention further provides a display device with the array substrate and a manufacturing method the array substrate. The array substrate has the advantages that the public electrodes are connected with the grid lines and can be powered by the same, public electrode lines for powering the public electrodes are omitted, floor space of a wiring part on the array substrate can be lowered, and aperture ratio of the array substrate is increased.
Description
Technical field
The present invention relates to display technique field, particularly, relate to a kind of array base palte, comprise the manufacture method of the display device of described array base palte and described array base palte.
Background technology
The array base palte of display device comprises many public electrode wires, many grid lines and a plurality of data lines, these many grid lines and a plurality of data lines cross one another and described array base palte are divided into multiple pixel cell, thin film transistor (TFT), pixel electrode and the public electrode corresponding with this pixel electrode is provided with in each described pixel cell, public electrode wire is connected with public electrode, thinks that this public electrode is powered.
The aperture opening ratio of array base palte refers to remove the light after the wiring part (comprising grid line, data line and public electrode wire) of each pixel cell and thin film transistor (TFT) (usually adopting black matrix" to hide) by the ratio (that is, the ratio of effective transmission region and entire area) between the area of part and the area of each pixel entirety.Aperture opening ratio is higher, and the efficiency that light passes through is higher.
Day by day increase along with to the demand of high definition display device, the aperture opening ratio how improving pixel becomes this area technical matters urgently to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide a kind of array base palte, comprise the manufacture method of the display device of described array base palte and described array base palte, described array base palte has larger aperture opening ratio.
To achieve these goals, as one aspect of the present invention, a kind of array base palte is provided, described array base palte comprises multirow grid line and multi-column data line, described multirow grid line and multi-column data line cross one another and described array base palte are divided into multiple pixel cell, described pixel cell comprises thin film transistor (TFT), pixel electrode and the public electrode corresponding with described pixel electrode, wherein, often going in described pixel cell, described public electrode is connected with the lastrow in grid line described in the adjacent rows limiting this row pixel cell, described pixel electrode is connected with the next line in grid line described in the adjacent rows limiting this row pixel cell.
Preferably, the part of described public electrode and the overlap joint at least partially of grid line that is connected with described public electrode.
Preferably, described public electrode is positioned at the top of the grid line place layer be connected with described public electrode.
Preferably, described public electrode is positioned at the top of described pixel electrode and described grid line place layer, described public electrode by the first via hole and the grid line that is connected with described public electrode connected.
Preferably, described array base palte comprises gate insulation layer, the part that described gate insulation layer at least covers described grid line and described public electrode and is connected with described grid line.
As another aspect of the present invention, provide a kind of display device, described display device comprises array base palte, and wherein, described array base palte is above-mentioned array base palte provided by the present invention.
Preferably, described display device comprises gate drivers and source electrode driver, described grid line is electrically connected with described gate drivers, described data line is electrically connected with described source electrode driver, and the difference between the low level that described gate drivers provides and the level that described source electrode driver provides is between-4.5V to 4.5V.
As another aspect of the invention, a kind of manufacture method of array base palte is provided, described array base palte comprises multirow grid line and multi-column data line, described multirow grid line and multi-column data line cross one another and described array base palte are divided into multiple pixel cell, each described pixel cell comprises thin film transistor (TFT), pixel electrode and the public electrode corresponding with described pixel electrode, wherein, described manufacture method comprises:
Form the figure comprising grid line; With
Form the figure comprising public electrode; With
Form the figure comprising pixel electrode, to make often to go in described pixel cell, described public electrode is connected with the lastrow in grid line described in the adjacent rows limiting this row pixel cell, and described pixel electrode is connected with the next line in grid line described in the adjacent rows limiting this row pixel cell.
Preferably, the step that described formation comprises the figure of grid line was carried out comprise the step of the figure of public electrode in described formation before, was positioned at the top of the grid line place layer be connected with described public electrode to make described public electrode.
Preferably, the part of described public electrode and the overlap joint at least partially of grid line that is connected with described public electrode.
Preferably, described formation comprises the step that the step of the figure of grid line and described formation comprises the figure of pixel electrode and carries out simultaneously, and described manufacture method also comprises:
Form the first via hole, described first via hole arrives described grid line through the passivation layer of described thin film transistor (TFT) and the gate insulation layer of described thin film transistor (TFT);
Carry out the step that described formation comprises the figure of public electrode, described public electrode is connected with described grid line by described first via hole.
In array base palte provided by the present invention, public electrode is connected with grid line, and grid line can be utilized to power for public electrode, thus eliminates the public electrode wire of powering for public electrode, reduce the area on array base palte shared by wiring part, thus improve the aperture opening ratio of array base palte.In addition, omit total metal content required when public electrode wire can also reduce manufacturing array substrate, reduce the cost of array base palte.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for instructions, is used from explanation the present invention, but is not construed as limiting the invention with embodiment one below.In the accompanying drawings:
Fig. 1 (a) to Fig. 1 (f) is the diagram of the manufacture method of the array base palte showing a kind of embodiment provided by the present invention, and wherein, shown in Fig. 1 (f) is array base palte provided by the present invention;
Fig. 2 is the process flow diagram of the manufacture method of the array base palte showing a kind of embodiment provided by the present invention;
Fig. 3 is the process flow diagram of the manufacture method of the array base palte showing another kind of embodiment provided by the present invention;
Fig. 4 is the A-A cut-open view of the array base palte shown in Fig. 1 (f);
Fig. 5 is the cut-open view of the array base palte of another kind of embodiment provided by the present invention.
Description of reference numerals
10: grid line 11: grid
20: public electrode 21: the first via hole
30: gate insulation layer 40: data line
50: active layer 60: source electrode
70: drain electrode 71: the second via holes
80: passivation layer 90: pixel electrode
91: the three via holes
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Should be understood that, embodiment described herein, only for instruction and explanation of the present invention, is not limited to the present invention.
As one aspect of the present invention, as Fig. 1 (f), shown in Fig. 4 and Fig. 5, a kind of array base palte is provided, this array base palte comprises multirow grid line 10 and multi-column data line 40, multirow grid line 10 and multi-column data line 40 cross one another and described array base palte are divided into multiple pixel cell, thin film transistor (TFT) is provided with in each described pixel cell, pixel electrode 90 and the public electrode 20 corresponding with this pixel electrode 90, wherein, in every row pixel cell, public electrode 20 is connected with the lastrow in the adjacent rows grid line limiting this row pixel cell, pixel electrode 90 is connected with the next line in the adjacent rows grid line limiting this row pixel cell respectively.Such as, as shown in Fig. 1 (f), the adjacent capable grid line of N-1 and N-th row grid line collectively define line K pixel cell, and public electrode is connected with the capable grid line of N-1, and pixel electrode is connected with N-th row grid line.
As mentioned above, public electrode 20 is connected with grid line 10, and grid line 10 can be utilized to power for public electrode 20, thus eliminates the public electrode wire into public electrode 20 power supply, reduce the area on array base palte shared by wiring part, thus improve the aperture opening ratio of array base palte.
In addition, omit total metal content required when public electrode wire can also reduce manufacturing array substrate, reduce the cost of array base palte.
It is easily understood that pixel electrode 90 non-immediate are connected with grid line, but be connected with grid line by thin film transistor (TFT).Particularly, grid line 10 is one-body molded with the grid 11 of thin film transistor (TFT), the active layer of thin film transistor (TFT) is connected with grid 11 by gate insulation layer, the drain electrode of thin film transistor (TFT) is formed on the active layer of thin film transistor (TFT), and pixel electrode is connected with the drain electrode of thin film transistor (TFT), therefore, pixel electrode is connected with grid line by thin film transistor (TFT).
Should be understood that, multiple pixel cells on described array base palte are divided into multirow and multiple row according to many grid lines and a plurality of data lines, in order to make the structure of array base palte simpler, and make described array base palte be easier to processing, preferably, the public electrode 20 being positioned at same a line is connected on same grid line 10.
In array base palte provided by the present invention, adjacent rows grid line 10 limits same a line pixel cell.Due in each pixel cell, the voltage being applied to pixel electrode 90 is different from the voltage be applied on public electrode 20, and therefore, in same pixel cell, pixel electrode 90 is connected from different grid lines respectively with public electrode 20.Such as, as shown in Fig. 1 (b) He Fig. 1 (f), in line K pixel cell, public electrode 20 is electrically connected with the capable grid line of N-1, and pixel electrode 90 is connected with N-th row grid line.Should be understood that, pixel electrode 90 described herein is connected with N-th row grid line and refers to pixel electrode 90 and be connected with N-th row grid line by the drain and gate of thin film transistor (TFT).
When scanning N-th row grid line, the thin film transistor (TFT) be arranged on this N-th row grid line is opened, and data line 40 provides the first voltage for pixel electrode 90, and the voltage now on the capable grid line of N-1 is the second voltage, thus provides the second voltage for public electrode 20.When utilizing the display device of array base palte provided by the present invention for liquid crystal display, the voltage difference between the first voltage and the second voltage should drive liquid crystal molecule to rotate; When utilizing the display device of array base palte provided by the present invention for electrochromic display device (ECD), the voltage difference in the first voltage and second source support should drive electrochromic material variable color.
In the present invention, do not have special restriction to the structure of thin film transistor (TFT), such as, described thin film transistor (TFT) can have top gate structure, also can have bottom grating structure.In the embodiment shown in Fig. 1 f, Fig. 4 and Fig. 5, described thin film transistor (TFT) has bottom grating structure.That is, the grid 11 of thin film transistor (TFT) is positioned at below the active layer 50 of this thin film transistor (TFT).It is well known that grid 11 is one-body molded with grid line, that is, while formation grid line 10, form grid 11.
Realizing the mode that pixel electrode is electrically connected with grid line is well-known in the art, and such as, in the embodiment provided in Fig. 1 (a) to Fig. 1 (f), pixel electrode 90 is electrically connected with grid line by thin film transistor (TFT).
In array base palte provided by the present invention, by numerous embodiments, public electrode can be electrically connected with grid line, such as, as as shown in Fig. 1 (b) and Fig. 4, public electrode 20 and grid line 10 directly can be overlapped, that is, a part for public electrode 20 and the overlap joint at least partially of grid line 10.The advantage that public electrode 20 and grid line 10 directly overlap is, the generation of dead resistance can be reduced.In embodiment in the diagram, pixel electrode 90 can be positioned at the top of public electrode 20.
In the present invention, particular determination is not had to the relative position relation of the thickness direction at array base palte between grid line 10 and public electrode 20, such as, public electrode 20 can be arranged on the below of grid line 10 place layer, or as shown in Fig. 1 (a) to Fig. 1 (f) and Fig. 4 and Fig. 5, public electrode 20 can be arranged on the top of grid line 10 place layer.Should be understood that, " upper and lower " described herein all refers to the above-below direction in Fig. 4 and Fig. 5.
Separate to the grid 11 of described thin film transistor (TFT) and active layer be insulated, described array base palte can comprise gate insulation layer 30, and this gate insulation layer 30 at least covers the part that grid line 10 and public electrode 20 are connected with grid line 10.In embodiment provided by the present invention, in order to save material, gate insulation layer 30 cover only the part that grid line 10 and public electrode 20 are connected with grid line 10.But in other embodiments, gate insulation layer 30 can cover whole substrate.
Certainly, also other modes can be adopted to be electrically connected with grid line 10 by public electrode 20, grid line 10 such as, by the mode arranging the first via hole 21, public electrode 20 can be electrically connected with grid line (as shown in Figure 5), as long as can be utilized to power for public electrode 20.In this case, public electrode 20 can be positioned at the top of pixel electrode 90 place layer.First via hole 21 arrives grid line 10 through the passivation layer 80 of described thin film transistor (TFT) and gate insulation layer 30.
Particularly, as shown in Figure 5, pixel electrode 90 and grid line 10 are positioned at same layer, the top of pixel electrode 90 and grid line 10 place layer is provided with gate insulation layer 30, gate insulation layer 30 is provided with active layer 50 source electrode and the drain electrode 70 of thin film transistor (TFT), drain electrode 70 is connected with pixel electrode 90 by the second via hole 71, the top of drain electrode 70 is provided with passivation layer 80, public electrode 20 is positioned at the top of pixel electrode 90 place layer, first via hole 21 arrives grid line 10 through passivation layer 80 and gate insulation layer 30, and public electrode 20 is connected with grid line 10 by the first via hole 21.
As another aspect of the present invention, provide a kind of display device, this display device comprises array base palte, and wherein, this array base palte is above-mentioned array base palte provided by the present invention.
Because described array base palte has larger aperture opening ratio, therefore, display device provided by the present invention has display effect more clearly.
Correspondingly, display device of the present invention comprises gate drivers and source electrode driver, and grid line 10 is electrically connected with described gate drivers, and data line 40 is electrically connected with described source electrode driver.Therefore, gate drivers is directly powered for public electrode, eliminates extra circuit structure of powering for public electrode, thus further simplify the structure of described display device.
In the present invention, the restriction not special to the type of display device, such as, described display device can be liquid crystal indicator, also can be electrochromic display device etc.When described display device is liquid crystal indicator, in order to provide driving voltage for the liquid crystal in display device, preferably, the difference between the negative voltage VGL that described gate drivers provides and the voltage that described source electrode driver provides is between-4.5V to 4.5V.That is, when the low level negative voltage that described gate drivers provides is for-5V, the voltage that source electrode driver provides can be selected between-0.5V ~-9.5V.
The drive principle of display device provided by the present invention is described below in conjunction with Fig. 1 (f).As shown in Fig. 1 f, the thin film transistor (TFT) of line K pixel cell can be opened by N-th row grid line 10, thus be the charging of line K pixel cell, the thin film transistor (TFT) of capable for K+1 pixel cell can be opened by the capable grid line of N+1, thus is the capable pixel cell charging of K+1.When charging for line K pixel cell, the voltage except N-th row grid line is except high voltage VGH, and the voltage of other grid lines is low-voltage VGL; In line K pixel cell the voltage of public electrode equal N-1 capable in the voltage of grid line, that is, low-voltage VGL.The voltage of N-th row grid line is high voltage VGH, can open thin film transistor (TFT), and described source electrode driver is that pixel electrode charges.After charging, the voltage (voltage difference between pixel electrode and public electrode) be applied on liquid crystal maintains until next frame one's own profession pixel cell charges again.
When utilizing described display device to show, the content of each pixel cell display can not be suddenlyd change, and this just requires pixel capacitance (being formed by pixel electrode and public electrode) and be stored in pixel capacitance two ends pressure reduction to suddenly change.In display device provided by the present invention, when line K pixel cell charges, the capable pixel cell of K+1 is subject to following impact: the voltage of the capable public electrode of K+1 is with the change in voltage of N-th row grid line, high voltage VGH is become from low-voltage VGL, but only when the change in voltage of N-th row grid line, the pixel cell that K+1 is capable just can be affected, and due to electric capacity characteristic (namely, charge or discharge process is there is when the voltage at electric capacity two ends changes, but this process need regular hour), and high voltage duration on grid line is extremely short, electric capacity not yet has enough time to discharge, or discharge capacity is minimum, negligible, therefore, even if the pixel capacitance two ends pressure reduction generation disturbance time that also a disturbance is extremely short of pixel cell, most of the time, pixel capacitance pressure reduction is not disturbance.For the resolution of 1366 × 768, the ratio of not disturbance time and disturbance time is 767:1, therefore, can ignore the show image of pixel.
As shown in Fig. 1 a to Fig. 1 f and 2, as another aspect of the invention, a kind of manufacture method of array base palte is also provided, this array base palte comprises multirow grid line 10 and multi-column data line 40, this multirow grid line 10 and multi-column data line 40 cross one another and described array base palte are divided into multiple pixel cell, each described pixel cell comprises thin film transistor (TFT), pixel electrode 90 and the public electrode 20 corresponding with this pixel electrode 90, wherein, as shown in Fig. 1 (a), Fig. 1 (b), Fig. 1 (f) He Fig. 2, described manufacture method comprises:
Form the figure (as shown in Figure 1a) comprising grid line 10; With
Form the figure (as Suo Shi Fig. 1 (b)) comprising public electrode 20; With
Form the figure (as Suo Shi Fig. 1 (f)) comprising pixel electrode 90, to make in every row pixel cell, public electrode 20 is connected with the lastrow in the adjacent rows grid line limiting this row pixel cell, and pixel electrode 90 is connected with the next line in the adjacent rows grid line 10 limiting this row pixel cell.
As noted before, public electrode 20 is connected with grid line 10, thus utilizes grid line 10 to provide voltage to save public electrode wire for public electrode 20, saved the consumption of metal, reduced the cost of array base palte.And decrease distribution on array base palte, improve the aperture opening ratio of array base palte.
It is easily understood that the step providing substrate of also carrying out before formation comprises the figure of grid line in manufacture method provided by the present invention, grid line, public electrode, pixel electrode, data line, thin film transistor (TFT) are all arranged on substrate.
In the present invention, to the sequencing not particular determination of each step, the order of each step above-mentioned can be decided according to the concrete structure of required array base palte.Such as, in embodiment provided by the present invention, grid line 10 is formed directly on substrate, public electrode 20 is positioned at the top of the grid line place layer be connected with this public electrode, pixel electrode 90 is positioned at the top of public electrode 20 place layer, in this embodiment, the step that described formation comprises the step of the figure of grid line, described formation comprises the figure of public electrode step and described formation comprise the figure of pixel electrode can once be carried out.
Mask technique can be utilized to carry out described formation comprises the step of the figure of grid, described formation comprises the figure of public electrode step and described formation comprise the step of the figure of pixel electrode.。Such as, the step that described formation comprises the figure of grid can comprise the rete of the metal first forming grid, is then formed the figure comprising grid line 10 by patterning processes.
Can be formed described " forming the rete of the metal of grid " by various ways such as deposition, coating, sputterings.
Patterning processes comprises the techniques such as photoresist coating, exposure, development, etching and photoresist lift off.
Certainly, other modes such as printing, printing also can be adopted to be formed in figure substrate being formed and comprises grid line.
To comprise the technique of the step of the figure of grid similar with implementing described formation to implement to be formed the technique that comprises the step of the figure of public electrode, repeats no more here.
Should be understood that, comprise the grid 11 that the figure comprising grid line 10 formed in the step of the figure of grid also comprises thin film transistor (TFT) in described formation.
As noted before, in several ways public electrode 20 can be connected with grid line 10, such as, in order to reduce dead resistance simplified manufacturing technique, can by the overlap joint at least partially (as shown in Figure 4) of a part for public electrode 20 and the grid line 10 be connected with this public electrode 20.After grid line 10 is formed directly on the layer of public electrode 20 place, grid line 10 is directly connected with public electrode, without the need to the first via hole, because this simplify the manufacturing process of described array base palte.Or, can first form public electrode 20, then form grid line 10, as long as guarantee overlapping with a part for public electrode 20 at least partially of grid line 10.
In the above-described embodiment, as shown in Fig. 1 (d) to Fig. 1 (f) and Fig. 2, after formation includes the step of the figure of active layer 50, can following steps be carried out:
Formed and comprise the source electrode 60 of data line 40 and described thin film transistor (TFT) and the figure of drain electrode 70;
Form passivation layer 80, this passivation layer 80 can cover whole substrate;
Form the 3rd via hole the 91, three via hole 91 and arrive drain electrode 70 through passivation layer 80.
In accompanying drawing provided by the present invention, pixel electrode 90 is positioned at the superiors, therefore, finally carries out the step that described formation comprises the figure of pixel electrode.Form the figure comprising pixel electrode 90, pixel electrode 90 is connected with drain electrode 70 by described 3rd via hole 91.
In order to the active layer 50 of thin film transistor (TFT) and grid 11 be separated, as shown in Fig. 1 (c), described manufacture method also comprises: form gate insulation layer 30, this gate insulation layer 30 at least covers grid line 10 and the part that public electrode 20 is connected with grid line 10.
Same as shown in Fig. 1 (c), in the thin film transistor (TFT) with bottom grating structure, described manufacture method is carried out after can also being included in and forming gate insulation layer 30: form the figure including active layer 50.It is easily understood that this active layer 50 is formed on gate insulation layer 30.
Or, as another embodiment of the invention, by the first via hole 21, public electrode can be connected (as shown in Figure 5) with grid line 10.In this case, as shown in Figure 3, described formation comprises the step that the step of the figure of grid line 10 and described formation comprises the figure of pixel electrode 90 and carries out simultaneously, and described manufacture method comprises:
Form the first via hole 21, this first via hole 21 arrives grid line 10 through the passivation layer 80 of described thin film transistor (TFT) and the gate insulation layer 30 of described thin film transistor (TFT);
Carry out the step that described formation comprises the figure of public electrode 20, public electrode 20 is connected with grid line 10 by the first via hole 21.
Should be understood that, described thin film transistor (TFT) comprises the grid 11, active layer 50, gate insulation layer 30, the source electrode be connected with active layer 50 between grid 11 and active layer 50 that form as one with grid line 10 and drains 70.Public electrode 20 is connected with grid line 10 with gate insulation layer 30 through passivation layer 80 successively.
Particularly, before the step of described formation first via hole 21, manufacture method provided by the present invention can also comprise the following steps:
Form gate insulation layer 30, this gate insulation layer at least covers grid line 10;
Form the figure comprising the active layer 50 of described thin film transistor (TFT);
Form the second via hole 71, this second via hole 71 arrives pixel electrode 90 through gate insulation layer 30;
Form the figure comprising the source electrode of data line 40 and described thin film transistor (TFT) and the drain electrode 70 of described thin film transistor (TFT), the drain electrode 70 of described thin film transistor (TFT) is connected with pixel electrode 90 by the second via hole 71;
Form passivation layer 80, the step of described formation passivation layer 80 is carried out after described formation comprises the figure of the source electrode of described thin film transistor (TFT) and the drain electrode 70 of described thin film transistor (TFT).
In the manufacture method of the array base palte shown in shop drawings 5, forming the step providing substrate before grid line 10 and pixel electrode 90, grid line 10, thin film transistor (TFT), data line 40, pixel electrode 90 and public electrode 20 are all arranged on substrate.
As noted before, as one embodiment of the present invention, described thin film transistor (TFT) can have bottom grating structure, and certainly, described thin film transistor (TFT) also can have top gate structure.Certainly, in the thin film transistor (TFT) with top gate structure, active layer is formed in the below of gate insulation layer.
Implement the step of the figure forming the source electrode 60 and drain electrode 70 comprising data line 40 and described thin film transistor (TFT) and to implement to form the concrete technology comprising the step of the figure of pixel electrode similar with the concrete technology implementing to be formed the step of the figure comprising grid line, repeat no more here.
Be understandable that, the illustrative embodiments that above embodiment is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (10)
1. an array base palte, described array base palte comprises multirow grid line and multi-column data line, described multirow grid line and multi-column data line cross one another and described array base palte are divided into multiple pixel cell, described pixel cell comprises thin film transistor (TFT), pixel electrode and the public electrode corresponding with described pixel electrode, it is characterized in that, often going in described pixel cell, described public electrode is connected with the lastrow in grid line described in the adjacent rows limiting this row pixel cell, described pixel electrode is connected with the next line in grid line described in the adjacent rows limiting this row pixel cell.
2. array base palte according to claim 1, is characterized in that, the part of described public electrode and the overlap joint at least partially of grid line be connected with described public electrode.
3. array base palte according to claim 1 and 2, is characterized in that, described public electrode is positioned at the top of the grid line place layer be connected with described public electrode.
4. array base palte according to claim 1, is characterized in that, described public electrode is positioned at the top of described pixel electrode and described grid line place layer, described public electrode by the first via hole and the grid line that is connected with described public electrode connected.
5. a display device, described display device comprises array base palte, it is characterized in that, described array base palte is the array base palte in Claims 1-4 described in any one.
6. display device according to claim 5, it is characterized in that, described display device comprises gate drivers and source electrode driver, described grid line is electrically connected with described gate drivers, described data line is electrically connected with described source electrode driver, and the difference between the low level that described gate drivers provides and the level that described source electrode driver provides is between-4.5V to 4.5V.
7. the manufacture method of an array base palte, described array base palte comprises multirow grid line and multi-column data line, described multirow grid line and multi-column data line cross one another and described array base palte are divided into multiple pixel cell, each described pixel cell comprises thin film transistor (TFT), pixel electrode and the public electrode corresponding with described pixel electrode, it is characterized in that, described manufacture method comprises:
Form the figure comprising grid line; With
Form the figure comprising public electrode; With
Form the figure comprising pixel electrode, to make often to go in described pixel cell, described public electrode is connected with the lastrow in grid line described in the adjacent rows limiting this row pixel cell, and described pixel electrode is connected with the next line in grid line described in the adjacent rows limiting this row pixel cell.
8. manufacture method according to claim 7, it is characterized in that, the step that described formation comprises the figure of grid line was carried out comprise the step of the figure of public electrode in described formation before, was positioned at the top of the grid line place layer be connected with described public electrode to make described public electrode.
9. the manufacture method according to claim 7 or 8, is characterized in that, the part of described public electrode and the overlap joint at least partially of grid line be connected with described public electrode.
10. manufacture method according to claim 7, is characterized in that, described formation comprises the step that the step of the figure of grid line and described formation comprises the figure of pixel electrode and carries out simultaneously, and described manufacture method also comprises:
Form the first via hole, described first via hole arrives described grid line through the passivation layer of described thin film transistor (TFT) and the gate insulation layer of described thin film transistor (TFT);
Carry out the step that described formation comprises the figure of public electrode, described public electrode is connected with described grid line by described first via hole.
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| JP2013080185A (en) * | 2011-10-05 | 2013-05-02 | Japan Display East Co Ltd | Liquid crystal display device |
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| CN1704828A (en) * | 2004-05-31 | 2005-12-07 | Lg.菲利浦Lcd株式会社 | In-plane switching liquid crystal display and driving method thereof |
| CN1892328A (en) * | 2005-06-27 | 2007-01-10 | Lg.菲利浦Lcd株式会社 | In-plane switching mode liquid crystal display device and method of manufacturing the same |
| CN1945391A (en) * | 2005-09-27 | 2007-04-11 | 三星电子株式会社 | Liquid crystal display |
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| CN103472635A (en) | 2013-12-25 |
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