CN103472288A - Peak voltage detection circuit - Google Patents
Peak voltage detection circuit Download PDFInfo
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- CN103472288A CN103472288A CN2013103903142A CN201310390314A CN103472288A CN 103472288 A CN103472288 A CN 103472288A CN 2013103903142 A CN2013103903142 A CN 2013103903142A CN 201310390314 A CN201310390314 A CN 201310390314A CN 103472288 A CN103472288 A CN 103472288A
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- hysteresis comparator
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- transmission gate
- signal
- time delay
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Abstract
The invention discloses a peak voltage detection circuit, which is used for solving the technical problem of low accuracy of the existing peak voltage detection circuit. The technical scheme is as follows: the circuit is composed of a controllable time-delay unit, a hysteresis comparator, a transmission gate switch and a holding capacitor, wherein the controllable time-delay unit is realized by a passive RC (resistor-capacitor) circuit; the transmission gate switch is realized by connecting an NMOS (N-channel metal oxide semiconductor) transistor and a PMOS (P-channel metal oxide semiconductor) transistor in parallel; a time-delayed signal is obtained after the time delay of the controllable time-delay unit for an input signal, the time-delayed signal is input to the hysteresis comparator, and the output signals Vn and Vp of the hysteresis comparator are used for controlling the on/off of the NMOS transistor and the PMOS transistor respectively, so that voltages Vout at the both ends of the holding capacitor Ch are changed along with the time-delayed signal Vd, and an output voltage on the holding capacitor is a peak output voltage. Due to the addition of the hysteresis comparator and the controllable time-delay unit, the peak voltage detection error is reduced to be less than 1% from 5-18% of the background technology, and the detection accuracy is increased to be more than 99% from 82-95% of the background technology.
Description
Technical field
The present invention relates to a kind of crest voltage testing circuit.
Background technology
With reference to Fig. 7.Document " Ming Zhang; Nicolas Llaser; Herve Mathias; Design and analysis of switched-capacitor-based peak detector[C]; Circuit and System (ISCAS); pp.1001-1004,2011 " a kind of switching capacity peak detection circuit disclosed.In this circuit, input signal Vin produces the inhibit signal Vh of input signal after switch S 1 and capacitor C 1, input signal Vin and inhibit signal Vh input comparator are compared, controlling 2 couples of inhibit signal Vh of switch S when comparator output signal Vo becomes high level is sampled, make the voltage-tracing input signal on capacitor C 2, finally export crest voltage Vout.The shortcoming of this peak detection circuit is: 1) crest voltage detection error is large, is about 5%～18%, detection accuracy 82%～95%; 2) do not consider the impact of noise on the comparer action in circuit.As can be seen from Figure 8, if noise contributions can produce burr signal on inhibit signal Vh, especially, when burr signal appears near peak value, comparer is exported a plurality of high level, causes obtaining crest voltage accurately.
Summary of the invention
In order to overcome the existing low deficiency of crest voltage testing circuit precision, the invention provides a kind of crest voltage testing circuit.This circuit is comprised of controllable time delay unit, hysteresis comparator, transmission gate switch and maintenance electric capacity.Wherein, the controllable time delay unit is realized by resistance R and capacitor C; Transmission gate switch is by NMOS pipe and the realization in parallel of PMOS pipe.Input signal obtains time delayed signal after the time delay of controllable time delay unit, and time delayed signal is input to the negative input of hysteresis comparator and receives the input end of transmission gate switch simultaneously.The positive input of hysteresis comparator is connected with input signal, the forward output terminal of hysteresis comparator connects the grid of NMOS pipe, the negative sense output terminal of hysteresis comparator connects the grid of PMOS pipe, the output of transmission gate switch is connected to and keeps on electric capacity, keeps the output voltage on electric capacity to be peak output voltage.Owing to having increased hysteresis comparator, not only can obtain accurate crest voltage and detect constantly, and can eliminate the impact of noise and burr, can effectively improve the accuracy of detection of crest voltage; The controllable time delay unit that utilization is realized by passive RC circuit, the time delay size that can accurately control and regulate input signal, with the hysteresis voltage of exact matching hysteresis comparator.
The technical solution adopted for the present invention to solve the technical problems is: a kind of crest voltage testing circuit, and comprise comparer and keep electric capacity, be characterized in also comprising controllable time delay unit and transmission gate switch.Described comparer is hysteresis comparator.Input signal V
inobtain time delayed signal V after the time delay of controllable time delay unit
d, time delayed signal V
dbe input to the negative input of hysteresis comparator and receive transmission gate switch S simultaneously
nand S
pinput end.The positive input of hysteresis comparator and input signal V
inbe connected, the forward output terminal of hysteresis comparator and the output signal V of negative sense output terminal
nand V
pcontrol respectively transmission gate switch S
nand S
pclosure and shutoff, when switch is closed, keep capacitor C
hboth end voltage V
outfollow time delayed signal V
dchange, when switch turn-offs, output voltage V
outbe held.Transmission gate switch S
nand S
poutput be connected to the maintenance capacitor C
han end, keep capacitor C
hother end ground connection, keep capacitor C
hon output voltage be peak output voltage.
Described controllable time delay unit is realized by the RC passive electric circuit, and regulating resistance R or capacitor C realize the time delay adjusting.
Described transmission gate switch is by NMOS pipe and the realization in parallel of PMOS pipe.The forward output terminal of hysteresis comparator connects the grid of NMOS pipe M1, and the negative sense output terminal of hysteresis comparator connects the grid of PMOS pipe M2.
The invention has the beneficial effects as follows: this circuit is comprised of controllable time delay unit, hysteresis comparator, transmission gate switch and maintenance electric capacity.Wherein, the controllable time delay unit is realized by resistance R and capacitor C; Transmission gate switch is by NMOS pipe and the realization in parallel of PMOS pipe.Input signal obtains time delayed signal after the time delay of controllable time delay unit, and time delayed signal is input to the negative input of hysteresis comparator and receives the input end of transmission gate switch simultaneously.The positive input of hysteresis comparator is connected with input signal, the forward output terminal of hysteresis comparator connects the grid of NMOS pipe, the negative sense output terminal of hysteresis comparator connects the grid of PMOS pipe, the output of transmission gate switch is connected to and keeps on electric capacity, keeps the output voltage on electric capacity to be peak output voltage.Owing to having increased hysteresis comparator, not only can obtain accurate crest voltage and detect constantly, and can eliminate the impact of noise and burr, can effectively improve the accuracy of detection of crest voltage; The controllable time delay unit that utilization is realized by passive RC circuit, the time delay size that can accurately control and regulate input signal, with the hysteresis voltage of exact matching hysteresis comparator.Crest voltage detect error by 5%～18% of background technology be reduced to<1%, detection accuracy is brought up to more than 99% by 82%～95% of background technology.
Below in conjunction with drawings and Examples, the present invention is elaborated.
The accompanying drawing explanation
Fig. 1 is the structured flowchart of crest voltage testing circuit of the present invention.
Fig. 2 is that Fig. 1 circuit crest voltage detects principle schematic.
Fig. 3 is that common comparer contains noisy response curve to input.
Fig. 4 is that hysteresis comparator contains noisy response curve to input.
Fig. 5 is the structured flowchart of crest voltage testing circuit embodiment of the present invention.
Fig. 6 is that circuit crest voltage of the present invention detects the error simulation result.
Fig. 7 is the structured flowchart of background technology crest voltage testing circuit.
Fig. 8 is the influence curve of background technology crest voltage testing circuit noise to the crest voltage accuracy of detection.
Embodiment
With reference to Fig. 1-6.Crest voltage testing circuit of the present invention comprises comparer, keeps electric capacity, controllable time delay unit and transmission gate switch.Described comparer is hysteresis comparator.Input signal V
inobtain time delayed signal V after the time delay of controllable time delay unit
d, time delayed signal V
dbe input to the negative input of hysteresis comparator and receive transmission gate switch S simultaneously
nand S
pinput end.The positive input of hysteresis comparator and input signal V
inbe connected, the forward output terminal of hysteresis comparator and the output signal V of negative sense output terminal
nand V
pcontrol respectively transmission gate switch S
nand S
pclosure and shutoff, when switch is closed, keep capacitor C
hboth end voltage V
outfollow time delayed signal V
dchange, when switch turn-offs, output voltage V
outbe held.Transmission gate switch S
nand S
poutput be connected to the maintenance capacitor C
han end, keep capacitor C
hother end ground connection, keep capacitor C
hon output voltage be peak output voltage.
At first pass through the controllable time delay unit by input signal V to be measured
incarry out time delay and obtain time delayed signal V
d, then by time delayed signal V
dwith input signal V
inthe input hysteresis comparator compares, the positive and negative output signal V of hysteresis comparator
nand V
pcontrol respectively transmission gate switch S
nand S
pclosure and shutoff, when switch is closed, keep capacitor C
hboth end voltage V
outfollow time delayed signal V
dchange, when switch turn-offs, output voltage V
outbe held.
Suppose input signal V
inwith time delayed signal V
dbetween time delay be t
d, at time delayed signal V
dbetween the rising stage, due to V
inv
d, the output V of comparer
nfor high level, V
pfor low level, switch S
nand S
pequal closure, now C
hboth end voltage V
outfollow time delayed signal V
dchange; As time delayed signal V
dafter reaching peak value and while starting to descend, due to V
in<V
d, comparator output signal overturns, i.e. V
nbecome low level, V
pbecome high level, now switch S
nand S
pall turn-off, because of the maintenance capacitor C of output terminal
hthe discharge off path, therefore can be by time delayed signal V
dcrest voltage remain at C
hupper, and as crest voltage V
outoutput.
Keep capacitor C
hthe upper final output voltage V kept
outvalue depends on the upset moment of comparator output signal, therefore, and comparator output signal V
nand V
pupset constantly directly determined the precision that crest voltage detects, this will ask accurately control and regulate comparer upset constantly.In the present invention, introducing hysteresis comparator, is Δ V if set the hysteresis voltage of hysteresis comparator, the output signal V of comparer
nand V
pjust at time delayed signal V
dreach peak value and constantly overturn, the crest voltage of input signal can accurately be detected like this.Another advantage of introducing hysteresis comparator is to eliminate the interference of noise.If input signal V
inon noise is arranged, i.e. burr signal, common comparer V
outexport a plurality of comparative results.Adopt hysteresis comparator to containing noisy input signal, comparing processing, but the elimination noise signal is eliminated the V produced by burr signal
outresult.The amplitude peak of supposing the noise signal that exists in detection system is v
n, as long as set the hysteresis voltage Δ V of hysteresis comparator, be greater than v
n, the output signal of comparer just can not be subject to the interference of noise, is conducive to improve accuracy of detection.
In order to coordinate the hysteresis voltage Δ V of hysteresis comparator, in the present invention, adopt the controllable time delay unit to realize that accurate time delay is controlled and adjusting, guarantee measured signal V
inwith time delayed signal V
dbetween accurate delay be t
d.The controllable time delay unit is realized by the RC passive electric circuit, and regulating resistance R or capacitor C can realize the time delay adjusting.
The controllable time delay unit is realized by controllable resistor R and capacitor C; Transmission gate switch is by NMOS pipe M1 and in parallel realization of PMOS pipe M2.Input signal V
inobtain time delayed signal V after the time delay of controllable time delay unit
d, V
dbe input to the negative input of hysteresis comparator, V
dreceive the input end of transmission gate switch simultaneously.The positive input of hysteresis comparator and input signal V
inbe connected, the forward output terminal V of hysteresis comparator
nthe grid that connects NMOS pipe M1, the negative sense output terminal V of hysteresis comparator
pconnect the grid of PMOS pipe M2, the output of transmission gate switch is connected to the maintenance capacitor C
hupper, C
hon output voltage be peak output voltage V
out.
Adopt 0.35um CMOS technological design to realize the crest voltage testing circuit, the hysteresis voltage of hysteresis comparator is made as 30mV, is greater than noise voltage, and the RC delay time is made as 50ns.Simulation result shows, for sinusoidal input signal, and the detection error of crest voltage<1%, the crest voltage detection accuracy can reach 99%.。
The crest voltage testing circuit that the present invention proposes also can detect the trough place voltage of input signal, now only need change the forward input voltage of hysteresis comparator into time delay voltage, or the control signal of transmission gate is carried out oppositely getting final product.
Claims (3)
1. a crest voltage testing circuit, comprise comparer and keep electric capacity, characterized by further comprising and also comprise controllable time delay unit and transmission gate switch; Described comparer is hysteresis comparator; Input signal V
inobtain time delayed signal V after the time delay of controllable time delay unit
d, time delayed signal V
dbe input to the negative input of hysteresis comparator and receive transmission gate switch S simultaneously
nand S
pinput end; The positive input of hysteresis comparator and input signal V
inbe connected, the forward output terminal of hysteresis comparator and the output signal V of negative sense output terminal
nand V
pcontrol respectively transmission gate switch S
nand S
pclosure and shutoff, when switch is closed, keep capacitor C
hboth end voltage V
outfollow time delayed signal V
dchange, when switch turn-offs, output voltage V
outbe held; Transmission gate switch S
nand S
poutput be connected to the maintenance capacitor C
han end, keep capacitor C
hother end ground connection, keep capacitor C
hon output voltage be peak output voltage.
2. crest voltage testing circuit according to claim 1 is characterized in that: described controllable time delay unit is realized by the RC passive electric circuit, and regulating resistance R or capacitor C realize that time delay regulates.
3. crest voltage testing circuit according to claim 1 is characterized in that: described transmission gate switch is by NMOS pipe and the realization in parallel of PMOS pipe; The forward output terminal of hysteresis comparator connects the grid of NMOS pipe M1, and the negative sense output terminal of hysteresis comparator connects the grid of PMOS pipe M2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103903142A CN103472288A (en) | 2013-08-30 | 2013-08-30 | Peak voltage detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103903142A CN103472288A (en) | 2013-08-30 | 2013-08-30 | Peak voltage detection circuit |
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| Publication Number | Publication Date |
|---|---|
| CN103472288A true CN103472288A (en) | 2013-12-25 |
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|---|---|---|---|
| CN2013103903142A Pending CN103472288A (en) | 2013-08-30 | 2013-08-30 | Peak voltage detection circuit |
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|---|---|
| CN (1) | CN103472288A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105652071A (en) * | 2016-02-22 | 2016-06-08 | 深圳市明微电子股份有限公司 | Pulse peak amplitude measuring device and measuring circuit thereof |
| CN115032441A (en) * | 2022-04-15 | 2022-09-09 | 龙芯中科技术股份有限公司 | Voltage peak detection circuit and electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998019172A1 (en) * | 1996-10-29 | 1998-05-07 | Mikroprozessor Handels-Ges.Mbh & Co. Kg | Circuit for the hysteresis-related detection of the threshold value of the peak value of a periodic input signal |
| JP2003215173A (en) * | 2002-01-23 | 2003-07-30 | Nec Microsystems Ltd | Peak-holding circuit |
| JP2010187092A (en) * | 2009-02-10 | 2010-08-26 | Dkk Toa Corp | Peak hold circuit |
| CN102089665A (en) * | 2008-07-10 | 2011-06-08 | 西门子工业公司 | Single-supply single-ended high voltage peak detector |
| CN102685984A (en) * | 2012-04-10 | 2012-09-19 | 苏州聚元微电子有限公司 | LED (Light Emitting Diode) constant-current driving circuit |
-
2013
- 2013-08-30 CN CN2013103903142A patent/CN103472288A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998019172A1 (en) * | 1996-10-29 | 1998-05-07 | Mikroprozessor Handels-Ges.Mbh & Co. Kg | Circuit for the hysteresis-related detection of the threshold value of the peak value of a periodic input signal |
| JP2003215173A (en) * | 2002-01-23 | 2003-07-30 | Nec Microsystems Ltd | Peak-holding circuit |
| CN102089665A (en) * | 2008-07-10 | 2011-06-08 | 西门子工业公司 | Single-supply single-ended high voltage peak detector |
| JP2010187092A (en) * | 2009-02-10 | 2010-08-26 | Dkk Toa Corp | Peak hold circuit |
| CN102685984A (en) * | 2012-04-10 | 2012-09-19 | 苏州聚元微电子有限公司 | LED (Light Emitting Diode) constant-current driving circuit |
Non-Patent Citations (1)
| Title |
|---|
| MING ZHANG ET AL.: "Design and analysis of switched-capacitor-based peak detector", 《CIRCUIT AND SYSTEM(ISCAS)》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105652071A (en) * | 2016-02-22 | 2016-06-08 | 深圳市明微电子股份有限公司 | Pulse peak amplitude measuring device and measuring circuit thereof |
| CN105652071B (en) * | 2016-02-22 | 2018-12-28 | 深圳市明微电子股份有限公司 | Pulse spike amplitude measurement device and its measuring circuit |
| CN115032441A (en) * | 2022-04-15 | 2022-09-09 | 龙芯中科技术股份有限公司 | Voltage peak detection circuit and electronic equipment |
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Application publication date: 20131225 |