CN103456738A - Thin film transistor substrate and displayer - Google Patents
Thin film transistor substrate and displayer Download PDFInfo
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- CN103456738A CN103456738A CN2012101851967A CN201210185196A CN103456738A CN 103456738 A CN103456738 A CN 103456738A CN 2012101851967 A CN2012101851967 A CN 2012101851967A CN 201210185196 A CN201210185196 A CN 201210185196A CN 103456738 A CN103456738 A CN 103456738A
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- film transistor
- thin film
- base plate
- barrier layer
- transistor base
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Abstract
The invention discloses a thin film transistor substrate and a displayer. The thin film transistor substrate comprises a substrate body an a plurality of thin film transistors arranged on the substrate body, wherein each thin film transistor comprises a grid arranged on the substrate body, a first diffusion blocking layer arranged on the substrate body and used for covering the grid, a gate insulator arranged on the first diffusion blocking layer, an active layer arranged on the grate insulator and located above the grid, a source electrode arranged on the substrate body and electrically connected with the active layer, a drain electrode arranged on the substrate body and electrically connected with the active layer, and a protection layer which covers the source electrode and the drain electrode.
Description
Technical field
The present invention relates to thin-film transistor, and particularly relate to thin film transistor base plate and the display with diffused barrier layer.
Background technology
Along with showing being showing improvement or progress day by day of science and technology, people can make life more convenient by the auxiliary of display, for asking the characteristic that display is light, thin, impel flat-panel screens (flat panel display, FPD) to become current main flow.In many flat-panel screens, liquid crystal display (liquid crystal display, LCD) has the advantageous characteristic such as high spatial utilization ratio, low consumpting power, radiationless and low electromagnetic interference, and therefore, liquid crystal display is very popular.
Liquid crystal display is consisted of active array base plate, colored optical filtering substrates and the liquid crystal layer between two substrates.Active array base plate has active area and periphery circuit region.Active array is positioned at active area, and the drive circuit with a plurality of thin-film transistors is positioned at periphery circuit region.At present, thin-film transistor uses grid (lock) insulating barrier to be separated between grid and active layer, so that grid and active layer are insulated from each other, yet the material of grid easily diffuses into gate insulation layer, to such an extent as to affect the insulation characterisitic of gate insulation layer.
Summary of the invention
For addressing the above problem, one embodiment of the invention provides a kind of thin film transistor base plate, comprising: a substrate; A plurality of thin-film transistors, be arranged on substrate, and wherein, each thin-film transistor comprises: a grid is disposed on substrate; One first diffused barrier layer, be disposed on substrate and cover gate; One gate insulation layer, be disposed on the first diffused barrier layer; One active layer, be disposed on gate insulation layer, and be positioned at the grid top; One source pole, be disposed on substrate and be electrically connected to active layer; One drain electrode, be disposed on substrate and be electrically connected to active layer; And a protective layer, cover source electrode and drain electrode.
One embodiment of the invention provides a kind of display to comprise: one in one embodiment, thin film transistor base plate; One substrate, be oppositely arranged with thin film transistor base plate; And a display medium, be formed between thin film transistor base plate and substrate.
The accompanying drawing explanation
The cutaway view of the thin film transistor base plate that Fig. 1 is one embodiment of the invention;
The cutaway view of the thin film transistor base plate that Fig. 2 and Fig. 3 are a plurality of embodiment of the present invention; .
The cutaway view of the thin film transistor base plate that Fig. 4 is one embodiment of the invention;
The cutaway view of the thin film transistor base plate that Fig. 5 and Fig. 6 are a plurality of embodiment of the present invention;
The cutaway view of the display that Fig. 7 is one embodiment of the invention.
The main element symbol description
100,200,400,500,710 ~ thin film transistor base plate;
110 ~ substrate;
120 ~ grid;
122 ~ upper surface;
124 ~ ring-side wall;
126 ~ edge;
130 ~ the first diffused barrier layers;
140 ~ gate insulation layer;
142 ~ the first retes;
144 ~ the second retes;
150 ~ active layer;
160 ~ source electrode;
170 ~ drain electrode;
180 ~ insulating barrier;
190 ~ the second diffused barrier layers;
The 210 ~ three diffused barrier layer (cap rock);
212 ~ edge;
700 ~ display;
720 ~ substrate;
730 ~ display medium;
B1 ~ first bottom;
B2 ~ second bottom;
P ~ protective layer;
S ~ thin-film transistor;
T1, T2, T3, T4, T5 ~ thickness.
Embodiment
Below will describe making and the occupation mode of the embodiment of the present invention in detail.So it should be noted, the invention provides many inventive concepts for application, it can multiple specific pattern be implemented.The specific embodiment of discussing of giving an example in literary composition is only manufacture and use ad hoc fashion of the present invention, non-in order to limit the scope of the invention.In addition, may use label or the sign of repetition in different embodiment.These only repeat, in order simply clearly to narrate the present invention, not represent between discussed different embodiment and/or structure and to have any association.Moreover, when address that one first material layer is positioned on one second material layer or on the time, comprise that the first material layer directly contacts with the second material layer or be separated with the situation of one or more other materials layers.In the accompanying drawings, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.Moreover the element that does not illustrate in figure or describe, for having the form of usually knowing known to the knowledgeable in affiliated technical field.
Fig. 1 illustrates the cutaway view of the thin film transistor base plate of one embodiment of the invention.Please refer to Fig. 1, the thin film transistor base plate 100 of the present embodiment comprises a substrate 110 and a plurality of thin-film transistor S, and thin-film transistor S is arranged on this substrate 110.It should be noted that for simplicity, it is that representative describes that Fig. 1 only illustrates a thin-film transistor S, not in order to limit the present invention.
Each thin-film transistor S comprises a grid 120, one first diffused barrier layer 130, a gate insulation layer 140, an active layer 150, one source pole 160, drain electrode 170 and one a protective layer P.In addition, thin film transistor base plate 100 optionally comprises an insulating barrier 180.
Specifically, grid 120 is disposed on substrate 110.The material of substrate 110 is for example glass or other applicable transparent materials.The material of grid 120 is for example copper, aluminium, molybdenum or other applicable electric conducting materials.
The first diffused barrier layer 130 is disposed on substrate 110 and a upper surface 122 and the ring-side wall 124 be connected with upper surface 122 of cover gate 120.Specifically, in the present embodiment, the upper surface 122 and ring-side wall 124 of the first diffused barrier layer 130 compliance ground cover gate 120.
The material of the first diffused barrier layer 130 is for example the material that nitride, metal oxide or aforesaid combination or other materials (for example copper) that is suitable for barrier grid 120 diffuse to gate insulation layer 140.Particularly, the material of the first diffused barrier layer 130 can be silicon nitride, aluminium oxide, titanium oxide, hafnium oxide, sieve and silica-sesquioxide or aforesaid combination.In addition, the thickness T 1 of the first diffused barrier layer 130 for example is about 10 dusts～5000 dusts.In one embodiment, the thickness T 1 of the first diffused barrier layer 130 is about 500 dusts～1000 dusts.
Insulating barrier 180 is disposed on active layer 150 and covering gate insulating barrier 140, and wherein source electrode 160 is disposed on insulating barrier 180 with drain electrode 170 and runs through insulating barrier 180 and be connected to active layer 150.Source electrode 160 is for example copper, aluminium, molybdenum or other applicable electric conducting materials with the material of drain electrode 170.
Thin film transistor base plate 100 optionally also comprises a protective layer P, and protective layer P is disposed in source electrode 160 and drain electrode 170 and covers insulating barrier 180, with protection source electrode 160, draining 170 avoids being subject to the impact of external environment with insulating barrier 180.The material of protective layer P comprises silica or other applicable insulating material.
In addition, thin film transistor base plate 100 optionally comprises one first bottom B1 and one second bottom B2.Specifically, the first bottom B1 is formed between substrate 110 and grid 120, with adhesive base plate 110 and grid 120.The second bottom B2 is formed at source electrode 160(or drains 170) and active layer 150 between, to reduce source electrode 160(or to drain 170) and active layer 150 between contact impedance.The material of the first bottom B1 and the second bottom B2 can comprise molybdenum, titanium, aluminium, chromium, aforesaid alloy, cupromanganese or aforesaid combination separately.The thickness of the first bottom B1 and the second bottom B2 is about 1 dust to 3000 dust.
It should be noted that the present embodiment complete cover gate 120 the first diffused barrier layer 130 effectively the material of barrier grid 120 diffuse in gate insulation layer 140, and then promote the electrical stability of thin film transistor base plate 100.
Fig. 2 and Fig. 3 illustrate the cutaway view of the thin film transistor base plate of a plurality of embodiment of the present invention.Please refer to Fig. 2, the thin film transistor base plate 200 of the present embodiment is similar in appearance to the thin film transistor base plate 100 of Fig. 1, and both difference parts are that the thin-film transistor S of the thin film transistor base plate 200 of the present embodiment also comprises one the 3rd diffused barrier layer (cap rock) 210.
Specifically, the upper surface 122 of the 3rd diffused barrier layer (cap rock) 210 cover gate 120, and between grid 120 and the first diffused barrier layer 130, diffuse in gate insulation layer 140 with the material of barrier grid 120 further.The thickness T 2 of the 3rd diffused barrier layer (cap rock) 210 is about 1 dust to 3000 dust.The material of the 3rd diffused barrier layer (cap rock) 210 is for example molybdenum, titanium, aluminium, chromium or the alloy of previous materials or the material that other materials that is suitable for barrier grid 120 (for example copper) diffuse to gate insulation layer 140.In the present embodiment, the edge 126(ring-side wall 124 of the edge 212 alignment grids 120 of the 3rd diffused barrier layer (cap rock) 210).In another embodiment, please refer to Fig. 3, the edge 212 of the 3rd diffused barrier layer (cap rock) 210 is less than or equal to the edge of grid 120.The edge of the present embodiment the 3rd diffused barrier layer 210 is less than the edge (that is inwardly shrinking back with respect to the edge 126 of grid 120 in the edge 212 of the 3rd diffused barrier layer (cap rock) 210) of grid 120.
It should be noted that, due to the edge 126(of the edge 212 alignment grids 120 of the 3rd diffused barrier layer (cap rock) 210 as shown in Figure 2) or inwardly shrink back (as shown in Figure 3) with respect to the edge 126 of grid 120, therefore, the first diffused barrier layer 130 that covers the 3rd diffused barrier layer (cap rock) 210 is the ring-side wall of cover gate 120 well also.
Fig. 4 illustrates the cutaway view of the thin film transistor base plate of one embodiment of the invention.Please refer to Fig. 4, the thin film transistor base plate 400 of the present embodiment is similar in appearance to the thin film transistor base plate 100 of Fig. 1, and both difference parts are that the gate insulation layer 140 of the thin film transistor base plate 400 of the present embodiment comprises one first rete 142 and one second rete 144.Specifically, the first rete 142 covers the first diffused barrier layer 130, and the second rete 144 is positioned on the first rete 142, and the hydrogen content of the second rete 144 is lower than the hydrogen content of the first rete 142, and the hydrogen content of the second rete 144 approximately is less than or equal to 20atomic%.
The manufacture method of the first rete 142 and the second rete 144 can be first high hydrogen manufacture craft (sedimentary condition: the proportionality of nitrogen oxide and silicomethane is as be less than 60) of take a high deposition velocity (deposit thickness per minute is for example 1000 dusts) and deposits the first rete 142, then, take the low hydrogen manufacture craft (sedimentary condition: the proportionality of nitrogen oxide and silicomethane is as be greater than 60) of a low deposition speed (deposit thickness per minute is for example 500 dusts) deposits the second rete 144.
Electrical and the gate insulation layer 140 that can affect active layer 150 due to hydrogen atom needs enough thickness, therefore, the first rete 142 that the present embodiment is that hydrogen content is high and deposition velocity is fast first is deposited on the first diffused barrier layer 130, then, just hydrogen content is low and the second rete 144 that deposition velocity is slow is deposited on the first rete 142, thus, the first rete 142 that can be fast by deposition velocity provides enough thicknesses of layers, and can make 150 of active layers contact with the second rete 144 of low hydrogen content, and then avoid hydrogen atom can affect the electrical problem of active layer 150.The thickness T 3 of the second rete 144 is for example 500 dust to 1000 dusts.The gross thickness T4 of gate insulation layer 140 is for example 5000 dusts.
Fig. 5 and Fig. 6 illustrate the cutaway view of the thin film transistor base plate of a plurality of embodiment of the present invention.Please refer to Fig. 5, the thin film transistor base plate 500 of the present embodiment is similar in appearance to the thin film transistor base plate 100 of Fig. 1, and both difference parts are that the thin-film transistor S of the thin film transistor base plate 500 of the present embodiment also comprises one second diffused barrier layer 190.
Specifically, the second diffused barrier layer 190 is disposed in source electrode 160 and drain electrode 170 and covers insulating barrier 180.The material of the second diffused barrier layer 190 is for example silicon nitride, aluminium oxide, titanium oxide, hafnium oxide, sieve and silica-sesquioxide or aforesaid combination.The material of the second diffused barrier layer 190 is for example the material that is same as the first diffused barrier layer 130.The material of the second diffused barrier layer 190 is different from the material of protective layer P.The thickness T 5 of the second diffused barrier layer 190 for example is about 1000 dusts～2000 dusts.In the present embodiment, the second diffused barrier layer 190 is between insulating barrier 180 and protective layer P.
In other embodiments, as shown in Figure 6, the second diffused barrier layer 190 can replace protective layer P fully, therefore, thin film transistor base plate 600 can only utilize the second diffused barrier layer 190 to cover and protect source electrode 160, drain 170 with insulating barrier 180.
Fig. 7 illustrates the cutaway view of the display of one embodiment of the invention.Please refer to Fig. 7, the display 700 of the present embodiment comprises that a thin film transistor base plate 710, a substrate 720 and are sandwiched in the display medium 730 between thin film transistor base plate 710 and substrate 720.Thin film transistor base plate 710 can be the thin film transistor base plate shown in earlier figures 1～Fig. 6, and display medium 730 can be liquid crystal layer or organic luminous layer.Substrate 720 is for example colored optical filtering substrates or transparency carrier.
In sum, the present invention is by the diffused barrier layer of a complete cover gate being set between grid and gate insulation layer, diffusing in gate insulation layer with the material that utilizes the diffused barrier layer barrier grid, and then promotes the electrical stability of thin film transistor base plate.
Although disclosed the present invention in conjunction with above preferred embodiment; yet it is not in order to limit scope of the present invention; be familiar with this operator in technical field under any; without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (20)
1. a thin film transistor base plate comprises:
Substrate;
A plurality of thin-film transistors, be arranged on this substrate, and wherein, each thin-film transistor comprises:
Grid, be disposed on this substrate;
The first diffused barrier layer, be disposed on this substrate and cover this grid;
Gate insulation layer, be disposed on this first diffused barrier layer;
Active layer, be disposed on this gate insulation layer, and be positioned at this grid top;
Source electrode, be disposed on this substrate and be electrically connected to this active layer;
Drain electrode, be disposed on this substrate and be electrically connected to this active layer; And
Protective layer, cover this source electrode and this drain electrode.
2. thin film transistor base plate as claimed in claim 1, wherein the material of this first diffused barrier layer comprises nitride, metal oxide or aforesaid combination.
3. thin film transistor base plate as claimed in claim 2, wherein the nitride material of this first diffused barrier layer comprises silicon nitride.
4. thin film transistor base plate as claimed in claim 2, wherein the metal oxide material of this first diffused barrier layer is by aluminium oxide, titanium oxide, hafnium oxide, sieve and silica-sesquioxide or aforesaid combination.
5. thin film transistor base plate as claimed in claim 1, wherein the thickness of this first diffused barrier layer is about 10 dusts～5000 dusts.
6. thin film transistor base plate as claimed in claim 5, wherein the preferably thickness of this first diffused barrier layer is about 500 dusts～1000 dusts.
7. thin film transistor base plate as claimed in claim 1, wherein this gate insulation layer comprises that first rete and of this first diffused barrier layer of a covering is positioned at the second rete on this first rete, the hydrogen content of this second rete is lower than the hydrogen content of this first rete, and the hydrogen content of this second rete approximately is less than or equal to 20 atomic percents.
8. thin film transistor base plate as claimed in claim 1 also comprises:
Insulating barrier, be disposed on this active layer and cover this gate insulation layer, and wherein this source electrode and this drain configuration are on this insulating barrier and run through this insulating barrier and be connected to this active layer.
9. thin film transistor base plate as claimed in claim 8 also comprises:
The second diffused barrier layer, be disposed at this source electrode and this insulating barrier is gone up and covered in this drain electrode.
10. thin film transistor base plate as claimed in claim 9, wherein this protective layer also covers this second diffused barrier layer, and the material of this protective layer is different from the material of this second diffused barrier layer.
11. thin film transistor base plate as claimed in claim 9, wherein the thickness of this second diffused barrier layer is about 1000 dusts～2000 dusts.
12. thin film transistor base plate as claimed in claim 9, wherein the material of this first diffused barrier layer is same as the material of this second diffused barrier layer.
13. thin film transistor base plate as claimed in claim 9, wherein the material of this second diffused barrier layer comprises silicon nitride, aluminium oxide, titanium oxide, hafnium oxide or sieve and silica-sesquioxide.
14. thin film transistor base plate as claimed in claim 1, wherein, this grid has upper surface and ring-side wall, and the upper surface of this grid also is provided with one the 3rd diffused barrier layer, and the 3rd diffused barrier layer is between this grid and this first diffused barrier layer.
15. thin film transistor base plate as claimed in claim 14, wherein the material of the 3rd diffused barrier layer comprises the alloy of molybdenum, titanium, aluminium, chromium or previous materials.
16. thin film transistor base plate as claimed in claim 14, the wherein ring-side wall of this grid of justified margin of the 3rd diffused barrier layer.
17. thin film transistor base plate as claimed in claim 14, wherein the edge of the 3rd diffused barrier layer (cap rock) is less than or equal to the edge of this grid.
18. a display comprises:
Thin film transistor base plate as claimed in claim 1;
Substrate, be oppositely arranged with this thin film transistor base plate; And
Display medium, be formed between this thin film transistor base plate and this substrate.
19. display as claimed in claim 18, wherein this display medium is a liquid crystal layer.
20. display as claimed in claim 18, wherein this display medium is an organic luminous layer.
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| CN2012101851967A CN103456738A (en) | 2012-06-05 | 2012-06-05 | Thin film transistor substrate and displayer |
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| CN2012101851967A CN103456738A (en) | 2012-06-05 | 2012-06-05 | Thin film transistor substrate and displayer |
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| CN103474471A (en) * | 2013-08-29 | 2013-12-25 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof, and display device |
| CN104022150A (en) * | 2014-02-20 | 2014-09-03 | 友达光电股份有限公司 | Thin film transistor and pixel structure |
| CN105845690A (en) * | 2015-01-14 | 2016-08-10 | 南京瀚宇彩欣科技有限责任公司 | Semiconductor device and manufacturing method therefor |
| CN107482019A (en) * | 2017-08-10 | 2017-12-15 | 深圳市华星光电技术有限公司 | A kind of thin-film transistor array base-plate and preparation method thereof and liquid crystal panel |
| CN108288643A (en) * | 2018-01-26 | 2018-07-17 | 华南理工大学 | A kind of oxide thin film transistor grid and its preparation, oxide thin film transistor |
| CN109143707A (en) * | 2018-10-08 | 2019-01-04 | 惠科股份有限公司 | A kind of conductive layer insulating method, conductive layer insulation system and display device |
| CN109300918A (en) * | 2018-10-08 | 2019-02-01 | 惠科股份有限公司 | A kind of conductive layer insulating method, conductive layer insulation system and display device |
| CN111987095A (en) * | 2019-05-22 | 2020-11-24 | 南亚科技股份有限公司 | Semiconductor element and method for manufacturing the same |
| WO2021022681A1 (en) * | 2019-08-08 | 2021-02-11 | Tcl华星光电技术有限公司 | Thin film transistor array substrate |
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| US9455324B2 (en) | 2013-08-29 | 2016-09-27 | Boe Technology Group Co., Ltd. | Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device |
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| CN103474471B (en) * | 2013-08-29 | 2016-05-25 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method, array base palte and preparation method, display unit |
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| CN104022150A (en) * | 2014-02-20 | 2014-09-03 | 友达光电股份有限公司 | Thin film transistor and pixel structure |
| CN105845690A (en) * | 2015-01-14 | 2016-08-10 | 南京瀚宇彩欣科技有限责任公司 | Semiconductor device and manufacturing method therefor |
| CN107482019A (en) * | 2017-08-10 | 2017-12-15 | 深圳市华星光电技术有限公司 | A kind of thin-film transistor array base-plate and preparation method thereof and liquid crystal panel |
| CN108288643A (en) * | 2018-01-26 | 2018-07-17 | 华南理工大学 | A kind of oxide thin film transistor grid and its preparation, oxide thin film transistor |
| CN109143707A (en) * | 2018-10-08 | 2019-01-04 | 惠科股份有限公司 | A kind of conductive layer insulating method, conductive layer insulation system and display device |
| CN109300918A (en) * | 2018-10-08 | 2019-02-01 | 惠科股份有限公司 | A kind of conductive layer insulating method, conductive layer insulation system and display device |
| WO2020073456A1 (en) * | 2018-10-08 | 2020-04-16 | 惠科股份有限公司 | Method and structure for insulating conductive layer, and display device |
| CN111987095A (en) * | 2019-05-22 | 2020-11-24 | 南亚科技股份有限公司 | Semiconductor element and method for manufacturing the same |
| CN111987095B (en) * | 2019-05-22 | 2024-03-15 | 南亚科技股份有限公司 | Semiconductor element and method for manufacturing the same |
| WO2021022681A1 (en) * | 2019-08-08 | 2021-02-11 | Tcl华星光电技术有限公司 | Thin film transistor array substrate |
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Application publication date: 20131218 |