CN103456659A - Method for manufacturing photoetching registration mark for manufacturing semiconductor device - Google Patents
Method for manufacturing photoetching registration mark for manufacturing semiconductor device Download PDFInfo
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- CN103456659A CN103456659A CN2013103751421A CN201310375142A CN103456659A CN 103456659 A CN103456659 A CN 103456659A CN 2013103751421 A CN2013103751421 A CN 2013103751421A CN 201310375142 A CN201310375142 A CN 201310375142A CN 103456659 A CN103456659 A CN 103456659A
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Abstract
The invention discloses a method for manufacturing a photoetching registration mark for manufacturing a semiconductor device, and relates to the technical field of marks added to semiconductor devices. The method comprises the steps that 1) the upper surface of semiconductor materials is coated with photoresist in a suspension mode; 2) the photoresist at the position of the photoetching mark is removed through a photoetching mask board based on a photolithography technique; 3) a layer of silicon crystal materials is evaporated on the sample with a marked photolithography graph based on an electron beam evaporation process; 4) the photoresist is removed based on a stripping process, the silicon crystal materials on the photoresist are removed at the same time, and the silicon photoetching registration mark is obtained. The photoetching registration mark manufactured by the method are made of silicon, the silicon cannot pollute an MOCVD device or an MBE device, and therefore the mark is suitable for photoetching registration marks for manufacturing common semiconductor devices, and is especially suitable for photoetching registration marks for manufacturing GaN devices based on an ohmic contact zone secondary epitaxial growth n+GnN technology.
Description
Technical field
The present invention relates to be added to the marker technique field on semiconductor device.
Background technology
Photoetching in semiconductor manufacture is an important processing step, and in photoetching process, photoetching alignment mark plays key effect.The GaN material, as the semi-conductive representative of the third generation, is a kind of important semi-conducting material after Si, GaAs material.GaN radical heterojunction field effect transistor (HFET) is study hotspot in the last few years always, and through further investigation in the last few years, device performance and stability have obtained tremendous increase.Along with the lifting of device performance, device size dwindles gradually, and grid are long has been decreased to sub-micron and even nanometer scale, and this has also had higher requirement to device manufacturing process.The ohmic contact resistance of device has important impact to the performance of device, the ohmic contact of traditional Ti/Al/Metal/Au system needs high temperature alloy (850 ℃), high temperature alloy can affect the ohmic contact pattern (especially for small size device) of device on the one hand, also is difficult to further stably reduce on the other hand ohmic contact resistance.
Pass through at present the etching ohmic contact regions, then secondary epitaxy growth n
+gaN, can obtain very low ohmic contact resistance (≤0.2 W.mm), and, owing to only needing low-temperature alloy or alloy not, the ohmic contact surface topography also is greatly improved.Ohmic contact secondary epitaxy growth n
+a critical process in the GaN technical process be exactly need to be in MOCVD or MBE equipment secondary epitaxy growth n
+gaN, traditional metal system mark, because meeting pollutes MOCVD or MBE equipment, therefore can't be used in this technique.At present, mostly adopt etching GaN technology or first at GaN surface epitaxial growth SiN, then utilize lithographic technique to obtain photoetching alignment mark, but these methods need the auxiliary equipment such as ICP etching or PECVD.Because etching needs Cl base gas auxiliary, this technical process can be to environment.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of photoetching alignment mark manufacture method prepared for semiconductor device, and described method can not pollute MOCVD or MBE equipment, therefore is particularly useful for adopting ohmic contact regions secondary epitaxy growth n
+the GaN device production technique of GaN technology.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind of photoetching alignment mark manufacture method prepared for semiconductor device is characterized in that comprising the following steps:
1) upper surface at semi-conducting material is coated with photoresist;
2) utilize mask blank, by photoetching process, the photoresist of photo-etching mark position is removed;
3) by evaporation technology, evaporation one deck silicon crystal material on the sample of carrying out the mark litho pattern;
4) by stripping technology, photoresist is removed, the silicon crystal material when removing photoresist on photoresist is removed, and obtains the silicon photoetching alignment mark.
Preferably, the thickness >=40nm of described silicon crystal material.
Preferably, described semi-conducting material is Si, GaAs or GaN.
The beneficial effect that adopts technique scheme to produce is: the use material of photoetching alignment mark prepared by the method is silicon, silicon can not pollute MOCVD or MBE equipment, can not pollute MOCVD or MBE equipment, therefore, this mark is not only applicable to the photoetching alignment mark of using in the general semiconductor device manufacturing processes, is particularly useful for adopting ohmic contact regions secondary epitaxy growth n
+the photoetching alignment mark of using in the manufacture process of the GaN device of GaN technology.In addition, with respect to other traditional etching marks, photoetching alignment mark preparation technology of the present invention is simple, and only light requirement quarter and electron beam evaporation process get final product, and have reduced processing step, have reduced technology difficulty.Owing to not adopting the auxiliary equipment such as etching, this mark preparation method has avoided the pollution of etching gas to environment, and in addition, because this alignment mark is realized by lithography stripping technique, the neat in edge degree improves greatly, and alignment precision has obtained corresponding raising.
The accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Fig. 1 is the product structure schematic diagram after step 1);
Fig. 2 is through step 2) after the product structure schematic diagram;
Fig. 3 is the product structure schematic diagram after step 3);
Fig. 4 is the product structure schematic diagram after step 4);
Wherein: 1, semi-conducting material 2, photoresist 3, silicon crystal material 4, silicon photoetching alignment mark.
Embodiment
A kind of photoetching alignment mark manufacture method prepared for semiconductor device comprises the following steps:
1) as shown in Figure 1, at the upper surface of semi-conducting material 1, be coated with photoresist 2, described semi-conducting material 1 is Si, GaAs or GaN;
2) as shown in Figure 2, utilize mask blank, by photoetching process, the photoresist of photo-etching mark position 2 is removed;
3) as shown in Figure 3, by electron beam evaporation process, evaporation one deck silicon crystal material 3 on the sample of carrying out the mark litho pattern, the thickness >=40nm of described silicon crystal material 3;
4) as shown in Figure 4, by stripping technology, photoresist 2 is removed, the silicon crystal material 3 when removing photoresist 2 on photoresist 2 is removed, and obtains silicon photoetching alignment mark 4.
The use material of photoetching alignment mark prepared by the method is silicon, silicon can not pollute MOCVD or MBE equipment, can not pollute MOCVD or MBE equipment, therefore, this mark is not only applicable to the photoetching alignment mark of using in the general semiconductor device manufacturing processes, is particularly useful for adopting ohmic contact regions secondary epitaxy growth n
+the photoetching alignment mark of using in the manufacture process of the GaN device of GaN technology.In addition, with respect to other traditional etching marks, photoetching alignment mark preparation technology of the present invention is simple, and only light requirement quarter and electron beam evaporation process get final product, and have reduced processing step, have reduced technology difficulty.Owing to not adopting the auxiliary equipment such as etching, this mark preparation method has avoided the pollution of etching gas to environment, and in addition, because this alignment mark is realized by lithography stripping technique, the neat in edge degree improves greatly, and alignment precision has obtained corresponding raising.
Applied specific case herein principle of the present invention and execution mode thereof are set forth, the explanation of above embodiment is just with helping understand method of the present invention and core concept thereof.It should be pointed out that for the person of ordinary skill of the art, can also carry out some improvement and modification to the present invention under the premise without departing from the principles of the invention, these improvement and modification also fall in the protection range of the claims in the present invention.
Claims (3)
1. the photoetching alignment mark manufacture method prepared for semiconductor device is characterized in that comprising the following steps:
1) upper surface at semi-conducting material (1) is coated with photoresist (2);
2) utilize mask blank, by photoetching process, the photoresist of photo-etching mark position (2) is removed;
3) by evaporation technology, evaporation one deck silicon crystal material (3) on the sample of carrying out the mark litho pattern;
4) by stripping technology, photoresist (2) is removed, the silicon crystal material (3) when removing photoresist (2) on photoresist (2) is removed, and obtains silicon photoetching alignment mark (4).
2. a kind of photoetching alignment mark manufacture method prepared for semiconductor device according to claim 1, is characterized in that the thickness >=40nm of described silicon crystal material (3).
3. a kind of photoetching alignment mark manufacture method prepared for semiconductor device according to claim 1 and 2, is characterized in that described semi-conducting material (1) is Si, GaAs or GaN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103751421A CN103456659A (en) | 2013-08-26 | 2013-08-26 | Method for manufacturing photoetching registration mark for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103751421A CN103456659A (en) | 2013-08-26 | 2013-08-26 | Method for manufacturing photoetching registration mark for manufacturing semiconductor device |
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| CN103456659A true CN103456659A (en) | 2013-12-18 |
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| CN2013103751421A Pending CN103456659A (en) | 2013-08-26 | 2013-08-26 | Method for manufacturing photoetching registration mark for manufacturing semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106025094A (en) * | 2016-05-04 | 2016-10-12 | 京东方科技集团股份有限公司 | Alignment marks on package glass, manufacturing method thereof, OLED and production method thereof |
| CN109188858A (en) * | 2018-09-10 | 2019-01-11 | 复旦大学 | A kind of high-accuracy silicon substrate vias masks version fission graphic structure |
| RU2746676C1 (en) * | 2020-09-01 | 2021-04-19 | Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт электронной техники" | Thermally stable alignment mark for electronic lithography |
| CN114460819A (en) * | 2022-01-14 | 2022-05-10 | 北京量子信息科学研究院 | Alignment mark for electron beam exposure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0982669A (en) * | 1995-09-14 | 1997-03-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| US6562691B2 (en) * | 2001-03-06 | 2003-05-13 | Macronix International Co., Ltd. | Method for forming protrusive alignment-mark |
| CN102969302A (en) * | 2012-11-21 | 2013-03-13 | 华中科技大学 | Electron beam aligning mark based on hafnium oxide and manufacturing method of mark |
-
2013
- 2013-08-26 CN CN2013103751421A patent/CN103456659A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0982669A (en) * | 1995-09-14 | 1997-03-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor device |
| US6562691B2 (en) * | 2001-03-06 | 2003-05-13 | Macronix International Co., Ltd. | Method for forming protrusive alignment-mark |
| CN102969302A (en) * | 2012-11-21 | 2013-03-13 | 华中科技大学 | Electron beam aligning mark based on hafnium oxide and manufacturing method of mark |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106025094A (en) * | 2016-05-04 | 2016-10-12 | 京东方科技集团股份有限公司 | Alignment marks on package glass, manufacturing method thereof, OLED and production method thereof |
| CN109188858A (en) * | 2018-09-10 | 2019-01-11 | 复旦大学 | A kind of high-accuracy silicon substrate vias masks version fission graphic structure |
| RU2746676C1 (en) * | 2020-09-01 | 2021-04-19 | Федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский университет "Московский институт электронной техники" | Thermally stable alignment mark for electronic lithography |
| CN114460819A (en) * | 2022-01-14 | 2022-05-10 | 北京量子信息科学研究院 | Alignment mark for electron beam exposure and preparation method thereof |
| CN114460819B (en) * | 2022-01-14 | 2024-01-26 | 北京量子信息科学研究院 | Alignment mark for electron beam exposure and preparation method thereof |
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Application publication date: 20131218 |
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