JPH0982669A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a metal mask alignment operation in alignment accuracy even after an interlayer insulating film is flattened through a chemical.mechanical polishing method by a method wherein an alignment mark provided with a step is formed on a semiconductor substrate, an interlayer insulating film is formed on all the surface of the semiconductor substrate, and a groove is provided in the insulating film so as to make the alignment mark exposed by partial etching. SOLUTION: A LOCOS oxide film 12 and an alignment mark 13 of polysilicon film are formed on a silicon substrate 11, and an interlayer insulating film 14 of BPSG or the like is formed on all the surface. At this point, a residual step is induced on the surface of the interlayer insulating film 14 corresponding to a step on a ground layer. Then, the interlayer insulating film 14 is partially etched, whereby a groove is provided in the interlayer insulating film 14 so as to make the alignment mark exposed. Next, the interlayer insulating film 14 is flattened by chemical and mechanical polishing, and then the silicon substrate 11 is rinsed with water for removal of polishing tailings. Then, an aluminum film and a resist film are formed, the center position of the alignment mark 13 is detected by irradiation with an He-Ne laser beam, and a metal mask is aligned on the basis of the alignment mark 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to formation of alignment marks on a wafer when a chemical mechanical polishing (CMP) technique is applied for flattening an interlayer insulating film. Regarding the method.

[0002]

2. Description of the Related Art Conventional semiconductor wafer mask alignment is
In the case of a metal forming process or a contact forming process after the interlayer insulating film is formed, the gate polysilicon or LOCOS (Local Oxidation) formed on the semiconductor wafer before the interlayer insulating film is formed.
A step of an alignment mark made of (Of Silicon) or the like remains on the interlayer insulating film, and the remaining step is detected by diffraction of laser light.

As an example, as shown in FIG. 9, a LOCOS oxide film (2) is formed on a silicon substrate (1).
Then, a polysilicon film (3) is formed, and this polysilicon film (3) is used as an alignment mark. And BPSG (Boron PhosphoSilicate glass) film (4) on the entire surface
When the film is formed, the steps of the underlying LOCOS oxide film (2) and the polysilicon film (3) appear as residual steps on the surface of the BPSG film (4).

Next, as shown in FIG. 10, an aluminum film (5) is formed on the BPSG film (4) by a sputtering method, and a resist film (6) is formed on the aluminum film (5).
Is applied and formed. Then, for example, a He-Ne laser is irradiated from above the silicon substrate (1), and a diffraction signal generated from a residual step on the surface of the aluminum film (5) is detected to determine the center position of the alignment mark. The metal mask was aligned based on.

[0005]

By the way, as the wiring of the LSI is multi-layered, chemical mechanical polishing (CMP) is used as a new planarization technique for the interlayer insulating film.
ing) is receiving attention. CMP is a technique of supplying a slurry (polishing material) onto a wafer and mechanically polishing the surface with a pad (polishing cloth). Compared with conventional planarization techniques, flatness and shape controllability in the vertical direction are provided. Is remarkably excellent. In addition,
The CMP is described in detail, for example, in "Monthly Semiconductor World February 1995".

However, if this CMP is directly applied to the conventional process, as shown in FIG.
Since there is no residual step on the film (4) and no diffraction signal is output, the center position of the alignment mark cannot be determined, and subsequent mask alignment becomes impossible. The present invention has been made in view of the above problems,
The purpose is to enable highly accurate alignment even after the interlayer insulating film is flattened by CMP.

[0007]

The present invention will be described with reference to FIGS.
, A step of forming an alignment mark (13) having a step on the semiconductor substrate (11), a step of forming an insulating film (14) on the entire surface of the semiconductor substrate (11), A groove (1) exposing the alignment mark (13) by partially etching the film (14).
5), a step of planarizing the insulating film (14) by chemical mechanical polishing (CMP), and a step (1) in the groove.
5) a step of removing polishing debris accumulated in 5) by washing,
And mask alignment using the exposed alignment mark (13).

Further, according to the present invention, as shown in FIGS. 5 to 8, a step of forming an insulating film (23) on a semiconductor substrate (21) and a partial etching of the insulating film (23). Forming an alignment mark (24) consisting of a groove in the insulating film, planarizing the insulating film (23) by chemical mechanical polishing (CMP), and removing polishing debris deposited in the groove by cleaning And a step of performing mask alignment using the alignment mark (24).

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

(1) First Embodiment First, as shown in FIG. 1, L is formed on a silicon substrate (11).
An alignment mark (13) made of an OCOS oxide film (12) and a polysilicon film is formed, and an interlayer insulating film (14) made of a BPSG film or the like is formed on the entire surface. At this time,
A residual step is formed on the surface of the interlayer insulating film (14) reflecting the step of the base.

Next, as shown in FIG. 2, an interlayer insulating film (1
4) is partially etched to form a groove (15) exposing the alignment mark (13). In this step, a reticle dedicated to mark exposure or a reticle that also serves as a mark (for example, a reticle for contact formation) is used.
Resist pattern formation and etching processing are performed. next,
As shown in FIG. 3, the interlayer insulating film (14) is planarized by CMP. At this time, SiO generated by polishing
2. Abrasive debris such as abrasives may be deposited on the groove (15), deteriorating the accuracy of alignment mark detection and adversely affecting the cleanliness. Therefore, the polishing debris is removed by washing with water after CMP.

Next, as shown in FIG. 4, an aluminum film (16) and a resist film (not shown) are formed, and the center position of the alignment mark (13) is detected by He-Ne laser irradiation. According to the present embodiment, since the alignment mark (13) is exposed from the interlayer insulating film (14), highly accurate position detection and mask alignment can be performed. . (2) Second Embodiment First, as shown in FIG. 5, L is formed on a silicon substrate (21).
An OCOS oxide film (22) and an interlayer insulating film (23) made of a BPSG film are formed.

Next, as shown in FIG. 6, the interlayer insulating film (2
3) is etched to form an alignment mark (24) consisting of a groove. In the first embodiment, the interlayer insulating film is etched to expose the alignment mark, but in the present embodiment, the alignment mark itself is formed by etching.

Next, as shown in FIG. 7, the interlayer insulating film (23) is etched by CMP, and like the first embodiment, it is washed with water to remove polishing debris accumulated in the groove portion. . After this, as shown in FIG. 8, an aluminum film (25) and a resist film (not shown) are formed, and the center position of the alignment mark (24) is detected by He-Ne laser irradiation. According to the embodiment, since the step of the alignment mark remains after CMP, highly accurate position detection and mask alignment can be performed.

[0014]

As described above, according to the present invention,
The interlayer insulating film is etched to expose the alignment mark, or the interlayer insulating film is etched to form the alignment mark itself, and then the interlayer insulating film is planarized by chemical mechanical polishing (CMP). Therefore, the step of the alignment mark remains, and it becomes possible to perform mask alignment of the metal mask, the contact mask, etc. with high accuracy after the interlayer insulating film is formed.

Further, according to the present invention, since polishing debris deposited in the groove of the interlayer insulating film is removed by washing with water or the like during CMP, the alignment mark detection accuracy is deteriorated and the cleanliness is adversely affected. It is possible to eliminate the risk of giving.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 2 is a second cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a third cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 4 is a fourth cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a first cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the invention.

FIG. 6 is a second cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the invention.

FIG. 7 is a third cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the invention.

FIG. 8 is a fourth cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the invention.

FIG. 9 is a first diagram showing a method of manufacturing a semiconductor device according to a conventional example.
FIG.

FIG. 10 is a second cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional example.

FIG. 11 is a third cross-sectional view showing the method of manufacturing the semiconductor device according to the conventional example.

Claims (3)

[Claims] 1. A step of forming an alignment mark having a step on a semiconductor substrate, a step of forming an interlayer insulating film on the entire surface of the semiconductor substrate, and a step of etching the insulating film to form the alignment mark. A step of forming a groove exposing the mark; a step of planarizing the insulating film by chemical mechanical polishing (CMP); a step of removing polishing debris accumulated in the groove by washing; And a step of performing mask alignment using a mark. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the alignment mark is formed of a polysilicon film. 3. A step of forming an interlayer insulating film on a semiconductor substrate, a step of partially etching the insulating film to form an alignment mark composed of a groove of the insulating film, and a chemical mechanical polishing (CMP). A step of flattening the insulating film by means of, a step of removing polishing debris accumulated in the groove by washing, and a step of performing mask alignment using the alignment mark. Method.