CN103455074A - Band-gap reference circuit and chip - Google Patents

Abstract

The invention belongs to the technical field of an integrated circuit and provides a band-gap reference circuit and a chip. The aim of outputting high-precise band-gap reference voltage is fulfilled by adopting the band-gap reference circuit comprising a current mirror, a dynamic matching logic control module, an error amplifier, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first PNP (Plug N Play) type triode Q1 and a second PNP type triode Q2, performing average current processing on the current mirror to weaken the influence of mismatch of the current mirror and technical diffusion on the band-gap reference voltage through the dynamic matching logic control module, weakening the influence of mismatch of the triodes on the band-gap reference voltage through the first PNP type triode Q1 and the second PNP type triode Q2 which are the same in area of the emitting electrodes, and filtering ripple voltage introduced in a dynamic matching process through a low-pass filter before outputting the band-gap reference voltage.

Description

A kind of band-gap reference circuit and chip

Technical field

The invention belongs to technical field of integrated circuits, relate in particular to a kind of band-gap reference circuit and chip.

Background technology

In chip, reference voltage is provided by band-gap reference circuit, common band-gap reference circuit as shown in Figure 1, wherein, the area of the emitter of positive-negative-positive triode Q2 is N times of positive-negative-positive triode Q1, the number of PMOS pipe P1, PMOS pipe P2 and PMOS pipe P3 is than being 1:1:M, on resistance R 2, produces by positive temperature coefficient (PTC) and negative temperature coefficient by resulting bandgap voltage reference V after weighting summation _bG, in the situation that do not consider that operational amplifier A MP imbalance, PMOS pipe P1, PMOS pipe P2 and PMOS pipe P3 mate (being the current mirror coupling) fully and positive-negative-positive triode Q1 mates fully with positive-negative-positive triode Q2 and positive-negative-positive triode Q3, bandgap voltage reference V _bGbe shown below:

$V_{\mathrm{BG}}=V_{\mathrm{BE}3}+M\·\frac{R2}{R1}{V}_T\·\ln N$

Wherein, V _bE3for the base-emitter voltage of positive-negative-positive triode Q3, V _tfor thermal voltage, V _t=KT/q, K is Boltzmann constant.

Yet, in actual conditions, the problem due to needs consideration device mismatch and technique diffusion, can be affected to precision and the temperature characterisitic of reference voltage, thereby cause obtaining the problem of precision voltage reference.For this problem, prior art is by adopting the chopping modulation technology to eliminate the impact of amplifier imbalance on reference voltage, it specifically utilizes the chopping modulation technology that the voltage signal except offset voltage is modulated to high frequency, and move back to fundamental frequency at the solution timing, offset voltage is modulated to high frequency simultaneously, then by the low pass filter filters out HFS to obtain needed bandgap voltage reference, although this mode can solve the impact of amplifier imbalance on reference voltage, but it can not solve the current mirror mismatch, the problems such as triode mismatch and technique diffusion, therefore, prior art exists because overcoming the current mirror mismatch, triode mismatch and technique diffusion and cause the low problem of precision of bandgap voltage reference.

Summary of the invention

The object of the present invention is to provide a kind of band-gap reference circuit, be intended to solve the existing low problem of precision that causes bandgap voltage reference because overcoming current mirror mismatch, triode mismatch and technique diffusion of prior art.

The present invention is achieved in that a kind of band-gap reference circuit, comprises that the ripple to being mingled with in bandgap voltage reference carries out the low-pass filter of filtering, and described band-gap reference circuit also comprises:

Current mirror, Dynamic Matching Logic control module, error amplifier, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2;

The input end access supply voltage of described current mirror, a plurality of output terminals of described current mirror connect one to one with a plurality of input ends of described Dynamic Matching Logic control module respectively, the quantity of a plurality of output terminals of described current mirror is identical with the quantity of a plurality of input ends of described Dynamic Matching Logic control module, a plurality of control end incoming clock control signals of described Dynamic Matching Logic control module, the control end of described current mirror connects the output terminal of described error amplifier, the emitter of described the first positive-negative-positive triode Q1 and the first output terminal of described Dynamic Matching Logic control module are connected to the inverting input of described error amplifier altogether, the first end of described the first resistance R 1 connects the base stage of described the first positive-negative-positive triode Q1, the collector of the second end of described the first resistance R 1 and described the first positive-negative-positive triode Q1, the collector of the first end of described the second resistance R 2 and described the second positive-negative-positive triode Q2 is connected to ground altogether, the first end of described the second resistance R 2 connects the first end of described the 3rd resistance R 3, the base stage of the second end of described the 3rd resistance R 3 and described the second positive-negative-positive triode Q2 is connected to the second output terminal of described Dynamic Matching Logic control module altogether, the emitter of described the second positive-negative-positive triode Q2 and the in-phase input end of described error amplifier are connected to the first end of described the 4th resistance R 4 altogether, the 3rd output terminal of the second end of described the 4th resistance R 4 and described Dynamic Matching Logic control module is connected to the input end of described low-pass filter altogether, the area of the emitter of described the first positive-negative-positive triode Q1 equals the area of the emitter of described the second positive-negative-positive triode Q2.

Another object of the present invention also is to provide a kind of chip that comprises above-mentioned band-gap reference circuit.

The present invention comprises current mirror by employing, the Dynamic Matching Logic control module, error amplifier, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the band-gap reference circuit of the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2, by the Dynamic Matching Logic control module, current mirror is averaged to current processing to weaken the impact of current mirror mismatch and technique diffusion couple bandgap voltage reference, and by adopting the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2 impact on bandgap voltage reference with weakening triode mismatch that emitter area is identical, and the ripple voltage of introducing in by low pass filter filters out Dynamic Matching process before bandgap voltage reference output, thereby reach the purpose of output high precision bandgap voltage reference, solved prior art existing because overcoming the current mirror mismatch, triode mismatch and technique diffusion and cause the low problem of precision of bandgap voltage reference.

The accompanying drawing explanation

Fig. 1 is the circuit structure diagram of the band-gap reference circuit that provides of prior art;

Fig. 2 is the structural drawing of the band-gap reference circuit that provides of the embodiment of the present invention;

Fig. 3 is the exemplary circuit structural drawing of the band-gap reference circuit that provides of the embodiment of the present invention;

Fig. 4 is the sequential chart of the related category-A clock control signal of the band-gap reference circuit that provides of the embodiment of the present invention;

Fig. 5 is the sequential chart of the related category-B clock control signal of the band-gap reference circuit that provides of the embodiment of the present invention;

Fig. 6 is the sequential chart of the related C class clock control signal of the band-gap reference circuit that provides of the embodiment of the present invention;

Fig. 7 is the equivalent circuit diagram of the band-gap reference circuit that provides of the embodiment of the present invention;

Fig. 8 is the equivalent circuit diagram of the band-gap reference circuit that provides of other embodiments of the invention.

Embodiment

In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.

The embodiment of the present invention comprises current mirror by employing, the Dynamic Matching Logic control module, error amplifier, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the band-gap reference circuit of the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2, by the Dynamic Matching Logic control module, current mirror is averaged to current processing to weaken the impact of current mirror mismatch and technique diffusion couple bandgap voltage reference, and by adopting the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2 impact on bandgap voltage reference with weakening triode mismatch that emitter area is identical, and the ripple voltage of introducing in by low pass filter filters out Dynamic Matching process before bandgap voltage reference output, thereby reach the purpose of output high precision bandgap voltage reference.

Fig. 2 shows the structure of the band-gap reference circuit that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention, and details are as follows:

Band-gap reference circuit comprises that the ripple to being mingled with in bandgap voltage reference carries out the low-pass filter 300 of filtering, and this band-gap reference circuit also comprises current mirror 100, Dynamic Matching Logic control module 200, error amplifier EA, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2.

The input end access supply voltage VDD of current mirror 100, a plurality of output terminals of current mirror 100 connect one to one with a plurality of input ends of Dynamic Matching Logic control module 200 respectively, the quantity of a plurality of output terminals of current mirror 100 is identical with the quantity of a plurality of input ends of Dynamic Matching Logic control module 200, a plurality of control end incoming clock control signals of Dynamic Matching Logic control module 200, the control end of current mirror 100 connects the output terminal of error amplifier EA, the first output terminal OUT1 of the emitter of the first positive-negative-positive triode Q1 and Dynamic Matching Logic control module 200 be connected to altogether the inverting input of error amplifier EA-, the first end of the first resistance R 1 connects the base stage of the first positive-negative-positive triode Q1, the collector of the second end of the first resistance R 1 and the first positive-negative-positive triode Q1, the collector of the first end of the second resistance R 2 and the second positive-negative-positive triode Q2 is connected to ground altogether, the first end of the second resistance R 2 connects the first end of described the 3rd resistance R 3, the base stage of the second end of described the 3rd resistance R 3 and described the second positive-negative-positive triode Q2 is connected to the second output terminal OUT2 of described Dynamic Matching Logic control module altogether, the emitter of described the second positive-negative-positive triode Q2 and the in-phase input end of error amplifier EA+be connected to the altogether first end of the 4th resistance R 4, the 3rd output terminal OUT3 of the second end of the 4th resistance R 4 and Dynamic Matching Logic control module 200 is connected to the input end of low-pass filter 300 altogether, the area of the emitter of the first positive-negative-positive triode Q1 equals the area of the emitter of the second positive-negative-positive triode Q2.

In above-mentioned band-gap reference circuit, the feedback loop that error amplifier EA and Dynamic Matching Logic control module 200 form provides bias voltage for current mirror 100, Dynamic Matching Logic control module 200 is for controlling the output of current mirror 100 different current paths, current mirror 100 provides emitter current by Dynamic Matching Logic control module 200 for the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2, and current mirror 100 is by Dynamic Matching Logic control module 200 output bandgap voltage references, the first resistance R 1, the second resistance R 2 and the 3rd resistance R 3 are used to the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2 to produce bias current, the 4th resistance R 4 is for finely tuning the consistance of bandgap voltage reference with the reference voltage that guarantees different chips, the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2 produce respectively the base-emitter voltage with negative temperature coefficient, the emitter current of the second positive-negative-positive triode Q2 equals the current value of unit current source, 300 pairs of bandgap voltage references of low-pass filter carry out after the ripple voltage filtering is processed exporting high-precision bandgap voltage reference.

Fig. 3 shows the exemplary circuit structure of the band-gap reference circuit that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention, and details are as follows:

As one embodiment of the present invention, current mirror 100 comprises:

The one PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7 and the 8th PMOS pipe P8;

The source electrode of the source electrode of the one PMOS pipe P1 and the 2nd PMOS pipe P2, the source electrode of the 3rd PMOS pipe P3, the source electrode of the 4th PMOS pipe P4, the source electrode of the 5th PMOS pipe P5, the source electrode of the 6th PMOS pipe P6, the source electrode of the source electrode of the 7th PMOS pipe P7 and the 8th PMOS pipe P8 connects formed contact altogether altogether as the input end of current mirror 100, the grid of the grid of a PMOS pipe P1 and the 2nd PMOS pipe P2, the grid of the 3rd PMOS pipe P3, the grid of the 4th PMOS pipe P4, the grid of the 5th PMOS pipe P5, the grid of the 6th PMOS pipe P6, the grid of the grid of the 7th PMOS pipe P7 and the 8th PMOS pipe P8 connects formed contact altogether altogether as the control end of current mirror 100, the drain electrode of the drain electrode of a PMOS pipe P1 and the 2nd PMOS pipe P2, the drain electrode of the 3rd PMOS pipe P3, the drain electrode of the 4th PMOS pipe P4, the drain electrode of the 5th PMOS pipe P5, the drain electrode of the 6th PMOS pipe P6, the drain electrode of the drain electrode of the 7th PMOS pipe P7 and the 8th PMOS pipe P8 is respectively the first output terminal of current mirror 100, the second output terminal, the 3rd output terminal, the 4th output terminal, the 5th output terminal, the 6th output terminal, the 7th output terminal and the 8th output terminal.

As one embodiment of the present invention, Dynamic Matching Logic control module 200 comprises:

The 9th PMOS pipe P9, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 19 PMOS pipe P19, the 20 PMOS pipe P20, the 21 PMOS pipe P21, the 22 PMOS pipe P22, the 23 PMOS pipe P23, the 24 PMOS pipe P24, the 25 PMOS pipe P25, the 26 PMOS pipe P26, the 27 PMOS pipe P27, the 28 PMOS pipe P28, the 29 PMOS pipe P29, the 30 PMOS pipe P30, the 31 PMOS pipe P31 and the 32 PMOS pipe P32,

The source electrode of the 9th PMOS pipe P9, the formed first input end IN1 that contact is Dynamic Matching Logic control module 200 altogether of source electrode of the source electrode of the tenth PMOS pipe P10 and the 11 PMOS pipe P11, the source electrode of the 12 PMOS pipe P12, formed the second input end IN2 that contact is Dynamic Matching Logic control module 200 altogether of source electrode of the source electrode of the 13 PMOS pipe P13 and the 14 PMOS pipe P14, the source electrode of the 15 PMOS pipe P15, formed the 3rd input end IN3 that contact is Dynamic Matching Logic control module 200 altogether of source electrode of the source electrode of the 16 PMOS pipe P16 and the 17 PMOS pipe P17, the source electrode of the 18 PMOS pipe P18, the formed four-input terminal IN4 that contact is Dynamic Matching Logic control module 200 altogether of source electrode of the source electrode of the 19 PMOS pipe P19 and the 20 PMOS pipe P20, the source electrode of the 21 PMOS pipe P21, formed the 5th input end IN5 that contact is Dynamic Matching Logic control module 200 altogether of source electrode of the source electrode of the 22 PMOS pipe P22 and the 23 PMOS pipe P23, the source electrode of the 24 PMOS pipe P24, formed the 6th input end IN6 that contact is Dynamic Matching Logic control module 200 altogether of source electrode of the source electrode of the 25 PMOS pipe P25 and the 26 PMOS pipe P26, the source electrode of the 27 PMOS pipe P27, formed the 7th input end IN7 that contact is Dynamic Matching Logic control module 200 altogether of source electrode of the source electrode of the 28 PMOS pipe P28 and the 29 PMOS pipe P29, the source electrode of the 30 PMOS pipe P30, formed the 8th input end IN8 that contact is Dynamic Matching Logic control module 200 altogether of source electrode of the source electrode of the 31 PMOS pipe P31 and the 32 PMOS pipe P32, the first input end of Dynamic Matching Logic control module 200, the second input end, the 3rd input end, four-input terminal, the 5th input end, the 6th input end, the 7th input end and the 8th input end connect respectively the first output terminal of current mirror 100, the second output terminal, the 3rd output terminal, the 4th output terminal, the 5th output terminal, the 6th output terminal, the 7th output terminal and the 8th output terminal.

The grid of the 9th PMOS pipe P9, the grid of the 12 PMOS pipe P12, the grid of the 15 PMOS pipe P15, the grid of the 18 PMOS pipe P18, the grid of the 21 PMOS pipe P21, the grid of the 24 PMOS pipe P24, the grid of the grid of the 27 PMOS pipe P27 and the 30 PMOS pipe P30 accesses respectively the first category-A clock control signal CKA1, the second category-A clock control signal CKA2, the 3rd category-A clock control signal CKA3, the 4th category-A clock control signal CKA4, the 5th category-A clock control signal CKA5, the 6th category-A clock control signal CKA6, the 7th category-A clock control signal CKA7 and the 8th category-A clock control signal CKA8, the grid of the 13 PMOS pipe P13, the grid of the 19 PMOS pipe P19, the grid of the 16 PMOS pipe P16, the grid of the 22 PMOS pipe P22, the grid of the 25 PMOS pipe P25, the grid of the 28 PMOS pipe P28, the grid of the grid of the 31 PMOS pipe P31 and the tenth PMOS pipe P10 accesses respectively the first category-B clock control signal CKB1, the second category-B clock control signal CKB2, the 3rd category-B clock control signal CKB3, the 4th category-B clock control signal CKB4, the 5th category-B clock control signal CKB5, the 6th category-B clock control signal CKB6, the 7th category-B clock control signal CKB7 and the 8th category-B clock control signal CKB8, the grid of the 23 PMOS pipe P23, the grid of the 26 PMOS pipe P26, the grid of the 29 PMOS pipe P29, the grid of the 32 PMOS pipe P32, the grid of the 11 PMOS pipe P11, the grid of the 14 PMOS pipe P14, the grid of the grid of the 17 PMOS pipe P17 and the 20 PMOS pipe P20 accesses respectively a C class clock control signal CKC1, the 2nd C class clock control signal CKC2, the 3rd C class clock control signal CKC3, the 4th C class clock control signal CKC4, the 5th C class clock control signal CKC5, the 6th C class clock control signal CKC6, the 7th C class clock control signal CKC7 and the 8th C class clock control signal CKC8, the drain electrode of the 9th PMOS pipe P9, the drain electrode of the 12 PMOS pipe P12, the drain electrode of the 15 PMOS pipe P15, the drain electrode of the 18 PMOS pipe P18, the drain electrode of the 21 PMOS pipe P21, the drain electrode of the 24 PMOS pipe P24, the formed contact altogether of the drain electrode of the drain electrode of the 27 PMOS pipe P27 and the 30 PMOS pipe P30 is as the 3rd output terminal OUT3 of Dynamic Matching Logic control module 200, and the tenth PMOS manages the drain electrode of P10, the drain electrode of the 13 PMOS pipe P13, the drain electrode of the 19 PMOS pipe P19, the drain electrode of the 16 PMOS pipe P16, the drain electrode of the 22 PMOS pipe P22, the drain electrode of the 25 PMOS pipe P25, the formed contact altogether of the drain electrode of the drain electrode of the 28 PMOS pipe P28 and the 31 PMOS pipe P31 is as the first output terminal OUT1 of Dynamic Matching Logic control module 200, and the 11 PMOS manages the drain electrode of P11, the drain electrode of the 14 PMOS pipe P14, the drain electrode of the 17 PMOS pipe P17, the drain electrode of the 20 PMOS pipe P20, the drain electrode of the 23 PMOS pipe P23, the drain electrode of the 26 PMOS pipe P26, the formed contact altogether of the drain electrode of the drain electrode of the 29 PMOS pipe P29 and the 32 PMOS pipe P32 is as the second output terminal OUT2 of Dynamic Matching Logic control module 200.

Wherein, as shown in Figure 4, the first category-A clock control signal CKA1, the second category-A clock control signal CKA2, the 3rd category-A clock control signal CKA3, the 4th category-A clock control signal CKA4, the 5th category-A clock control signal CKA5, the 6th category-A clock control signal CKA6, the 7th category-A clock control signal CKA7 and the 8th category-A clock control signal CKA8 are all clock signals that dutycycle is 87.5%, and be the Low level effective conducting to the PMOS pipe, the second category-A clock control signal CKA2 is time delay T/8 with respect to 1/8 signal period T(of the first category-A clock control signal CKA1 time delay), the 3rd category-A clock control signal CKA3 is time delay T/8 with respect to 1/8 signal period T(of the second category-A clock control signal CKA2 time delay), the 4th category-A clock control signal CKA4 is time delay T/8 with respect to 1/8 signal period T(of the 3rd category-A clock control signal CKA3 time delay), the 5th category-A clock control signal CKA5 is time delay T/8 with respect to 1/8 signal period T(of the 4th category-A clock control signal CKA4 time delay), the 6th category-A clock control signal CKA6 is time delay T/8 with respect to 1/8 signal period T(of the 5th category-A clock control signal CKA5 time delay), the 7th category-A clock control signal CKA7 is time delay T/8 with respect to 1/8 signal period T(of the 6th category-A clock control signal CKA6 time delay), the 8th category-A clock control signal CKA8 is time delay T/8 with respect to 1/8 signal period T(of the 7th category-A clock control signal CKA7 time delay).

As shown in Figure 5, the first category-B clock control signal CKB1, the second category-B clock control signal CKB2, the 3rd category-B clock control signal CKB3, the 4th category-B clock control signal CKB4, the 5th category-B clock control signal CKB5, the 6th category-B clock control signal CKB6, the 7th category-B clock control signal CKB7 and the 8th category-B clock control signal CKB8 are all clock signals that dutycycle is 62.5%, and be the Low level effective conducting to the PMOS pipe, the second category-B clock control signal CKB2 is time delay T/8 with respect to 1/8 signal period T(of the first category-B clock control signal CKB1 time delay), the 3rd category-B clock control signal CKB3 is time delay T/8 with respect to 1/8 signal period T(of the second category-B clock control signal CKB2 time delay), the 4th category-B clock control signal CKB4 is time delay T/8 with respect to 1/8 signal period T(of the 3rd category-B clock control signal CKB3 time delay), the 5th category-B clock control signal CKB5 is time delay T/8 with respect to 1/8 signal period T(of the 4th category-B clock control signal CKB4 time delay), the 6th category-B clock control signal CKB6 is time delay T/8 with respect to 1/8 signal period T(of the 5th category-B clock control signal CKB5 time delay), the 7th category-B clock control signal CKB7 is time delay T/8 with respect to 1/8 signal period T(of the 6th category-B clock control signal CKB6 time delay), the 8th category-B clock control signal CKB8 is time delay T/8 with respect to 1/8 signal period T(of the 7th category-B clock control signal CKB7 time delay).

As shown in Figure 6, the one C class clock control signal CKC1, the 2nd C class clock control signal CKC2, the 3rd C class clock control signal CKC3, the 4th C class clock control signal CKC4, the 5th C class clock control signal CKC5, the 6th C class clock control signal CKC6, the 7th C class clock control signal CKC7 and the 8th C class clock control signal CKC8 are all clock signals that dutycycle is 50%, and be the Low level effective conducting to the PMOS pipe, the 2nd C class clock control signal CKC2 is time delay T/8 with respect to 1/8 signal period T(of a C class clock control signal CKC1 time delay), the 3rd category-B clock control signal CKC3 is time delay T/8 with respect to 1/8 signal period T(of the 2nd C class clock control signal CKC2 time delay), the 4th C class clock control signal CKC4 is time delay T/8 with respect to 1/8 signal period T(of the 3rd C class clock control signal CKC3 time delay), the 5th C class clock control signal CKC5 is time delay T/8 with respect to 1/8 signal period T(of the 4th C class clock control signal CKC4 time delay), the 6th C class clock control signal CKC6 is time delay T/8 with respect to 1/8 signal period T(of the 5th C class clock control signal CKC5 time delay), the 7th C class clock control signal CKC7 is time delay T/8 with respect to 1/8 signal period T(of the 6th C class clock control signal CKC6 time delay), the 8th C class clock control signal CKC8 is time delay T/8 with respect to 1/8 signal period T(of the 7th C class clock control signal CKC7 time delay).

As one embodiment of the present invention, the 4th resistance R 4 can be specifically the adjustable adjustable resistance of resistance value.

In embodiments of the present invention, low-pass filter 300 is low-pass filter circuit commonly used, and it is for the ripple voltage of filtering high frequency.

Below in conjunction with principle of work, above-mentioned band-gap reference circuit is described further:

Dynamic Matching Logic control module 200 is within the same time, in eight clock control signals of CKA1～CKA8, only have one for low level, with one of them PMOS controlled in eight PMOS pipes such as P9, P12, P15, P18, P21, P24, P27 and P30, to manage conducting output current, this electric current is by the 3rd output terminal OUT3 output of Dynamic Matching Logic control module 200; In eight clock control signals of CKB1～CKB8, have three for low level, with three PMOS that control in eight PMOS pipes such as P13, P19, P16, P22, P25, P28, P31 and P10, to manage conducting output current, this electric current is by the first output terminal OUT1 output of Dynamic Matching Logic control module 200; In eight clock control signals of CKC1～CKC8, have four for low level, with four PMOS that control in eight PMOS pipes such as P23, P26, P29, P32, P11, P14, P17 and P20, to manage conducting output current, this electric current is by the second output terminal OUT2 output of Dynamic Matching Logic control module 200.So, in at the same time, by a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, PMOS in the current mirror 100 that the 7th PMOS pipe P7 and the 8th PMOS pipe P8 form manages whole conductings, wherein, the On current of the one PMOS pipe P1 flows out by the 3rd output port OUT3 of Dynamic Matching Logic control module 200, the On current of the 2nd PMOS pipe P2, the On current of the On current of the 3rd PMOS pipe P3 and the 4th PMOS pipe P4 flows out by the first output terminal OUT1 of Dynamic Matching Logic control module 200, the On current of the 5th PMOS pipe P5, the On current of the 6th PMOS pipe P6, the On current of the On current of the 7th PMOS pipe P7 and the 8th PMOS pipe P8 flows out by the second output terminal OUT2 of Dynamic Matching Logic control module 200, now, the equivalent circuit diagram of the band-gap reference circuit shown in Fig. 3 as shown in Figure 7, therefore, bandgap voltage reference V _rEFbe shown below:

$V_{\mathrm{REF}}=\frac{I(R_2+R_3)}{1+{\mathrm{\β}}_F}+4I(R_2+R_3){+\mathrm{IR}}_4+V_{\mathrm{BE}2}---\left(1\right)$

In above formula, β _ffor the common emitter current gain of positive-negative-positive triode, the On current that I is the unitary current mirror that in current mirror 100, every two PMOS pipe forms, also be called unitary current, R ₂, R ₃and R ₄be respectively the resistance of the second resistance R 2, the resistance of the 3rd resistance R 3 and the resistance of the 4th resistance R 4, V _bE2base-emitter voltage for positive-negative-positive triode Q2.

The voltage difference delta V of the base-emitter voltage of the base-emitter voltage of positive-negative-positive triode Q1 and positive-negative-positive triode Q2 _bEbe shown below:

ΔV _BE=12IR ₁ (2)

Because positive-negative-positive triode Q1 and positive-negative-positive triode Q2 are operated under different current densities, so according to Δ V _bEwith the proportional following formula that draws of absolute temperature T:

$\mathrm{\&Delta;}{V}_{\mathrm{BE}}=12I{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA0000373626660000011.png,HDA0000373626660000042.png"\; state="\{\{state\}\}">R</figure-callout>}}_1=\frac{\mathrm{kT}}{q}\&times;\ln 3---\left(3\right)$

Wherein, R ₁be the resistance of the first resistance R 1, and the ratio of the resistance of the resistance of the first resistance R 1 and the second resistance R 2 and the 3rd resistance R 3 is 1:2:1, can makes like this chip layout layout better effects if.

Can obtain following formula from above formula (3):

$I=\frac{\mathrm{kT}}{12\mathrm{<figure-callout\; id="1"\; label="q\; R"\; filenames="HDA0000373626660000011.png,HDA0000373626660000042.png"\; state="\{\{state\}\}">q</figure-callout>}{R}_{}{}_1}\&times;\ln 3---\left(4\right)$

In relational expression (1),

4I (R ₂+ R ₃) and IR ₄for positive temperature coefficient (PTC), V _bE2for negative temperature coefficient, can obtain the bandgap voltage reference of the zero-temperature coefficient at a certain temperature through weighting summation.

In actual chip manufacturing proces, the coupling of the PMOS pipe in current mirror 100 can cause Δ V usually _bEerror, suppose that the current mirror ratio in current mirror 100 is 1:p, i.e. total p+1 current source has following relational expression:

I _i=I(1+δ _i)，(1≤i≤p+1) （5）

In above formula (5), δ _ibe the correlated error of i current source and I, and have

if j current mirror is used to produce unitary current, the current ratio produced as shown in the formula:

$\frac{{\mathrm{\&Sigma;}}_{i\&NotEqual;j}{I}_i}{I_j}=\frac{{\mathrm{\&Sigma;}}_{i=1}^{p+1}\left(I_i\right)-I_j}{I_j}=p\frac{1-{\mathrm{\&delta;}}_j/\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="HDA0000373626660000011.png,HDA0000373626660000042.png"\; state="\{\{state\}\}">p</figure-callout>}}{1+{\mathrm{\&delta;}}_j}=p+\mathrm{\&Delta;}{p}_j---\left(6\right)$

The correlated error that this current mirror ratio produces is:

$\frac{\mathrm{\&Delta;}{p}_j}{p}=-\frac{p+1}{p}\frac{{\mathrm{\&delta;}}_{\mathrm{<figure-callout\; id="1"\; label="j"\; filenames="HDA0000373626660000011.png,HDA0000373626660000042.png"\; state="\{\{state\}\}">j</figure-callout>}}}{1+{\mathrm{\&delta;}}_j}\&ap;-\frac{p+1}{p}{\mathrm{\&delta;}}_j,({\mathrm{\&delta;}}_j<<1)---\left(7\right)$

To Δ V _{bE, j}the error produced can be expressed as:

$\mathrm{\&Delta;}{V}_{\mathrm{BE},j}-{\mathrm{\&Delta;V}}_{\mathrm{BE}}{|}_{\mathrm{\&Delta;p}=0}=\frac{\mathrm{kT}}{q}\ln (p+\mathrm{\&Delta;}{p}_j)-\frac{\mathrm{kT}}{q}\ln \left(p\right)$

$=\frac{\mathrm{kT}}{q}\ln (1+\frac{\mathrm{\&Delta;}{p}_j}{p})\&ap;\frac{\mathrm{kT}}{q}\frac{\mathrm{\&Delta;}{p}_j}{p}=-\frac{\mathrm{kT}}{q}\frac{p+1}{p}{\mathrm{\&delta;}}_j---\left(8\right)$

Therefore each current mirror in the embodiment of the present invention has adopted Dynamic Matching technique guarantee p+1 current mirror is used as producing unitary current, the Δ V that produced _bEto average out, therefore, first-order error will be eliminated, and in order to assess the second order error in mean value, utilize formula ln (1+ δ)=δ-δ ²/ 2+O (Δ p ³) rewrite above formula (8) and be:

In the situation that ignore three rank and the error of high-order more, the expression formula of average error can be written as:

${\mathrm{\&Delta;V}}_{\mathrm{BE},\mathrm{avg}}-{\mathrm{\&Delta;V}}_{\mathrm{BE}}{|}_{\mathrm{\&Delta;p}=0}=\frac{1}{p+1}\frac{\mathrm{kT}}{q}\underset{j=1}{\overset{p+1}{\mathrm{\&Sigma;}}}(\frac{\mathrm{\&Delta;}{p}_j}{p}-\frac{1}{2}{\left(\frac{\mathrm{\&Delta;}{p}_j}{p}\right)}^2)=\frac{1}{2(p+1)}\frac{\mathrm{kT}}{q}\underset{j=1}{\overset{p+1}{\mathrm{\&Sigma;}}}{\left(\frac{\mathrm{\&Delta;}{p}_j}{p}\right)}^2---\left(10\right)$

If | Δ p _j/ p|≤Δ p/p, average error will be limited in following scope:

$|{\mathrm{\&Delta;V}}_{\mathrm{BE},\mathrm{avg}}-{\mathrm{\&Delta;V}}_{\mathrm{BE}}{|}_{\mathrm{\&Delta;p}=0}|<\frac{1}{2}\&times;\frac{\mathrm{kT}}{q}\&times;{\left(\frac{\mathrm{\&Delta;p}}{p}\right)}^2---\left(11\right)$

If $\frac{\mathrm{\&Delta;p}}{p}=1\%,$ P=3:

$\frac{|{\mathrm{\&Delta;V}}_{\mathrm{BE},\mathrm{avg}}-{\mathrm{\&Delta;V}}_{\mathrm{BE}}{|}_{\mathrm{\&Delta;p}=0}|}{{\mathrm{\&Delta;V}}_{\mathrm{BE}}{|}_{\mathrm{\&Delta;p}=0}}<\frac{\frac{1}{2}\&times;\frac{\mathrm{kT}}{q}{\&times;\left(\frac{\mathrm{\&Delta;p}}{p}\right)}^2}{\frac{\mathrm{kT}}{q}\&times;\ln p}=0.005\%$

If do not adopt Dynamic Matching, in the situation that the current mirror ratio is still 1:p, the emitter current of positive-negative-positive triode Q1 and Q2 meeting mismatch, Δ p is to Δ V _bEimpact be:

${\mathrm{\&Delta;V}}_{\mathrm{BE}\_I\_\mathrm{mismatch}}=\frac{\mathrm{kT}}{q}\ln (p+\mathrm{\&Delta;p})\&ap;\frac{\mathrm{kT}}{q}\ln \left(p\right)\&CenterDot;(1+\frac{\mathrm{\&Delta;p}}{p\ln p}),(\mathrm{\&Delta;p}<<p)---\left(12\right)$

So, Δ V _bEerror be:

${\mathrm{\&Delta;V}}_{\mathrm{BE}}-{\mathrm{\&Delta;V}}_{\mathrm{BE}}{|}_{\mathrm{\&Delta;p}=0}=\frac{\mathrm{kT}}{q}\&times;\frac{\mathrm{\&Delta;p}}{p}---\left(13\right)$

That is:

$\frac{\mathrm{\&Delta;}{V}_{\mathrm{BE}}-{\mathrm{\&Delta;V}}_{\mathrm{BE}}{|}_{\mathrm{\&Delta;p}=0}}{{\mathrm{\&Delta;V}}_{\mathrm{BE}}}=\frac{\frac{\mathrm{kT}}{q}\&times;\frac{\mathrm{\&Delta;p}}{p}}{\frac{\mathrm{kT}}{q}\ln p}=\frac{\mathrm{\&Delta;p}}{p\&times;\ln p}---\left(14\right)$

If $\frac{\mathrm{\&Delta;p}}{p}=1\%,$ P=3:

$\frac{\mathrm{\&Delta;}{V}_{\mathrm{BE}}-\mathrm{\&Delta;}{V}_{\mathrm{BE}}{|}_{\mathrm{\&Delta;p}=0}}{\mathrm{\&Delta;}{V}_{\mathrm{BE}}}=\frac{\mathrm{\&Delta;p}}{p\&times;\ln p}=0.3\%$

From above-mentioned derivation, adopt the band-gap reference circuit based on the Dynamic Matching technology of the embodiment of the present invention can effectively weaken the impact of current mirror mismatch on bandgap voltage reference.

In embodiments of the present invention, the realization of the Dynamic Matching function of Dynamic Matching Logic control module 200 is to be controlled the break-make of the PMOS pipe in Dynamic Matching Logic control module 200 by clock control signal, break-make by controlling each PMOS pipe in Dynamic Matching Logic control module 200 is to select the flow direction of 100 output currents of current mirror, by as Fig. 4, the clock control signal of Fig. 5 and Fig. 6 is realized corresponding sequential control to Dynamic Matching Logic control module 200, can guarantee in the different time, the electric current of three current mirrors is arranged successively by the first output terminal OUT1 outflow of Dynamic Matching Logic control module 200 in eight PMOS pipes in current mirror 100, the electric current of four current mirrors is arranged successively by the second output terminal OUT2 outflow of Dynamic Matching Logic control module 200, the electric current of a current mirror is arranged by the 3rd output terminal OUT3 outflow of Dynamic Matching Logic control module 200, the emitter current that guarantees positive-negative-positive triode Q1 and positive-negative-positive triode Q1 has been used the electric current of all cell current mirrors in current mirror 100 successively, the the first output terminal OUT1 that namely is equivalent to Dynamic Matching Logic control module 200, the second output terminal OUT2, the output current of the 3rd output terminal OUT3 has an average effect in Long time scale, making also has an average effect because of the different bandgap voltage references that the current mirror mismatch produces, thereby weaken the impact that the current mirror mismatch causes bandgap voltage reference, the ripple voltage of finally introducing because of Dynamic Matching by low-pass filter 300 filterings is to obtain final average bandgap reference voltage.

In the band-gap reference circuit provided in the embodiment of the present invention, positive-negative-positive triode Q1 is identical with the emitter area of positive-negative-positive triode Q2, therefore can adopt rational triode number so that chip layout when design adopts the common centroid layout, thereby can effectively eliminate the impact that the triode mismatch is brought the precision of bandgap voltage reference.

In sum, the band-gap reference circuit based on the Dynamic Matching technology provided by the embodiment of the present invention, the impact that the precision of current mirror mismatch, triode mismatch and technique diffusion couple bandgap voltage reference is brought can be effectively reduced, thereby high precision, high conforming bandgap voltage reference can be accessed.

In embodiments of the present invention, the current mirror 100 that adopts eight PMOS pipes to form is to make under consideration optimal cases (comprising the best effort interval of circuit realization, chip layout layout, triode etc.).And in other embodiments of the invention, the quantity of the PMOS pipe in current mirror 100 can be got other value, and with other parameter correlation in band-gap reference circuit, equivalent circuit diagram as shown in Figure 8, the electric current that flows through the emitter of positive-negative-positive triode Q2 is got the i.e. unitary current of a current mirror of I(), it is h the total current that current mirror is exported that the electric current that flows through the emitter of positive-negative-positive triode Q1 is got h * I(), the electric current that flow to the base stage that flows through positive-negative-positive triode Q2 is m * I (being m the total current that current mirror is exported), R ₁=R ₃, R ₂/ R ₁=h-1, i.e. the desirable any number that is greater than 2 of h, R ₂/ R ₁ratio also can be thereupon different; For guaranteeing chip layout coupling, R ₂/ R ₁generally get even number 2,4 or 6 etc., now, the electric current I of unitary current mirror is:

$\frac{\ln h}{h\&times;m{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA0000373626660000011.png,HDA0000373626660000042.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}\&times;\frac{\mathrm{kT}}{q}---\left(15\right)$

In above formula (15), q is the electric charge constant, and k is Boltzmann constant, and T is absolute temperature.

In the quantity that meets the PMOS pipe under above-mentioned condition, be all feasible, its principle is also identical with the principle of 8 PMOS pipes of employing in current mirror 100.(h+m+1) individual clock pulse signal of each class in three class clock control signals in Dynamic Matching Logic control module 200 (category-A, category-B and C class), when if the delay time of adjacent two clock pulse signals is respectively T/4, T/8 and T/16, the quantity of the PMOS pipe in current mirror 100 correspondingly is respectively 4,8 and 16, then in conjunction with R ₂/ R ₁value can obtain the value of h, and and then the value of definite m, thereby reach the purpose of Dynamic Matching.

The embodiment of the present invention also provides a kind of chip that comprises above-mentioned band-gap reference circuit.

The embodiment of the present invention comprises current mirror by employing, the Dynamic Matching Logic control module, error amplifier, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the band-gap reference circuit of the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2, by the Dynamic Matching Logic control module, current mirror is averaged to current processing to weaken the impact of current mirror mismatch and technique diffusion couple bandgap voltage reference, and by adopting the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2 impact on bandgap voltage reference with weakening triode mismatch that emitter area is identical, and the ripple voltage of introducing in by low pass filter filters out Dynamic Matching process before bandgap voltage reference output, thereby reach the purpose of output high precision bandgap voltage reference, solved prior art existing because overcoming the current mirror mismatch, triode mismatch and technique diffusion and cause the low problem of precision of bandgap voltage reference.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.

Claims (8)

1. a band-gap reference circuit, comprise that the ripple to being mingled with in bandgap voltage reference carries out the low-pass filter of filtering, it is characterized in that, described band-gap reference circuit also comprises:

Current mirror, Dynamic Matching Logic control module, error amplifier, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2;

The input end access supply voltage of described current mirror, a plurality of output terminals of described current mirror connect one to one with a plurality of input ends of described Dynamic Matching Logic control module respectively, the quantity of a plurality of output terminals of described current mirror is identical with the quantity of a plurality of input ends of described Dynamic Matching Logic control module, a plurality of control end incoming clock control signals of described Dynamic Matching Logic control module, the control end of described current mirror connects the output terminal of described error amplifier, the emitter of described the first positive-negative-positive triode Q1 and the first output terminal of described Dynamic Matching Logic control module are connected to the inverting input of described error amplifier altogether, the first end of described the first resistance R 1 connects the base stage of described the first positive-negative-positive triode Q1, the collector of the second end of described the first resistance R 1 and described the first positive-negative-positive triode Q1, the collector of the first end of described the second resistance R 2 and described the second positive-negative-positive triode Q2 is connected to ground altogether, the first end of described the second resistance R 2 connects the first end of described the 3rd resistance R 3, the base stage of the second end of described the 3rd resistance R 3 and described the second positive-negative-positive triode Q2 is connected to the second output terminal of described Dynamic Matching Logic control module altogether, the emitter of described the second positive-negative-positive triode Q2 and the in-phase input end of described error amplifier are connected to the first end of described the 4th resistance R 4 altogether, the 3rd output terminal of the second end of described the 4th resistance R 4 and described Dynamic Matching Logic control module is connected to the input end of described low-pass filter altogether, the area of the emitter of described the first positive-negative-positive triode Q1 equals the area of the emitter of described the second positive-negative-positive triode Q2.

2. band-gap reference circuit as claimed in claim 1, is characterized in that, described current mirror comprises:

The one PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7 and the 8th PMOS pipe P8;

The source electrode of the source electrode of a described PMOS pipe P1 and described the 2nd PMOS pipe P2, the source electrode of described the 3rd PMOS pipe P3, the source electrode of described the 4th PMOS pipe P4, the source electrode of described the 5th PMOS pipe P5, the source electrode of described the 6th PMOS pipe P6, the source electrode of the source electrode of described the 7th PMOS pipe P7 and described the 8th PMOS pipe P8 connects formed contact altogether altogether as the input end of described current mirror, the grid of the grid of a described PMOS pipe P1 and described the 2nd PMOS pipe P2, the grid of described the 3rd PMOS pipe P3, the grid of described the 4th PMOS pipe P4, the grid of described the 5th PMOS pipe P5, the grid of described the 6th PMOS pipe P6, the grid of the grid of described the 7th PMOS pipe P7 and described the 8th PMOS pipe P8 connects formed contact altogether altogether as the control end of described current mirror, the drain electrode of the drain electrode of a described PMOS pipe P1 and described the 2nd PMOS pipe P2, the drain electrode of described the 3rd PMOS pipe P3, the drain electrode of described the 4th PMOS pipe P4, the drain electrode of described the 5th PMOS pipe P5, the drain electrode of described the 6th PMOS pipe P6, the drain electrode of the drain electrode of described the 7th PMOS pipe P7 and described the 8th PMOS pipe P8 is respectively the first output terminal of described current mirror, the second output terminal, the 3rd output terminal, the 4th output terminal, the 5th output terminal, the 6th output terminal, the 7th output terminal and the 8th output terminal.

3. band-gap reference circuit as claimed in claim 2, is characterized in that, described Dynamic Matching Logic control module comprises:

The 9th PMOS pipe P9, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 19 PMOS pipe P19, the 20 PMOS pipe P20, the 21 PMOS pipe P21, the 22 PMOS pipe P22, the 23 PMOS pipe P23, the 24 PMOS pipe P24, the 25 PMOS pipe P25, the 26 PMOS pipe P26, the 27 PMOS pipe P27, the 28 PMOS pipe P28, the 29 PMOS pipe P29, the 30 PMOS pipe P30, the 31 PMOS pipe P31 and the 32 PMOS pipe P32,

The source electrode of described the 9th PMOS pipe P9, the formed first input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the tenth PMOS pipe P10 and described the 11 PMOS pipe P11, the source electrode of described the 12 PMOS pipe P12, formed the second input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 13 PMOS pipe P13 and described the 14 PMOS pipe P14, the source electrode of described the 15 PMOS pipe P15, formed the 3rd input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 16 PMOS pipe P16 and described the 17 PMOS pipe P17, the source electrode of described the 18 PMOS pipe P18, the formed four-input terminal that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 19 PMOS pipe P19 and described the 20 PMOS pipe P20, the source electrode of described the 21 PMOS pipe P21, formed the 5th input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 22 PMOS pipe P22 and described the 23 PMOS pipe P23, the source electrode of described the 24 PMOS pipe P24, formed the 6th input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 25 PMOS pipe P25 and described the 26 PMOS pipe P26, the source electrode of described the 27 PMOS pipe P27, formed the 7th input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 28 PMOS pipe P28 and described the 29 PMOS pipe P29, the source electrode of described the 30 PMOS pipe P30, formed the 8th input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 31 PMOS pipe P31 and described the 32 PMOS pipe P32, the first input end of described Dynamic Matching Logic control module, the second input end, the 3rd input end, four-input terminal, the 5th input end, the 6th input end, the 7th input end and the 8th input end connect respectively the first output terminal of described current mirror, the second output terminal, the 3rd output terminal, the 4th output terminal, the 5th output terminal, the 6th output terminal, the 7th output terminal and the 8th output terminal,

The grid of described the 9th PMOS pipe P9, the grid of described the 12 PMOS pipe P12, the grid of described the 15 PMOS pipe P15, the grid of described the 18 PMOS pipe P18, the grid of described the 21 PMOS pipe P21, the grid of described the 24 PMOS pipe P24, the grid of the grid of described the 27 PMOS pipe P27 and described the 30 PMOS pipe P30 accesses respectively the first category-A clock control signal, the second category-A clock control signal, the 3rd category-A clock control signal, the 4th category-A clock control signal, the 5th category-A clock control signal, the 6th category-A clock control signal, the 7th category-A clock control signal and the 8th category-A clock control signal, the grid of described the 13 PMOS pipe P13, the grid of described the 19 PMOS pipe P19, the grid of described the 16 PMOS pipe P16, the grid of described the 22 PMOS pipe P22, the grid of described the 25 PMOS pipe P25, the grid of described the 28 PMOS pipe P28, the grid of the grid of described the 31 PMOS pipe P31 and described the tenth PMOS pipe P10 accesses respectively the first category-B clock control signal, the second category-B clock control signal, the 3rd category-B clock control signal, the 4th category-B clock control signal, the 5th category-B clock control signal, the 6th category-B clock control signal, the 7th category-B clock control signal and the 8th category-B clock control signal, the grid of described the 23 PMOS pipe P23, the grid of described the 26 PMOS pipe P26, the grid of described the 29 PMOS pipe P29, the grid of described the 32 PMOS pipe P32, the grid of described the 11 PMOS pipe P11, the grid of described the 14 PMOS pipe P14, the grid of the grid of described the 17 PMOS pipe P17 and described the 20 PMOS pipe P20 accesses respectively a C class clock control signal, the 2nd C class clock control signal, the 3rd C class clock control signal, the 4th C class clock control signal, the 5th C class clock control signal, the 6th C class clock control signal, the 7th C class clock control signal and the 8th C class clock control signal, the drain electrode of described the 9th PMOS pipe P9, the drain electrode of described the 12 PMOS pipe P12, the drain electrode of described the 15 PMOS pipe P15, the drain electrode of described the 18 PMOS pipe P18, the drain electrode of described the 21 PMOS pipe P21, the drain electrode of described the 24 PMOS pipe P24, the formed contact altogether of the drain electrode of the drain electrode of described the 27 PMOS pipe P27 and described the 30 PMOS pipe P30 is as the 3rd output terminal of described Dynamic Matching Logic control module, and described the tenth PMOS manages the drain electrode of P10, the drain electrode of described the 13 PMOS pipe P13, the drain electrode of described the 19 PMOS pipe P19, the drain electrode of described the 16 PMOS pipe P16, the drain electrode of described the 22 PMOS pipe P22, the drain electrode of described the 25 PMOS pipe P25, the formed contact altogether of the drain electrode of the drain electrode of described the 28 PMOS pipe P28 and described the 31 PMOS pipe P31 is as the first output terminal of described Dynamic Matching Logic control module, and described the 11 PMOS manages the drain electrode of P11, the drain electrode of described the 14 PMOS pipe P14, the drain electrode of described the 17 PMOS pipe P17, the drain electrode of described the 20 PMOS pipe P20, the drain electrode of described the 23 PMOS pipe P23, the drain electrode of described the 26 PMOS pipe P26, the formed contact altogether of the drain electrode of the drain electrode of described the 29 PMOS pipe P29 and described the 32 PMOS pipe P32 is as the second output terminal of described Dynamic Matching Logic control module.

4. band-gap reference circuit as claimed in claim 3, is characterized in that, described the 4th resistance R 4 is adjustable resistance.

5. a chip, is characterized in that, described chip comprises a band-gap reference circuit, and described band-gap reference circuit comprises that the ripple to being mingled with in bandgap voltage reference carries out the low-pass filter of filtering;

Described band-gap reference circuit also comprises:

Current mirror, Dynamic Matching Logic control module, error amplifier, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the first positive-negative-positive triode Q1 and the second positive-negative-positive triode Q2;

The input end access supply voltage of described current mirror, a plurality of output terminals of described current mirror connect one to one with a plurality of input ends of described Dynamic Matching Logic control module respectively, the quantity of a plurality of output terminals of described current mirror is identical with the quantity of a plurality of input ends of described Dynamic Matching Logic control module, a plurality of control end incoming clock control signals of described Dynamic Matching Logic control module, the control end of described current mirror connects the output terminal of described error amplifier, the emitter of described the first positive-negative-positive triode Q1 and the first output terminal of described Dynamic Matching Logic control module are connected to the inverting input of described error amplifier altogether, the first end of described the first resistance R 1 connects the base stage of described the first positive-negative-positive triode Q1, the collector of the second end of described the first resistance R 1 and described the first positive-negative-positive triode Q1, the collector of the first end of described the second resistance R 2 and described the second positive-negative-positive triode Q2 is connected to ground altogether, the first end of described the second resistance R 2 connects the first end of described the 3rd resistance R 3, the base stage of the second end of described the 3rd resistance R 3 and described the second positive-negative-positive triode Q2 is connected to the second output terminal of described Dynamic Matching Logic control module altogether, the emitter of described the second positive-negative-positive triode Q2 and the in-phase input end of described error amplifier are connected to the first end of described the 4th resistance R 4 altogether, the 3rd output terminal of the second end of described the 4th resistance R 4 and described Dynamic Matching Logic control module is connected to the input end of described low-pass filter altogether, the area of the emitter of described the first positive-negative-positive triode Q1 equals the area of the emitter of described the second positive-negative-positive triode Q2.

6. chip as claimed in claim 5, is characterized in that, described current mirror comprises:

The one PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7 and the 8th PMOS pipe P8;

The source electrode of the source electrode of a described PMOS pipe P1 and described the 2nd PMOS pipe P2, the source electrode of described the 3rd PMOS pipe P3, the source electrode of described the 4th PMOS pipe P4, the source electrode of described the 5th PMOS pipe P5, the source electrode of described the 6th PMOS pipe P6, the source electrode of the source electrode of described the 7th PMOS pipe P7 and described the 8th PMOS pipe P8 connects formed contact altogether altogether as the input end of described current mirror, the grid of the grid of a described PMOS pipe P1 and described the 2nd PMOS pipe P2, the grid of described the 3rd PMOS pipe P3, the grid of described the 4th PMOS pipe P4, the grid of described the 5th PMOS pipe P5, the grid of described the 6th PMOS pipe P6, the grid of the grid of described the 7th PMOS pipe P7 and described the 8th PMOS pipe P8 connects formed contact altogether altogether as the control end of described current mirror, the drain electrode of the drain electrode of a described PMOS pipe P1 and described the 2nd PMOS pipe P2, the drain electrode of described the 3rd PMOS pipe P3, the drain electrode of described the 4th PMOS pipe P4, the drain electrode of described the 5th PMOS pipe P5, the drain electrode of described the 6th PMOS pipe P6, the drain electrode of the drain electrode of described the 7th PMOS pipe P7 and described the 8th PMOS pipe P8 is respectively the first output terminal of described current mirror, the second output terminal, the 3rd output terminal, the 4th output terminal, the 5th output terminal, the 6th output terminal, the 7th output terminal and the 8th output terminal.

7. chip as claimed in claim 6, is characterized in that, described Dynamic Matching Logic control module comprises:

The 9th PMOS pipe P9, the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 19 PMOS pipe P19, the 20 PMOS pipe P20, the 21 PMOS pipe P21, the 22 PMOS pipe P22, the 23 PMOS pipe P23, the 24 PMOS pipe P24, the 25 PMOS pipe P25, the 26 PMOS pipe P26, the 27 PMOS pipe P27, the 28 PMOS pipe P28, the 29 PMOS pipe P29, the 30 PMOS pipe P30, the 31 PMOS pipe P31 and the 32 PMOS pipe P32,

The source electrode of described the 9th PMOS pipe P9, the formed first input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the tenth PMOS pipe P10 and described the 11 PMOS pipe P11, the source electrode of described the 12 PMOS pipe P12, formed the second input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 13 PMOS pipe P13 and described the 14 PMOS pipe P14, the source electrode of described the 15 PMOS pipe P15, formed the 3rd input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 16 PMOS pipe P16 and described the 17 PMOS pipe P17, the source electrode of described the 18 PMOS pipe P18, the formed four-input terminal that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 19 PMOS pipe P19 and described the 20 PMOS pipe P20, the source electrode of described the 21 PMOS pipe P21, formed the 5th input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 22 PMOS pipe P22 and described the 23 PMOS pipe P23, the source electrode of described the 24 PMOS pipe P24, formed the 6th input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 25 PMOS pipe P25 and described the 26 PMOS pipe P26, the source electrode of described the 27 PMOS pipe P27, formed the 7th input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 28 PMOS pipe P28 and described the 29 PMOS pipe P29, the source electrode of described the 30 PMOS pipe P30, formed the 8th input end that contact is described Dynamic Matching Logic control module altogether of source electrode of the source electrode of described the 31 PMOS pipe P31 and described the 32 PMOS pipe P32, the first input end of described Dynamic Matching Logic control module, the second input end, the 3rd input end, four-input terminal, the 5th input end, the 6th input end, the 7th input end and the 8th input end connect respectively the first output terminal of described current mirror, the second output terminal, the 3rd output terminal, the 4th output terminal, the 5th output terminal, the 6th output terminal, the 7th output terminal and the 8th output terminal,

The grid of described the 9th PMOS pipe P9, the grid of described the 12 PMOS pipe P12, the grid of described the 15 PMOS pipe P15, the grid of described the 18 PMOS pipe P18, the grid of described the 21 PMOS pipe P21, the grid of described the 24 PMOS pipe P24, the grid of the grid of described the 27 PMOS pipe P27 and described the 30 PMOS pipe P30 accesses respectively the first category-A clock control signal, the second category-A clock control signal, the 3rd category-A clock control signal, the 4th category-A clock control signal, the 5th category-A clock control signal, the 6th category-A clock control signal, the 7th category-A clock control signal and the 8th category-A clock control signal, the grid of described the 13 PMOS pipe P13, the grid of described the 19 PMOS pipe P19, the grid of described the 16 PMOS pipe P16, the grid of described the 22 PMOS pipe P22, the grid of described the 25 PMOS pipe P25, the grid of described the 28 PMOS pipe P28, the grid of the grid of described the 31 PMOS pipe P31 and described the tenth PMOS pipe P10 accesses respectively the first category-B clock control signal, the second category-B clock control signal, the 3rd category-B clock control signal, the 4th category-B clock control signal, the 5th category-B clock control signal, the 6th category-B clock control signal, the 7th category-B clock control signal and the 8th category-B clock control signal, the grid of described the 23 PMOS pipe P23, the grid of described the 26 PMOS pipe P26, the grid of described the 29 PMOS pipe P29, the grid of described the 32 PMOS pipe P32, the grid of described the 11 PMOS pipe P11, the grid of described the 14 PMOS pipe P14, the grid of the grid of described the 17 PMOS pipe P17 and described the 20 PMOS pipe P20 accesses respectively a C class clock control signal, the 2nd C class clock control signal, the 3rd C class clock control signal, the 4th C class clock control signal, the 5th C class clock control signal, the 6th C class clock control signal, the 7th C class clock control signal and the 8th C class clock control signal, the drain electrode of described the 9th PMOS pipe P9, the drain electrode of described the 12 PMOS pipe P12, the drain electrode of described the 15 PMOS pipe P15, the drain electrode of described the 18 PMOS pipe P18, the drain electrode of described the 21 PMOS pipe P21, the drain electrode of described the 24 PMOS pipe P24, the formed contact altogether of the drain electrode of the drain electrode of described the 27 PMOS pipe P27 and described the 30 PMOS pipe P30 is as the 3rd output terminal of described Dynamic Matching Logic control module, and described the tenth PMOS manages the drain electrode of P10, the drain electrode of described the 13 PMOS pipe P13, the drain electrode of described the 19 PMOS pipe P19, the drain electrode of described the 16 PMOS pipe P16, the drain electrode of described the 22 PMOS pipe P22, the drain electrode of described the 25 PMOS pipe P25, the formed contact altogether of the drain electrode of the drain electrode of described the 28 PMOS pipe P28 and described the 31 PMOS pipe P31 is as the first output terminal of described Dynamic Matching Logic control module, and described the 11 PMOS manages the drain electrode of P11, the drain electrode of described the 14 PMOS pipe P14, the drain electrode of described the 17 PMOS pipe P17, the drain electrode of described the 20 PMOS pipe P20, the drain electrode of described the 23 PMOS pipe P23, the drain electrode of described the 26 PMOS pipe P26, the formed contact altogether of the drain electrode of the drain electrode of described the 29 PMOS pipe P29 and described the 32 PMOS pipe P32 is as the second output terminal of described Dynamic Matching Logic control module.

8. chip as claimed in claim 7, is characterized in that, described the 4th resistance R 4 is adjustable resistance.

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