CN114035642A - Reference circuit, chip and control method - Google Patents
Reference circuit, chip and control method Download PDFInfo
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- CN114035642A CN114035642A CN202111314244.3A CN202111314244A CN114035642A CN 114035642 A CN114035642 A CN 114035642A CN 202111314244 A CN202111314244 A CN 202111314244A CN 114035642 A CN114035642 A CN 114035642A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention provides a reference circuit, a chip and a control method, belonging to the technical field of circuits, wherein the circuit comprises: the circuit comprises a first current mirror, a first chopping switch, a current branch, a feedback branch and an output branch, wherein the first current mirror is provided with a dynamic element matching switch and comprises a first output end and a second output end; the first chopping switch comprises a third output terminal and a fourth output terminal; the current ratio between the first output terminal and the second output terminal is determined by the phase relationship between the first clock of the dynamic element matched switch and the second clock of the first chopping switch; through the DEM technology and the chopping modulation technology, the influence of charge injection of a chopping switch is counteracted, the short-time pulse interference of a reference circuit is reduced, the output voltage ripple is reduced, and the stability and the precision of the reference voltage are improved.
Description
Technical Field
The present disclosure relates to circuit technologies, and in particular, to a reference circuit, a chip and a control method.
Background
In many electronic products, circuits such as bio-signal instrumentation amplifiers and programmable gain amplifiers generally require a stable reference voltage as a common mode level or a current source bias voltage of the circuit. The reference voltage is usually required to have a small coefficient of variation with temperature, a small offset voltage and a small noise of voltage output. At present, chopping modulation is generally used in a reference circuit, low-frequency noise and offset voltage can be reduced, but due to the charge injection effect of a chopping switch, ripples at the output end of the reference circuit are increased, and the output precision of the reference circuit is influenced.
Disclosure of Invention
The invention provides a reference circuit, a chip and a control method, which are used for counteracting the influence of charge injection of a chopping switch through a DEM (digital elevation model) technology and a chopping modulation technology, reducing the short-time pulse interference of the reference circuit, reducing the output voltage ripple and improving the stability and the precision of reference voltage.
The technical scheme adopted for solving the technical problems is as follows:
according to one aspect herein, there is provided a reference circuit comprising: the circuit comprises a first current mirror, a first chopping switch, a current branch, a feedback branch and an output branch, wherein the first current mirror is provided with a dynamic element matching switch and comprises a first output end and a second output end; the first chopping switch comprises a third output terminal and a fourth output terminal; the current ratio between the first output terminal and the second output terminal is determined by the phase relationship between the first clock of the dynamic element matched switch and the second clock of the first chopping switch;
the first chopping switch is used for alternating the output current of the third output end and the output current of the fourth output end according to the second clock so as to perform chopping modulation on the reference circuit;
the input end of the feedback branch circuit is connected with the output end of the first chopping switch, and the output end of the feedback branch circuit is connected with the current mirror and used for adjusting the output currents of the first output end and the second output end;
the current branch is respectively connected with the first chopping switch and the output branch and used for providing a bias signal for the output branch;
the output branch is used for outputting a reference voltage based on the bias signal.
Optionally, the current branch comprises: the chopper circuit comprises a second chopper switch, a plurality of voltage division resistors, a first switching tube and a second switching tube, wherein the voltage division resistors are connected in series with one another, two input ends of the second chopper switch are respectively connected with the first switching tube and the second switching tube through at least one voltage division resistor, an output end of the second chopper switch is connected with an output branch, the voltage division resistors are connected in series with one another and used for generating at least two bias points, and the second chopper switch is used for selecting one bias point from the at least two bias points to provide a bias signal for the output branch.
Optionally, the output branch includes a second current mirror and a programmable resistance circuit, and the second current mirror is connected to the current branch and the first current mirror, respectively, and is configured to generate a mirror current; the programmable resistance circuit is connected with the second current mirror and used for generating adjustable reference voltage according to the mirror current.
Optionally, the second current mirror includes at least two mirror image branches, each mirror image branch includes an input tube and an output tube, and the output branch further includes a third chopper switch, and the third chopper switch is connected between the input tube and the output tube, and is configured to rotate currents between the at least two mirror image branches.
Optionally, the frequency of the first clock is N times of the frequency of the second clock, where N is a positive integer and N ≧ 2.
Optionally, the first clock of the dynamic element matching switch partially overlaps the second clock of the chopping switch.
Optionally, the first clock comprises a plurality of phase clocks which do not overlap with each other, and a first level of each phase clock overlaps or is complementary to a second clock of the chopping switch in sequence in one clock cycle of the dynamic element matching switch;
the dynamic element matching switch comprises a plurality of sub-switches which are alternatively conducted according to the first levels of the plurality of non-overlapping phase clocks;
wherein the first level is a high level or a low level.
Optionally, the dynamic element matching switch includes M sub-switches, the first clock includes M phase clocks that do not overlap with each other, the M sub-switches are alternately turned on according to the M phase clocks that do not overlap with each other, and a duty ratio of each phase clock is 1: (M-1), wherein M is a positive integer and M.gtoreq.2.
Optionally, the current ratio between the first output terminal and the second output terminal is 1: (M-1) or (M-1): 1.
According to another aspect herein, there is provided a chip comprising the reference circuit described above.
According to still another aspect of the present disclosure, there is provided a control method of a reference circuit, applied to the above reference circuit, the method including:
determining a phase relationship between a first clock of the dynamic element matching switch and a second clock of a chopping switch;
determining the current proportion between the first output end and the second output end of the current mirror according to the phase relation;
according to the first clock control dynamic element matching switch, the ratio of the output current of the first output end and the output current of the second output end is in accordance with the current proportion;
and controlling the chopping switch according to the second clock, so that the output current of the third output end and the output current of the fourth output end of the chopping switch are alternated, and chopping modulation is performed on the reference circuit.
The invention discloses a reference circuit, a chip and a control method, wherein the circuit comprises: the circuit comprises a first current mirror, a first chopping switch, a current branch, a feedback branch and an output branch, wherein the first current mirror is provided with a dynamic element matching switch and comprises a first output end and a second output end; the first chopping switch comprises a third output terminal and a fourth output terminal; the current ratio between the first output terminal and the second output terminal is determined by the phase relationship between the first clock of the dynamic element matched switch and the second clock of the first chopping switch; through the DEM technology and the chopping modulation technology, the influence of charge injection of a chopping switch is counteracted, the short-time pulse interference of a reference circuit is reduced, the output voltage ripple is reduced, and the stability and the precision of the reference voltage are improved.
Drawings
Fig. 1 is a functional structure diagram of a reference circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a reference circuit according to an embodiment of the present invention;
FIG. 3 is a phase relationship diagram of a DEM clock and a chop clock according to an embodiment of the present invention;
fig. 4 is a flowchart of a control method of the reference circuit according to an embodiment of the present invention.
The objects, features, and advantages described herein will be further explained with reference to the accompanying drawings.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer and more obvious, the present invention is further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not restrictive.
In order to improve the output accuracy of the reference circuit, the present invention provides a reference circuit, as shown in fig. 1, comprising: the circuit comprises a first current mirror 101, a first chopping switch 102, a current branch 103, a feedback branch 104 and an output branch 105, wherein a dynamic element matching switch DEM is arranged in the first current mirror 101, and the first current mirror 101 comprises a first output end and a second output end; the first chopping switch 102 includes a third output terminal and a fourth output terminal; the current ratio between the first output and the second output is determined by the phase relationship between the first clock of the dynamic element matched switch and the second clock of the first chopping switch. And the first chopping switch is used for alternating the output current of the third output end and the output current of the fourth output end according to the second clock so as to perform chopping modulation on the reference circuit. The input end of the feedback branch circuit is connected with the output end of the first chopping switch, and the output end of the feedback branch circuit is connected with the current mirror and used for adjusting the output currents of the first output end and the second output end. The current branch is respectively connected with the first chopping switch and the output branch and used for providing a bias signal for the output branch. The output branch is used for outputting a reference voltage based on the bias signal.
As an example, as shown in fig. 2, the first current mirror is provided with 4 MOS transistors Q1, Q2, Q3, Q4) as input transistors, and 2 MOS transistors Q5, Q6 as output transistors. Taking the first current mirror as a P-type current mirror as an example, that is, the above 6 MOS transistors are all PMOS transistors, the drains of the 4 input transistors Q1, Q2, Q3, and Q4 are respectively connected to the dynamic element matching switch, the sources of the 2 output transistors Q5 and Q6 are connected to the dynamic element matching switch DEM, and the drains of the 2 output transistors are connected to the first chopper switch CHOP1 and serve as the first output terminal and the second output terminal.
In some embodiments, the frequency of the first clock is N times the frequency of the second clock, where N is a positive integer and N ≧ 2.
As an example, the input Q1 is a first input branch of the dynamic element matching switch, whose clock corresponds to the DEM _ ck1 pulse in fig. 3, the input Q2 is a second input branch of the dynamic element matching switch, whose clock corresponds to the DEM _ ck2 pulse in fig. 3, the input Q3 is a third input branch of the dynamic element matching switch, whose clock corresponds to the DEM _ ck3 pulse in fig. 3, the input Q4 is a fourth input branch of the dynamic element matching switch, whose clock corresponds to the DEM _ ck4 pulse in fig. 3, and the periods of the four input branches of the dynamic element matching switch are the same, whose clocks may be collectively referred to as the first clock. Chop clk in fig. 3 is the clock pulse of the first chopping switch, i.e., the second clock. As can be seen from fig. 3, the period of the first clock is half of the period of the second clock, and the frequency of the first clock is 2 times that of the second clock.
In some embodiments, the first clock of the dynamic element matching switch partially overlaps the second clock of the chopping switch, as shown in fig. 3, with the first rising edge of the second clock chop clk as the start of one cycle, and in a half cycle when the second clock is at a high level, when the pulse of the first input branch DEM _ ck1 is at a high level, the clock pulse of the first input branch DEM _ ck1 is at a high level and overlaps with the second clock, and when the pulse of the first input branch DEM _ ck1 is at a low level, the clock pulse of the first input branch DEM _ ck1 is complementary with the second clock; as can be seen from fig. 3, the clock pulses of the other three input branches also partially overlap with the second clock, and are partially complementary, which is not described herein again.
In some embodiments, the first clock comprises a plurality of phase clocks which do not overlap with each other, and the first level of each phase clock overlaps with or is complementary to the second clock of the chopping switch in sequence in one clock cycle of the dynamic element matching switch; the dynamic element matching switch comprises a plurality of sub-switches, the plurality of sub-switches correspond to the 4 input tubes and are alternately conducted according to first levels of a plurality of phase clocks which are not overlapped with each other; wherein the first level is a high level or a low level.
As an embodiment, the dynamic element matching switch includes M sub-switches, the first clock includes M phase clocks that do not overlap with each other, the M sub-switches are alternately turned on according to the M phase clocks that do not overlap with each other, and a duty ratio of each phase clock is 1: (M-1), wherein M is a positive integer and M.gtoreq.2.
In this embodiment, the current ratio between the first output terminal and the second output terminal is 1: (M-1) or (M-1): 1.
Taking M ═ 4 as an example, the dynamic element matching switch is a selection switch, 4 input tubes are alternately turned on, when any input tube is turned on, the first chopping switch is turned on, when a signal of a first clock of the dynamic element matching switch is as shown in fig. 3, 4 input tubes are alternately turned on, the duty ratio of a signal of each input tube is 1:3, a signal of a second clock of the first chopping switch is as shown in fig. 3, the duty ratio is 1:1, and assuming that currents of each input tube are all 4i, the current ratio of the first output end and the second output end is 1:3 or 3:1, and the current ratio is rotated on the rising edge or the falling edge of the clock signal of the first chopping switch.
As another example, the number of input tubes and output tubes may be set to other numbers, and the ratio of currents between the first output terminal and the second output terminal may be changed.
In some embodiments, as shown in fig. 2, the feedback branch includes an operational amplifier OP, positive and negative input terminals of the operational amplifier OP are respectively connected to a third output terminal and a fourth output terminal of the first chopping switch, an output terminal of the operational amplifier is connected to the first current mirror, when the first chopping switch is rotated, a current ratio of the third output terminal to the fourth output terminal is 1:3 or 3:1, in the rotating process, the first chopping switch and the dynamic element matching switch have charge injection, the charge injection is equal in size and opposite in direction, short-time pulse interference cancellation is performed, and stability and precision of the reference voltage are improved.
In some embodiments, as shown in fig. 2, the current branch 103 includes: the chopper switch comprises a second chopper switch CHOP2, a plurality of voltage dividing resistors R1, R2 and R3 which are connected in series with one another, a first switching tube V1 and a second switching tube V2, wherein two input ends of the second chopper switch CHOP2 are respectively connected with the first switching tube and the second switching tube through at least one voltage dividing resistor, an output end of the second chopper switch is connected with the output branch 105, the plurality of voltage dividing resistors which are connected in series with one another are used for generating at least two bias points (such as E1 and E2 shown in FIG. 2), and the second chopper switch is used for selecting one bias point from the at least two bias points to provide a bias signal for the output branch.
As an example, as shown in fig. 2, the voltage dividing resistor includes a first resistor R1, a second resistor R2, and a third resistor R3, the three voltage dividing resistors are sequentially connected in series, a node between the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is a first bias point E1, and a node between the second voltage dividing resistor R3 and the third voltage dividing resistor R3 is a second bias point E2. The first chopper switch and the second chopper switch are both triodes V1 and V2, one input end of the second chopper switch CHOP2 is connected with the base of the first chopper switch V1 through a first bias point E1 and a first voltage dividing resistor, the emitter of the first chopper switch is connected with the third output end of the first chopper switch, the other input end of the second chopper switch is connected with the base of the second chopper switch V2 through a second bias point E2 and a third voltage dividing resistor, and the emitter of the second chopper switch is connected with the fourth output end of the first chopper switch.
As another embodiment, the number of voltage dividing resistors may be more than three, and correspondingly, the number of bias points is also more than two, and the second chopping switch CHOP2 selects one bias point among a plurality of bias points to provide the bias signal for the output branch.
As another embodiment, the number of the voltage dividing resistors may be less than three, for example, one or two. Accordingly, the number of bias points is only one, which may be directly connected to the output branch and provide the voltage to the output branch, in which case the current branch 103 may not include the second chopping switch CHOP 2.
In some embodiments, output branch 105 includes a second current mirror 1051 and a programmable resistor circuit 1052, the second current mirror being connected to current branch 103 and first current mirror 101, respectively, and configured to generate a mirrored current; the programmable resistance circuit is connected with the second current mirror and used for generating adjustable reference voltage according to the mirror current.
In this embodiment, the second current mirror 1051 includes at least two mirror branches, each mirror branch includes an input tube and an output tube, and the output branch further includes a third chopping switch CHOP3, and the third chopping switch CHOP3 is connected between the input tube and the output tube for rotating the current between the at least two mirror branches.
As an example, as shown in fig. 2, the second current mirror includes two mirror image branches, the input transistor of the first mirror image branch is MOS transistor Q7, the output transistor is MOS transistor Q9, the input transistor of the second mirror image branch is MOS transistor Q8, the output transistor is MOS transistor Q10, the drains of MOS transistor Q7 and MOS transistor Q8 are connected to two input terminals of the third chopper switch CHOP3, the sources of MOS transistor Q9 and MOS transistor Q10 are connected to two output terminals of the third chopper switch CHOP3, the drain of MOS transistor Q9 is connected to an output terminal of the second chopper switch, and the drain of MOS transistor Q10 is connected to the programmable resistor circuit.
As an example, the programmable resistor circuit includes a programmable resistor R and a switching tube V3, one end of the programmable resistor R is connected to the drain of the MOS transistor Q10 for receiving the mirror current of the second current mirror, the other end of the programmable resistor R is connected to the emitter of the switching tube V3, and the base and the collector of the switching tube V3 are grounded together to perform a temperature compensation function. The middle contact of the programmable resistor R is a reference voltage output end, and the reference voltage VBG is generated according to the mirror current.
The embodiment of the invention also provides a chip, which comprises the reference circuit in any one of the embodiments.
In some embodiments, by means of the DEM technology and the chopping modulation technology, the influence of charge injection of a chopping switch is counteracted, short-time pulse interference of a reference circuit is reduced, output voltage ripples are reduced, and stability and precision of reference voltage are improved. When the method is used in a health measurement product, the stability of a current source or a common mode level of the health measurement product can be improved, and the measurement precision and the stability of the product are improved.
In some embodiments, the current mirrors are dynamically matched, reducing the residual offset input of the chopper modulation. The DEM clock frequency is set to 1/2 times of the chop clock frequency, 4 dynamic matching processes, and the switch MOS charge injection current cancels with the corresponding chopper modulated switch MOS charge injection current. The short-time pulse interference at the input end of the operational amplifier is greatly reduced, and the voltage output ripple is reduced.
An embodiment of the present invention further provides a control method of a reference circuit, which is applied to the reference circuit in the embodiment, as shown in fig. 4, the control method of the reference circuit includes:
s10, determining the phase relation between the first clock of the dynamic element matching switch and the second clock of the chopping switch;
s20, determining the current proportion between the first output end and the second output end of the current mirror according to the phase relation;
s30, according to the first clock control, the dynamic element matching switch is controlled, so that the ratio of the output current of the first output end and the output current of the second output end is in accordance with the current proportion;
and S40, controlling the chopping switch according to the second clock, and alternating the output current of the third output end and the output current of the fourth output end of the chopping switch to perform chopping modulation on the reference circuit.
In some embodiments, as shown in fig. 2, the first current mirror is provided with 4 MOS transistors Q1, Q2, Q3, Q4) as input transistors, and 2 MOS transistors Q5, Q6 as output transistors. Taking the first current mirror as a P-type current mirror as an example, that is, the above 6 MOS transistors are all PMOS transistors, the drains of the 4 input transistors Q1, Q2, Q3, and Q4 are respectively connected to the dynamic element matching switch, the sources of the 2 output transistors Q5 and Q6 are connected to the dynamic element matching switch DEM, and the drains of the 2 output transistors are connected to the first chopper switch CHOP1 and serve as the first output terminal and the second output terminal.
In some embodiments, the frequency of the first clock is N times the frequency of the second clock, where N is a positive integer and N ≧ 2.
As an example, the input Q1 is a first input branch of the dynamic element matching switch, whose clock corresponds to the DEM _ ck1 pulse in fig. 3, the input Q2 is a second input branch of the dynamic element matching switch, whose clock corresponds to the DEM _ ck2 pulse in fig. 3, the input Q3 is a third input branch of the dynamic element matching switch, whose clock corresponds to the DEM _ ck3 pulse in fig. 3, the input Q4 is a fourth input branch of the dynamic element matching switch, whose clock corresponds to the DEM _ ck4 pulse in fig. 3, and the periods of the four input branches of the dynamic element matching switch are the same, whose clocks may be collectively referred to as the first clock. The chop clk in fig. 3 is the clock pulse of the first chopping switch, and as can be seen from fig. 3, the period of the first clock is half the period of the second clock, and the frequency of the first clock is 2 times that of the second clock.
In some embodiments, the first clock of the dynamic element matching switch partially overlaps the second clock of the chopping switch, as shown in fig. 3, with the first rising edge of the second clock as the start of a period, and during a half period when the second clock is at a high level, the first input branch DEM _ ck1 pulse is at a high level, and the first input branch DEM _ ck1 pulse is at a high level and overlaps the second clock, and the first input branch DEM _ ck1 pulse is at a low level, and the first input branch DEM _ ck1 pulse is at a complementary level to the second clock; as can be seen from fig. 3, the clock pulses of the other three input branches also partially overlap with the second clock, and are partially complementary, which is not described herein again.
As an example, as shown in fig. 3, phase differences exist between the first clock and the second clock and between 4 clock pulses of the first clock, specifically, referring to a rising edge and a falling edge of each clock pulse in fig. 3, a first rising edge of the second clock comes at the same time as a first rising edge of the DEM _ ck4 clock, there is no phase difference therebetween, the DEM _ ck4 clock is advanced by 90 ° compared with the DEM _ ck1 clock, the DEM _ ck1 clock is advanced by 90 ° compared with the DEM _ ck2 clock, the DEM _ ck2 clock is advanced by 90 ° compared with the DEM _ ck3 clock, the DEM _ ck3 clock is advanced by 90 ° compared with the DEM _ ck4 clock, according to these phase relationships, the number M of sub-switches included in the dynamic element matching switch may be known, and it may be derived that the current ratio between the first output terminal and the second output terminal is 1: (M-1) or (M-1): 1. As another example, the number of input tubes and output tubes may be set to other numbers, and the ratio of currents between the first output terminal and the second output terminal may be changed.
Taking M ═ 4 as an example, the dynamic element matching switch is a selection switch, 4 input tubes are alternately turned on, when any input tube is turned on, the first chopping switch is turned on, when a signal of a first clock of the dynamic element matching switch is as shown in fig. 3, 4 input tubes are alternately turned on, the duty ratio of a signal of each input tube is 1:3, a signal of a second clock of the first chopping switch is as shown in fig. 3, the duty ratio is 1:1, and assuming that currents of each input tube are all 4i, the current ratio of the first output end and the second output end is 1:3 or 3:1, and the current ratio is rotated on the rising edge or the falling edge of the clock signal of the first chopping switch. In this embodiment, the first clock includes a plurality of phase clocks that do not overlap each other, and in one clock cycle of the dynamic element matching switch, the first level of each phase clock overlaps or complements the second clock of the chopper switch in sequence;
the dynamic element matching switch comprises a plurality of sub-switches, the plurality of sub-switches correspond to the 4 input tubes and are alternately conducted according to first levels of a plurality of phase clocks which are not overlapped with each other; wherein the first level is a high level or a low level.
In the embodiment, by means of the DEM technology and the chopping modulation technology, the influence of charge injection of the chopping switch is counteracted, short-time pulse interference of the reference circuit is reduced, output voltage ripples are reduced, and stability and precision of the reference voltage are improved. When the method is used in a health measurement product, the stability of a current source or a common mode level of the health measurement product can be improved, and the measurement precision and the stability of the product are improved.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, and are not to be construed as limiting the scope of the invention. Any modifications, equivalents and improvements which may occur to those skilled in the art without departing from the scope and spirit of the present invention are intended to be within the scope of the claims.
Claims (11)
1. A reference circuit, comprising: the circuit comprises a first current mirror, a first chopping switch, a current branch, a feedback branch and an output branch, wherein the first current mirror is provided with a dynamic element matching switch and comprises a first output end and a second output end; the first chopping switch comprises a third output terminal and a fourth output terminal; the current ratio between the first output terminal and the second output terminal is determined by the phase relationship between the first clock of the dynamic element matched switch and the second clock of the first chopping switch;
the first chopping switch is used for alternating the output current of the third output end and the output current of the fourth output end according to the second clock so as to perform chopping modulation on the reference circuit;
the input end of the feedback branch circuit is connected with the output end of the first chopping switch, and the output end of the feedback branch circuit is connected with the current mirror and used for adjusting the output currents of the first output end and the second output end;
the current branch is respectively connected with the first chopping switch and the output branch and used for providing a bias signal for the output branch;
the output branch is used for outputting a reference voltage based on the bias signal.
2. The reference circuit of claim 1, wherein the current branch comprises: the chopper circuit comprises a second chopper switch, a plurality of voltage division resistors, a first switching tube and a second switching tube, wherein the voltage division resistors are connected in series with one another, two input ends of the second chopper switch are respectively connected with the first switching tube and the second switching tube through at least one voltage division resistor, an output end of the second chopper switch is connected with an output branch, the voltage division resistors are connected in series with one another and used for generating at least two bias points, and the second chopper switch is used for selecting one bias point from the at least two bias points to provide a bias signal for the output branch.
3. The reference circuit of claim 1, wherein the output branch comprises a second current mirror and a programmable resistance circuit, the second current mirror being connected to the current branch and the first current mirror, respectively, and configured to generate a mirror current; the programmable resistance circuit is connected with the second current mirror and used for generating adjustable reference voltage according to the mirror current.
4. The reference circuit of claim 3, wherein the second current mirror comprises at least two mirror legs, each of the mirror legs comprises an input tube and an output tube, and the output leg further comprises a third chopping switch connected between the input tube and the output tube for rotating current between the at least two mirror legs.
5. The reference circuit according to any of claims 1-4, wherein the frequency of the first clock is N times the frequency of the second clock, where N is a positive integer and N ≧ 2.
6. The reference circuit of any of claims 1-4, wherein a first clock of the dynamic element matching switch partially overlaps a second clock of the chopping switch.
7. The reference circuit of claim 6,
the first clock comprises a plurality of phase clocks which are not overlapped with each other, and in one clock cycle of the dynamic element matching switch, the first level of each phase clock is overlapped with or complementary to the second clock of the chopping switch in sequence;
the dynamic element matching switch comprises a plurality of sub-switches which are alternatively conducted according to the first levels of the plurality of non-overlapping phase clocks;
wherein the first level is a high level or a low level.
8. The reference circuit of claim 7, wherein the dynamic element matching switch comprises M sub-switches, the first clock comprises M non-overlapping phase clocks, the M sub-switches are alternately turned on according to the M non-overlapping phase clocks, and a duty ratio of each phase clock is 1: (M-1), wherein M is a positive integer and M.gtoreq.2.
9. The reference circuit of claim 8, wherein a current ratio between the first output terminal and the second output terminal is 1: (M-1) or (M-1): 1.
10. A chip comprising a reference circuit as claimed in any one of claims 1 to 4.
11. A control method of a reference circuit, applied to the reference circuit according to any one of claims 1 to 9, the method comprising:
determining a phase relationship between a first clock of the dynamic element matching switch and a second clock of a chopping switch;
determining the current proportion between the first output end and the second output end of the current mirror according to the phase relation;
according to the first clock control dynamic element matching switch, the ratio of the output current of the first output end and the output current of the second output end is in accordance with the current proportion;
and controlling the chopping switch according to the second clock, so that the output current of the third output end and the output current of the fourth output end of the chopping switch are alternated, and chopping modulation is performed on the reference circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103455074A (en) * | 2013-08-28 | 2013-12-18 | 深圳市芯海科技有限公司 | Band-gap reference circuit and chip |
| CN104390715A (en) * | 2014-10-15 | 2015-03-04 | 南通大学 | Temperature conversion method and a low-power high-precision integrated temperature sensor |
| CN105705085A (en) * | 2013-06-12 | 2016-06-22 | 新加坡科技研究局 | Integrated multimodal sensor device for intracranial neuromonitoring |
| US20170257113A1 (en) * | 2016-03-04 | 2017-09-07 | Sandisk Technologies Llc | High Accuracy Temperature Sensor |
| CN107543626A (en) * | 2017-07-07 | 2018-01-05 | 芯海科技（深圳）股份有限公司 | A kind of temperature sensors of high precision without calibration |
| US20180149526A1 (en) * | 2016-11-28 | 2018-05-31 | Nxp Usa, Inc. | Temperature sensor circuitry and method therefor |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105705085A (en) * | 2013-06-12 | 2016-06-22 | 新加坡科技研究局 | Integrated multimodal sensor device for intracranial neuromonitoring |
| CN103455074A (en) * | 2013-08-28 | 2013-12-18 | 深圳市芯海科技有限公司 | Band-gap reference circuit and chip |
| CN104390715A (en) * | 2014-10-15 | 2015-03-04 | 南通大学 | Temperature conversion method and a low-power high-precision integrated temperature sensor |
| US20170257113A1 (en) * | 2016-03-04 | 2017-09-07 | Sandisk Technologies Llc | High Accuracy Temperature Sensor |
| US20180149526A1 (en) * | 2016-11-28 | 2018-05-31 | Nxp Usa, Inc. | Temperature sensor circuitry and method therefor |
| CN107543626A (en) * | 2017-07-07 | 2018-01-05 | 芯海科技（深圳）股份有限公司 | A kind of temperature sensors of high precision without calibration |
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