CN103455002B - A kind of FPGA hypervelocity industrial control system based on Verilog HDL - Google Patents

Abstract

A kind of FPGA hypervelocity industrial control system based on Verilog HDL, comprise: DA top level control module, one AD bottom layer driving module, 2nd AD bottom layer driving module, AD top level control module, DA bottom layer driving module, asynchronous serial communication transmission interface, asynchronous serial communication receiving interface, controller communications command word receives control module, controller information sends control module, output switch parameter DO Logic control module, pid algorithm module, PLL phase-locked loop module, sine values Rom storer, first AD conversion value module Ram, second AD conversion value module Ram, analog quantity DA real output value module Ram, analog quantity closed loop PID control parameter module Ram, the manual setting value module Ram of analog output DA, analog quantity AI set-point module Ram, waveform parameter module Ram.Control cycle Ts of the present invention can arrange very little according to demand, can be used for hypervelocity and controls in application.

Description

A kind of FPGA hypervelocity industrial control system based on Verilog HDL

Technical field

The present invention relates to a kind of hypervelocity industrial control system.Particularly relate to a kind of FPGA hypervelocity industrial control system based on Verilog HDL.

Background technology

In recent years, along with the continuous progress of computer technology and electronic technology and perfect, universal digital controller, as industrial automatic control series products, is accepted by increasing industrial field, and has reached a market scale attracted people's attention.In Aero-Space, Large-Scale Equipment manufacture, the contour frontier of electronic information, the index such as rapidity, stability, anti-interference, precision, speed of controller is had higher requirement, more and more stronger to the demand of hypervelocity industrial control unit (ICU).Domestic industry controller achieves certain progress catching up with in international most advanced level in recent years, but aggregate level still lags behind the country of foreign technology advanced person, develop also immature, be mainly reflected in: 1. controller is difficult to apply to ultra-high speed applications occasion, anti-interference and less stable.Due to controller soft hardware architecture design unreasonable, cause control cycle to be greater than the requirement of ultra-high speed applications, anti-interference and stability bad, final control effects is poor.2. core controller does not have independent intellectual property rights.Existing control system generally adopts external PLC and related software composition, and institute joins controller and only has indivedual external producer to provide, and controlling functions is special, is not suitable for the application requirement of China.

Nowadays domestic industry controller market is still external product and occupies most of share, and high-caliber controller market is almost monopolized by Ji Jia offshore company, that is China lacks the industrial control unit (ICU) of a kind of hypervelocity of independent intellectual property right, low cost, high reliability now.

Therefore, develop and aly possess independent intellectual property right, can be common to the hypervelocity of various control system, low cost, high reliability hypervelocity industrial control unit (ICU) have great importance.

Industrial control system scene comprises various kinds of equipment: the host computer at pulpit or scene; The analog sensor of the various manufacturing variables of measure field, as flow sensor, pressure transducer, displacement transducer, temperature sensor etc.; Change the variable valve of pipeline fluid flow, as surplus valve, ratio two-way valve etc.; The switching regulator equipment of reflection production status and man-machine interaction, as alarm contact, start/stop button etc.; For the solenoid valve etc. in the various production loop of break-make.

The applicable cases of hypervelocity industrial control unit (ICU) in industrial control system, in order to mutual with the on-the-spot various kinds of equipment comprised of above-mentioned industrial control system, hypervelocity industrial control unit (ICU) has as lower interface: RS232 with RS422(half/full duplex RS485) bus---for communicating with host computer, 16 tunnel 4 ~ 20mA/0 ~ 10V analog input signal AI---for gathering various analog sensor signal, 8 tunnel-10V ~+10V analog quantity output signals AO---for regulating and controlling valve opening, 16 way switch amount input signal DI---for reading on-the-spot various On-off signal states, 8 way switch amount output signal DO---the various solenoid valves in producing for Direct driver.

Summary of the invention

Technical matters to be solved by this invention is, provide a kind of can be common to various control system hypervelocity, low cost, high reliability can with the common forming control system of host computer and the FPGA hypervelocity industrial control system based on Verilog HDL that can directly mate with sensor and operator signals.

The technical solution adopted in the present invention is: a kind of FPGA hypervelocity industrial control system based on Verilog HDL, comprising:

DA top level control module, for in a control cycle Ts, receiving control module (8) the analog quantity DA output mode that exports according to controller communications command word selects position AUTO_HAND_DA [31:0] data to carry out the calculating of DA numerical value by a kind of mode in following five kinds of modes, and call the voltage output refreshing that DA bottom layer driving module (5) completes 8 road analog outputs, and stored in analog quantity DA real output value module Ram(16), five kinds of described modes are:

First kind of way, manually arranges DA value according to the numerical value read from the manual setting value module Ram of analog output DA and exports;

The second way, exports square wave automatically according to the cycle relative value read from waveform parameter module Ram, peak value, valley;

The third mode, exports triangular wave automatically according to the cycle relative value read from waveform parameter module Ram, peak value, valley;

4th kind of mode, according to the cycle relative value, peak value, the valley that read from waveform parameter module Ram, and according to the automatic sine wave output of numerical value read from sine values Rom storer;

5th kind of mode, according to the closed loop set-point of the analog input AI corresponding with each road AO passage of 8 road analog outputs read from analog quantity AI set-point module Ram, with the corresponding closed loop PID control parameter read from analog quantity closed loop PID control parameter module Ram, call the pid algorithm module for realizing increment type PID algorithm, the PID carrying out single closed loop or two close cycles regulates automatically, calculates DA numerical value and exports;

AD top level control module, the poll AD sample conversion of whole 16 road analog input signals is completed for calling an AD bottom layer driving module and the 2nd AD bottom layer driving module, and by transformation result stored in the first AD conversion value module Ram and the second AD conversion value module Ram, provide the control cycle synchronizing signal Ts of whole system to DA top level control module;

One AD bottom layer driving module, for receiving the 16 bit parallel control words that AD top level control module sends, convert SPI serial line interface sequential to, write is based on 12 the 8 passage A/D converter circuit of the first in the hypervelocity industrial control unit (ICU) of FPGA, control this circuit and carry out AD conversion, and the data parallel of transformation result is outputted to AD top level control module;

2nd AD bottom layer driving module, for receiving the 16 bit parallel control words that AD top level control module (4) sends, convert SPI serial line interface sequential to, write is based on 12 the 8 passage A/D converter circuit of second in the hypervelocity industrial control unit (ICU) of FPGA, control this circuit and carry out AD conversion, and the data parallel of transformation result is outputted to AD top level control module;

DA bottom layer driving module, converts SPI serial line interface sequential to for 32 bit parallel control words DA top level control module sent, and writes based on 14 8 passage D/A converter circuit in the hypervelocity industrial control unit (ICU) of FPGA.

Asynchronous serial communication receiving interface, for receiving the signal inputted based on the communication numeral buffer circuit 111 in the hypervelocity industrial control unit (ICU) of FPGA, and the asynchronous serial communication of write inside receives in fifo module, receive control module for controller communications command word and read.

Controller communications command word receives control module, for from asynchronous serial communication receiving interface sense data, all School Affairs calculating is carried out after often reading 10 byte command words of host computer transmission, controller communications command word according to setting receives resolution table, separated out the implication of host computer command word by the first character joint received and function code numerical solution, thus carry out corresponding command analysis and optimum configurations.

Output switch parameter DO Logic control module, for reading in 16 way switch amount input state signals, and exports 8 way switch amount output status signals according to the pattern of controller communications command word reception control module setting.

Controller information sends control module, respectively: the numerical value reading 16 way switch amount input states and 8 way switch amount output states from output switch parameter DO Logic control module, 12,16 analog input channel, tunnel AD conversion value is read from the first AD conversion value module Ram, 14,8 analog output channel, tunnel DA numerical value is read from analog quantity DA real output value module Ram, and by the numerical value that the reads order format write asynchronous serial communication transmission interface by setting, and this process of transmitting is moved in circles carry out.

Asynchronous serial communication transmission interface, utilizes inner asynchronous serial communication to send fifo module and receives the written information that controller information sends control module, on delivery outlet, finally complete the transmission of asynchronous serial communication Frame.

PLL phase-locked loop module, inputs with the 48MHz clock of automatic/hand reset circuit unit based on the clock input in the hypervelocity industrial control unit (ICU) of FPGA for receiving, and provides global clock signal for system.

A described AD bottom module is identical with the 2nd AD bottom modular structure, wherein, a described AD bottom module is in the read-write cycle 4.770833us of an A/D converter, convert the parallel control word receiving the transmission of AD top level control module to SPI serial line interface sequential, 16 data parallels comprising a upper read-write cycle AD conversion result read from first 12 8 passage A/D converter circuit serial based on 12 the 8 passage A/D converter circuit of the first in the hypervelocity industrial control unit (ICU) of FPGA, and are outputted to AD top level control module by write; The 2nd described AD bottom module is in the read-write cycle 4.770833us of an A/D converter, for converting the parallel control word receiving the transmission of AD top level control module to SPI serial line interface sequential, 16 data parallels comprising a upper read-write cycle AD conversion result read from second 12 8 passage A/D converter circuit serial based on 12 the 8 passage A/D converter circuit of second in the hypervelocity industrial control unit (ICU) of FPGA, and are outputted to AD top level control module by write.

Described AD top level control module, for in each control cycle Ts=0.2896667ms, call the poll AD sample conversion that an AD bottom layer driving module and the 2nd AD bottom layer driving module complete whole 16 road analog input signals, complete based on after the synchronous AD conversion of continuous 7 times an of input channel in 12 the 8 passage A/D converter circuit of the first in the hypervelocity industrial control unit (ICU) of FPGA and second 12 8 passage A/D converter circuit at every turn, after 7 subsynchronous AD conversion results of first 12 8 passage A/D converter circuit and second 12 8 passage A/D converter circuit rear is carried out simple selected and sorted 6 times, again by the middle AD conversion value of first 12 8 passage A/D converter circuit and second 12 8 passage A/D converter circuit, stored in the first AD conversion value module Ram and the second AD conversion value module Ram, the control cycle synchronizing signal Ts of whole system is provided to DA top level control module.

Described asynchronous serial communication transmission interface includes, asynchronous serial communication bottom sends driver module, asynchronous serial communication upper strata sends control module, asynchronous serial communication sends fifo module, wherein, described asynchronous serial communication sends fifo module and receives the information that controller information sends control module write; Described asynchronous serial communication upper strata sends control module and sends from described asynchronous serial communication the data to be sent that fifo module reads 1 byte, calls asynchronous serial communication bottom and sends the transmission that driver module completes frame data, and move in circles; Described asynchronous serial communication bottom sends driver module and the 8 bit parallel data to be sent that asynchronous serial communication upper strata transmission control module is sent is outputted to delivery outlet by turn according to the sequential of the frame format of 1 start bit+8 data bit+1 position of rest, no parity check position in asynchronous serial communication, and described delivery outlet is configured to the transmission pin of 1 road RS422 or full duplex RS485 or the transmission pin of 2 road RS232-C.

Described asynchronous serial communication receiving interface includes, asynchronous serial communication bottom receives driver module, asynchronous serial communication upper strata receives control module, asynchronous serial communication receives fifo module, wherein, described asynchronous serial communication upper strata receives control module and calls the reception that asynchronous serial communication bottom reception driver module completes frame data, receives 8 bit parallel data just received that fifo module writes 1 byte, move in circles to asynchronous serial communication; Described asynchronous serial communication bottom receives driver module under the control of asynchronous serial communication upper strata reception control module, become 8 bit parallel data to receive control module for asynchronous serial communication upper strata to input port state according to the timing conversion of the frame format of 1 start bit+8 data bit+1 position of rest, no parity check position in asynchronous serial communication to read, described input port is configured to the reception pin of 1 road RS422 or full duplex RS485 or the reception pin of 2 road RS232-C; The information that described asynchronous serial communication receives the write of fifo module reception asynchronous serial communication upper strata reception control module receives control module reading for controller communications command word.

The described controller communications command word controller communications command word received in control module receives resolution table setting:

When first character joint and function code numerical value are 0, the numerical value in resolve command word, and carry out a way switch amount output DO hand/Lookup protocol;

When first character joint and function code numerical value are 1, the numerical value in resolve command word, and the DA value of carrying out a road analog output AO is manually arranged;

When first character joint and function code numerical value are 2, the numerical value in resolve command word, and the setting carrying out that a road analog output AO generates square wave automatically;

When first character joint and function code numerical value are 3, the numerical value in resolve command word, and the setting carrying out that a road analog output AO generates triangular wave automatically;

When first character joint and function code numerical value are 4, the numerical value in resolve command word, and the setting carrying out that a road analog output AO generates sine wave automatically;

When first character joint and function code numerical value are 5, the numerical value in resolve command word, and carry out a road analog output AO cut automatic PID regulate enable;

When first character joint and function code numerical value are 6, the numerical value in resolve command word, and the closed loop set-point carrying out a road analog input AI is arranged;

When first character joint and function code numerical value are 7, the numerical value in resolve command word, and the closed loop PID control optimum configurations carrying out a road analog input AI.

When described function code numerical value is 0, described controller communications command word receives control module and refreshes the data exporting to output switch parameter DO Logic control module according to received command word; When described function code numerical value is 2,3 and 4, described controller communications command word receives control module, according to received command word, waveform parameter is write waveform parameter module Ram, and refreshes analog quantity DA output mode selection position AUTO_HAND_DA [31:0] data exporting to DA top level control module; When described function code numerical value is 1, described controller communications command word receives control module, according to received command word, the DA of analog output AO is manually worth the manual setting value module Ram of write analog output DA, and refreshes analog quantity DA output mode selection position AUTO_HAND_DA [31:0] data exporting to DA top level control module; When described function code numerical value is 5, described controller communications command word receives control module and refreshes analog quantity DA output mode selection position AUTO_HAND_DA [31:0] data exporting to DA top level control module according to received command word; When described function code numerical value is 6, described controller communications command word receives control module according to received command word by the closed loop set-point of road analog input write analog quantity AI set-point module Ram; When described function code numerical value is 7, described controller communications command word receives control module according to the closed loop PID control parameter read-in analog quantity closed loop PID control parameter module Ram of received command word by a road analog input.

Described controller information sends control module to host computer circulation transmit control device status information, in each transmission circulation, this controller information sends the controller state information that control module sends 52 bytes altogether: the reception synchronizing information of 0x55 as host computer first sending a byte, then from first AD conversion value module Ram read 16 × 12bit totally 32 bytes 16 road AI numerical value and send, then from analog quantity DA real output value module Ram read 8 × 14bit totally 16 bytes 8 road AO numerical value and send, the numerical value of 16 way switch amount input states and 8 way switch amount output states totally 3 bytes is finally read from output switch parameter DO Logic control module.

A kind of FPGA hypervelocity industrial control system based on Verilog HDL of the present invention, because all control and acquisition function all realize with on-site programmable gate array FPGA, therefore control cycle Ts can arrange very little according to demand, can be used for hypervelocity and control in application.EP3C16E144I7 completes the modular design of Verilog code, and nearly all module relating to sequential all becomes finite state machine by Verilog Code Design, and work is quick, stable.Only use a slice FPGA as main control chip in design, complete the analog quantity of industrial control system, the data acquisition and controlling of switching value, the most outstanding feature is that speed is fast, hypervelocity, there is cost simultaneously low, versatility is good, stability is high, good reliability, field-programmable and the advantage such as extended capability is strong, when a control cycle Ts Zhong Mei road AI gathers 7 times, PID closed-loop control total cycle of 8 analog quantitys can be low to moderate 289us(and 0.289ms), if a control cycle Ts Zhong Mei road AI gathers be less than 7 times, control cycle can be low to moderate below 100us, superfast control overflow can be met completely.Controller is by RS232-C bus interface, RS422 bus interface (half/Full Duplex RS 485 Bus interface), for connecting host computer or industrial computer, and industrial control network can be connected into as a Controlling vertex in half-duplex RS 485 bus, the control system of complete set is formed with industrial computer, signal regulating panel, controlled device, achieve the integration of control system, user can expand the support RS485 interface of various different performance controller according to different control overflow makes the function of control system more perfect.Controller in the present invention uses the project organization of four layers of fpga core plate+signal regulating panel, signal regulating panel in the present invention is connected with FPGA, and different conditioning plates can be exchanged according to different demands to realize different performances (as changed A/D, D/A precision, increasing interface quantity etc.).

Accompanying drawing explanation

Fig. 1 is the hardware structure diagram of the hypervelocity industrial control unit (ICU) based on FPGA;

Fig. 2 is the connection signal of each virtual functions module in the top layer block scheme design of present system and external pinouts;

Fig. 3 is the state transition graph of DA top level control module DA_top_control.v;

Fig. 4 is the state transition graph of AD top level control modules A D_top_control.v;

Fig. 5 is the state transition graph of AD bottom layer driving modules A D.v;

Fig. 6 is the serial line interface sequential chart of AD7928;

Fig. 7 is the position definition figure of 12 control registers of AD7928;

Fig. 8 is the state transition graph of DA bottom layer driving module DA.v;

Fig. 9 is the serial line interface sequential chart of D/A converter (AD5648);

Figure 10 is the position definition figure of 32 input registers of D/A converter (AD5648);

Figure 11 is the block scheme of asynchronous serial communication receiving interface rx_interface.bdf;

Figure 12 is the state transition graph that asynchronous serial communication bottom receives driver module rx_module.v;

Figure 13 is the state transition graph that asynchronous serial communication upper strata receives control module rx_top_control_module.v;

Figure 14 is the state transition graph that controller communications command word receives control module rx_control.v;

Figure 15 is the state transition graph that controller information sends control module tx_control.v;

Figure 16 is the block scheme of asynchronous serial communication transmission interface tx_interface.bdf;

Figure 17 is the state transition graph that asynchronous serial communication bottom sends driver module tx_module.v;

Figure 18 is the state transition graph that asynchronous serial communication upper strata sends control module tx_top_control_module.v.

Embodiment

Below in conjunction with embodiment and accompanying drawing, a kind of FPGA hypervelocity industrial control system based on Verilog HDL of the present invention is described in detail.

A kind of FPGA hypervelocity industrial control system based on Verilog HDL of the present invention is for based on the hypervelocity industrial control unit (ICU) of FPGA.The structural drawing of the described hypervelocity industrial control unit (ICU) based on FPGA as shown in Figure 1, the fpga core main control chip 1 that the Altera Cyclone III Series FPGA that to comprise by model be EP3C16E144I7 is formed, be connected to 16 road analog input A/D conversion circuit units 7 of the analog signals input end of fpga core main control chip 1, be connected to 8 road analog output D/A conversion circuit units 8 of the analog signals output terminal of fpga core main control chip 1, be connected to 16 way switch amount input signal isolated locations 9 of the on-off model input end of fpga core main control chip 1, be connected to 8 way switch amount output signal isolation and the driver element 10 of the on-off model output terminal of fpga core main control chip 1, described fpga core main control chip 1 is by RS232/ half/full duplex RS485(RS422) bus communication unit 11 connects host computer or access industrial network, described fpga core main control chip 1 connects FPGA independent current source (3.3V, 2.5V, 1.2V) power supply unit 2, fpga core main control chip 1 connects clock input and automatic/hand reset circuit unit 5, fpga core main control chip 1 connects JTAG debug i/f circuit 3, fpga core main control chip 1 connects EPCS16 application configuration chip circuit 4, described fpga core main control chip 1 and described 2, 3, 4, the 5 common four layers of core board forming FPGA hypervelocity industrial control unit (ICU), conditioning plate power supply (5V, ± 12V) power supply unit 6 and described 7, 8, 9, 10, the 11 common two-layer signal regulating panels forming FPGA hypervelocity industrial control unit (ICU).

Only use a slice FPGA as main control chip in Controller gain variations in the present invention, select the EP3C16E144I7 in altera corp Cyclone III Series FPGA, its internal logic resource is quite abundant, frequency is high, postpone little, the analog quantity of industrial control system is completed with it, the data acquisition and controlling of switching value, the most outstanding feature is that speed is fast, hypervelocity, there is speed simultaneously fast, cost is low, versatility is good, stability is high, good reliability, field-programmable and the advantage such as extended capability is strong, when a control cycle Ts Zhong Mei road AI gathers 7 times, PID closed-loop control total cycle of 8 analog quantitys can be low to moderate 289us(and 0.289ms), if a control cycle Ts Zhong Mei road AI gathers be less than 7 times, control cycle can be low to moderate below 100us, superfast control overflow can be met completely.Controller in the present invention has the large class external switch amount interface of DI and DO two, 16 road DI(24V digital quantities inputs) with 8 road DO(30VDC/250VAC, 5A digital outputs) can be used for direct with industrial control system common equipment and the switching value interface of driver module be connected the data acquisition and controlling of industry spot switching value.Controller in the present invention has the large class external analog amount data-interface of A/D and D/A two, 16 road A/D(wherein 8 roads support 4 ~ 20mA simultaneously, 0 ~ 10V analog acquisition, 4 ~ 20mA analog acquisition is only supported on other 8 tunnels) for the flow conventional with industrial control system, the analog signals of pressure and displacement transducer connects with the collection completing industry spot analog signals, 8 road D/A(export with-10 ~+10V through signal amplification, output current is not less than 100mA) for the driver module (AC/DC motor with industrial control system common equipment, servo-valve, surplus valve, rush liquid valve, the driver of reversal valve) connect with the double-polarity control completing industry spot analogue enlargement amount.Controller in the present invention has RS232-C bus interface, RS422 bus interface (half/Full Duplex RS 485 Bus interface), for connecting host computer or industrial computer, and DCS(Distributed Control System (DCS) can be formed as a Controlling vertex in half-duplex RS 485 bus), jointly form the control system of complete set with other equipment in network, achieve the integration of control system.Controller in the present invention all have employed quarantine measures and interference protection measure with the total interface of AI, AO, DI, DO, bus communication in Industry Control system, by the isolation of optocoupler, magnetic coupling, FPGA and other various industry spot signal is connected without any electric loop, thus greatly strengthen the interference free performance of controller, make fpga core plate may be subject to the interference of industry spot hardly and damage.Controller in the present invention is real technical grade hypervelocity controller, on hardware, the type selecting of all chips must ensure to be technical grade chip and make every effort to that integrated level is high, processing speed is fast, as fpga chip EP3C16E144I7, DA chip AD5648, A/D chip AD7928, magnetic coupling chip ADuM series, RS422/RS485 interface chip MAX491ESD etc., the working range of all chips, wider than-40 DEG C ~+85 DEG C, is technical grade hypervelocity controller worthy of the name.Controller in the present invention uses the project organization of four layers of fpga core plate+signal regulating panel, signal regulating panel in the present invention is connected with FPGA, and different conditioning plates can be exchanged according to different demands to realize different performances (as changed A/D, D/A precision, increasing interface quantity etc.).Controller core control chip in the present invention selects the EP3C16E144I7 in altera corp Cyclone III Series FPGA, its internal logic resource is quite abundant, frequency is high, it is little to postpone, for the control algolithm program of writing the complicated logic control programs such as state machine and complexity has established hardware foundation, make hypervelocity control to become possibility, be beneficial to the software upgrading of controller from now on simultaneously.

The EP3C16E144I7 that what the fpga core main control chip 1 of FPGA hypervelocity industrial control unit (ICU) was selected is in altera corp Cyclone III Series FPGA, because the internal logic resource of EP3C16E144I7 is very abundant, so the modular design of carrying out Verilog code or block scheme under Quartus II Integrated Development Environment just seems flexibly abnormal, it is more than sufficient that resource uses, and is more conducive to the upgrading of software from now on and more advance control algorithm and the more realization of complex control logic on the FPGA hypervelocity industrial control unit (ICU) taking EP3C16E144I7 as core main control chip.

The Main Function of FPGA is: the analog input signal AI of maximum No. 16 sensor collections to be converted to by A/D converter the binary message that FPGA can identify by FPGA, then FPGA calculates the due aperture of variable valve according to these information and control algorithms, then through D/A converter and drive amplification circuit, export maximum 8 tunnel-10V ~+10V analog quantity to variable valve, thus reach control object: simultaneously FPGA is by RS232 and RS422(half/full duplex RS485) bus sends all 16 road AI to host computer, the numerical value of 8 road AO and 16 road DI, the state of 8 road DO, host computer can send various control information to FPGA.

As shown in Figure 2, a kind of FPGA hypervelocity industrial control system based on Verilog HDL of the present invention, comprise: DA top level control module 1, one AD bottom layer driving module 2, 2nd AD bottom module 3, AD top level control module 4, DA bottom layer driving module 5, asynchronous serial communication transmission interface 6, asynchronous serial communication receiving interface 7, controller communications command word receives control module 8, controller information sends control module 9, output switch parameter DO Logic control module 10, pid algorithm module 11, PLL phase-locked loop module 12, sine values Rom storer 13, first AD conversion value module Ram14, second AD conversion value module Ram15, analog quantity DA real output value module Ram16, analog quantity closed loop PID control parameter module Ram17, the manual setting value module Ram18 of analog output DA, analog quantity AI set-point module Ram19 and waveform parameter module Ram20.Wherein,

DA top level control module 1, for in a control cycle Ts, receiving according to controller communications command word the analog quantity DA output mode that control module 8 exports selects position AUTO_HAND_DA [31:0] data to carry out the calculating of DA numerical value by a kind of mode in following five kinds of modes, and call the voltage output refreshing that DA bottom layer driving module 5 completes 8 road analog outputs, and stored in analog quantity DA real output value module Ram16, five kinds of described modes are:

First kind of way, manually arranges DA value according to the numerical value read from the manual setting value module Ram18 of analog output DA and exports;

The second way, exports square wave automatically according to the cycle relative value read from waveform parameter module Ram20, peak value, valley;

The third mode, exports triangular wave automatically according to the cycle relative value read from waveform parameter module Ram20, peak value, valley;

4th kind of mode, according to the cycle relative value, peak value, the valley that read from waveform parameter module Ram20, and according to the automatic sine wave output of numerical value read from sine values Rom storer 13;

5th kind of mode, according to the closed loop set-point of the analog input AI corresponding with each road AO passage of 8 road analog outputs read from analog quantity AI set-point module Ram19, with the corresponding closed loop PID control parameter read from analog quantity closed loop PID control parameter module Ram17, call the pid algorithm module 11 for realizing increment type PID algorithm, the PID carrying out single closed loop or two close cycles regulates automatically, calculates DA numerical value and exports.

As shown in Figure 3, in the state transition graph of DA top level control module DA_top_control.v, the major function that DA top level control module DA_top_control.v completes is: in each control cycle Ts=0.2896667ms, to each road AO passage of 8 road analog outputs, 4 all corresponding according to AUTO_HAND_DA [31:0] Zhong Yugai road AO passage bit value, carry out the calculating of DA numerical value by one of following 5 kinds of modes, and call according to the DA value calculated the voltage output refreshing that DA bottom layer driving module DA.v completes D/A converter AD5648.The method (command word form is in table 37) that each road of 8 road AO all sends command word by host computer to controller is configured to the following any one way of output, and the way of output of every road AO is completely independent.Mode 1:AO exports by the DA value manually arranged; Mode 2:AO exports square wave automatically by the cycle relative value arranged, peak value, valley; Mode 3:AO exports triangular wave automatically by the cycle relative value arranged, peak value, valley; Mode 4:AO is by the cycle relative value, peak value, the automatic sine wave output of valley that arrange; Mode 5:AO regulates automatically according to the PID that the closed loop set-point and corresponding closed loop PID control parameter of its corresponding analog input AI carry out single closed loop/two close cycles.

Above-mentioned mode 5 is the most important way of outputs of controller AO, can complete definite value or the servo antrol of maximum 8 tunnel analog quantity AI, and control cycle is only Ts=0.2896667ms.

Single closed loop corresponding relation of AO0 ~ AO3 and AI sees the following form.

Analog output AO---controlled quentity controlled variable

Analog quantity AI---controlled variable

AO0	AI0
		AO1	AI1
AO2	AI2
		AO3	AI3

The two close cycles corresponding relation of AO4 ~ AO7 and AI sees the following form.

Analog output AO---controlled quentity controlled variable	Analog quantity AI---controlled variable (outer shroud)	Analog quantity AI---inner ring variable
			AO4	AI4	AI5
AO5	AI6	AI7
			AO6	AI8	AI9
AO7	AI10	AI11

DA top level control module DA_top_control.v adopts Verilog HDL language to programme, and program is divided into 12 states.Main DA top level control sequential flow process is:

(1) in DA_INIT state, call DA.v and write 2 group of 32 order of the bit word: 32'h08000001 and 32'h040000ff to D/A converter (AD5648), arrange with the initialization and mode of operation that complete D/A converter, after completing, enter Wait_Ts state;

(2), in Wait_Ts state, NUM_DA_Channel<=4'd0 is passed through; Working as pre-treatment DA channel number NUM_DA_Channel clear 0, represent from AO0, carry out DA value calculating and write, original place is waited for until when level saltus step occurs input Ts, and the 8 road DA output valves just starting next control cycle calculate and refresh, and namely enter CAL_e state;

(3), in CAL_e state, from RAM_AD_SP module Ram, AI set-point (8 outer shroud AI:0 that 8 road AO are corresponding, 1,2 are read successively, 3,4,6,8,10) from RAM_AD2 module Ram, read AI sample conversion value (8 outer shroud AI:0 that 8 road AO are corresponding, 1,2,3,4,6,8,10), set-point deducts corresponding sample conversion value as the deviate of outer shroud AI, in the corresponding units stored in Parasites Fauna reg [15:0] e [7:0], then enters DA_MODE_SELECT state;

(4) in DA_MODE_SELECT state, by the value that AUTO_HAND_DA [31:0] and this paths number are 4 MODE [3:0] that the AO of NUM_DA_Channel is corresponding, determine the output mode of this road AO, thus enter calculating and the write that corresponding states carries out DA numerical value: if MODE=0001, enter AO_HAND state; If MODE=0010, enter AO_Fang state; If MODE=0100, enter AO_San state; If MODE=0110, enter AO_Sine state; If MODE=0000 and NUM_DA_Channel<=3, enter AO_PID_DanBiHuan state; If MODE=0000 and NUM_DA_Channel>3, enter AO_PID_ShuangBiHuan state;

(5) in AO_HAND state, this road AO manually exports DA value: the DA reading this road AO from RAM_DA_HAND module Ram manually exports numerical value, and is assigned to D [13:0], enters CALL_DA state;

(6) in AO_Fang state, this road AO exports the square wave of special parameter automatically: from RAM_BOXING_PARAMETER module Ram, read cycle relative value, peak value, valley that this road AO waveform occurs, if the half of the currency < periodic quantity of the square wave counter Fang_Count [NUM_DA_Channel] of this road AO, be then assigned to D [13:0] by peak value; Otherwise valley is assigned to D [13:0]; Then by Fang_Count [NUM_DA_Channel] if from increase 1(be added to periodic quantity, clear 0), above process complete laggard enter CALL_DA state;

(7) in AO_San state, this road AO exports the triangular wave of special parameter automatically: from RAM_BOXING_PARAMETER module Ram, read cycle relative value, peak value, valley that this road AO waveform occurs, if the half of the currency < periodic quantity of the triangular wave counter San_Count [NUM_DA_Channel] of this road AO, then by San_Count [NUM_DA_Channel] × (peak value-valley) ÷ (half of periodic quantity)+valley, be assigned to D [13:0]; Otherwise by (periodic quantity-San_Count [NUM_DA_Channel]) × (peak value-valley) ÷ (half of periodic quantity)+valley, be assigned to D [13:0]; Wherein use LPM_MULT and LPM_DIVIDE that MegaWizard generates under Quartus II, then by San_Count [NUM_DA_Channel] if be added to periodic quantity, clear 0 from increasing 1(), above process complete laggard enter CALL_DA state;

(8) in AO_Sine state, this road AO exports the sine wave of special parameter automatically: from RAM_BOXING_PARAMETER module Ram, read the cycle relative value that this road AO waveform occurs, peak value, valley, if the half of the currency < periodic quantity of the sinusoidal wave counter Sine_Count [NUM_DA_Channel] of this road AO, then Sine_Count [NUM_DA_Channel] × 4095 ÷ (half of periodic quantity) is assigned to Sine_x, the numerical value RdData_ROM_Sine that address is Sine_x is read from ROM_Sine module Rom, finally by RdData_ROM_Sine × (peak value-valley) >>16+ valley, be assigned to D [13:0], otherwise (periodic quantity-Sine_Count [NUM_DA_Channel]) × 4095 ÷ (half of periodic quantity) is assigned to Sine_x, and all the other algorithms are the same, are assigned to D [13:0].Wherein there are 4096 sine values (increasing to 65535 by sinusoidal rule by 0) in ROM_Sine module Rom, can think that the sine value deposited is the decimal of Q16 form, therefore finally RdData_ROM_Sine × (peak value-valley) need be moved to right 16 and just can be converted to Q0 form integer, this module Rom is by the initialization of Rom_Sine_Table_4096dot.mif file.Use LPM_MULT and LPM_DIVIDE that MegaWizard generates under Quartus II; Then by Sine_Count [NUM_DA_Channel] if from increase 1(be added to periodic quantity, clear 0), above process complete laggard enter CALL_DA state;

(9) in AO_PID_DanBiHuan state (AO0 ~ AO3), this road NUM_DA_Channel channel number (0 ~ 3) AO carries out single closed loop PID automatic regulation output DA value according to the AI deviate e [NUM_DA_Channel] of corresponding channel number: the controling parameters numerical value reading closed loop PID corresponding to the AO of this road from RAM_PID_PARAMETER module Ram, according to e [NUM_DA_Channel], e_1 [NUM_DA_Channel], e_2 [NUM_DA_Channel], call PID_CAL_CONTROL.v and obtain delta_u [15:0] through a PID delta algorithm, controlled quentity controlled variable is exported u [NUM_DA_Channel] certainly to add delta_u and carry out upper and lower amplitude limit again, assign it to D [13:0], need 3 deviations to be handled as follows after having carried out PID calculating, prepare for PID during next Ts calculates: e_2 [NUM_DA_Channel] <=e_1 [NUM_DA_Channel], e_1 [NUM_DA_Channel] <=e [NUM_DA_Channel], , above process complete laggard enter CALL_DA state,

(10) in AO_PID_ShuangBiHuan state (AO4 ~ AO7), this road NUM_DA_Channel channel number (4 ~ 7) AO is according to AI (the outer shroud AI:4 of corresponding channel number, 6, 8, 10) deviate e [NUM_DA_Channel] and corresponding inner ring AI(inner ring AI:5, 7, 9, 11) deviate NeiHuan_e [NUM_DA_Channel] carries out double closed-loop PID automatic regulation output DA value: the pid control parameter numerical value 1. first reading outer shroud AI corresponding to the AO of this road from RAM_PID_PARAMETER module Ram, according to e [NUM_DA_Channel], e_1 [NUM_DA_Channel], e_2 [NUM_DA_Channel], call PID_CAL_CONTROL.v and obtain delta_u [15:0] through first time PID delta algorithm, the output valve (i.e. the set-point of inner ring AI) NeiHuan_SP [NUM_DA_Channel] of outer shroud pid algorithm is added delta_u certainly and carries out upper and lower amplitude limit again, 2. from RAM_PID_PARAMETER module Ram, read the pid control parameter numerical value of inner ring AI corresponding to the AO of this road again, inner ring AI sample conversion value is read from RAM_AD2 module Ram, NeiHuan_SP [NUM_DA_Channel] deducts inner ring AI sample conversion value and is assigned to NeiHuan_e [NUM_DA_Channel], according to NeiHuan_e [NUM_DA_Channel], NeiHuan_e_1 [NUM_DA_Channel], NeiHuan_e_2 [NUM_DA_Channel], call PID_CAL_CONTROL.v and obtain delta_u [15:0] through second time PID delta algorithm, controlled quentity controlled variable is exported u [NUM_DA_Channel] certainly to add delta_u and carry out upper and lower amplitude limit again, assign it to D [13:0], carry out after twice PID calculates needing two groups of 3 deviations to be handled as follows, prepared for PID during next Ts calculates:

e_2[NUM_DA_Channel]<=e_1[NUM_DA_Channel];e_1[NUM_DA_Channel]<=e[NUM_DA_Channel];NeiHuan_e_2[NUM_DA_Channel]<=NeiHuan_e_1[NUM_DA_Channel];

NeiHuan_e_1[NUM_DA_Channel]<=NeiHuan_e[NUM_DA_Channel];

, above process complete laggard enter CALL_DA state;

(11), in CALL_DA state, call DA.v and the D obtained in front position [13:0] is write as DA numerical value export to the NUM_DA_Channel passage of D/A converter AD5648: DA_En_Sig<=1'b1; DA_DATAIN<={4'hf, 4'b0011, NUM_DA_Channel, D [13:0], 6'h3f}; Should note representing that write completes as DA_Done_Sig=1, should DA_En_Sig<=1'b0 be had; Again D [13:0] is write in the NUM_DA_Channel unit of RAM_AO module Ram: WrEn_Sig<=1'b1; WrAddr<=NUM_DA_Channel; WrData<={2 ' b00, D [13:0] }; And should WrEn_Sig<=1'b0 be had after write Ram; , above process complete laggard enter CALL_DA state;

(12) in NEXT_DA_Channel state, judge whether current NUM_DA_Channel is less than 7, if NUM_DA_Channel<4'd7, then NUM_DA_Channel is increased 1 certainly, enter DA_MODE_SELECT state; If NUM_DA_Channel=4'd7, then represent that calculating that whole 8 AO in this Ts have completed DA value all refreshes with exporting, get back to Wait_Ts state.

As shown in Figure 4, AD top level control module 4, the poll AD sample conversion of whole 16 road analog input signals is completed for calling an AD bottom layer driving module 2AD.v and the 2nd AD bottom layer driving module 3AD1.v, and by transformation result stored in the first AD conversion value module Ram14 and the second AD conversion value module Ram15, provide the control cycle synchronizing signal Ts of whole system to DA top level control module 1, described AD top level control module 4, for in each control cycle Ts=0.2896667ms, call the poll AD sample conversion that an AD bottom layer driving module 2AD.v and the 2nd AD bottom layer driving module 3AD1.v completes whole 16 road analog input signals, complete based on after the synchronous AD conversion of continuous 7 times an of input channel in 12 the 8 passage A/D converter circuit 73 of the first in the hypervelocity industrial control unit (ICU) of FPGA and second 12 8 passage A/D converter circuit 74 at every turn, after 7 subsynchronous AD conversion results of first 12 8 passage A/D converter circuit 73 and second 12 8 passage A/D converter circuit 74 rear is carried out simple selected and sorted 6 times, again by the middle AD conversion value of first 12 8 passage A/D converter circuit 73 and second 12 8 passage A/D converter circuit 74, stored in the first AD conversion value module Ram14 and the second AD conversion value module Ram15, the control cycle synchronizing signal Ts of whole system is provided to DA top level control module 1.

In AD top level control modules A D_top_control.v state transition graph, the major function that AD top level control modules A D_top_control.v completes is: in each control cycle Ts=0.2896667ms, call that sheet AD7928 interface that 2 AD bottom layer driving modules A D.v(and AI0 ~ AI7 are corresponding) and that sheet AD7928 interface corresponding to AD1.v(and AI8 ~ AI15) (concrete grammar is: export AD_CMD [15:0] and AD_CMD1 [15:0], AD_En_Sig is exported and sets high level until AD_En_Sig output is set low level by AD.v complete when feedback input signal AD_Done_Sig is high level again, read in AD_DATA [15:0] and AD_DATA1 [15:0] obtains AD conversion result) complete the poll AD sample conversion of whole 16 road analog input signals, complete the synchronous AD conversion to continuous 7 times of certain input channel in 2 AD7928 at every turn, after rear 6 effective AD conversion results of 2 AD7928 are carried out simple selected and sorted, by the middle AD conversion value (filtering) of 2 AD7928 stored in the corresponding Ram address of RAM_AD module and RAM_AD1 module.

AD top level control modules A D_top_control.v adopts Verilog HDL language to programme, and program is divided into 7 states.Should be specifically noted that during the programming of complete call AD.v and AD1.v: this module at every turn by export AD_CMD [15:0] and AD_CMD1 [15:0] again AD_En_Sig output is set high level call AD bottom layer driving modules A D.v time, once certain hour (4.770833us) is needed to the read-write of AD7928 because AD.v completes, therefore must wait for until AD_En_Sig output is set low level by AD.v complete when feedback input signal AD_Done_Sig is high level again in original place always, and read in AD_DATA [15:0] at this moment and AD_DATA1 [15:0] just can obtain AD conversion result.Must in strict accordance with above-mentioned sequential carry out just can correctly with AD bottom layer driving modules A D.v interface, thus correctly start AD conversion and read AD conversion numerical value.In the main time control flow of state transition graph and following A D_top_control.v above, all carrying out in strict accordance with above-mentioned sequential when calling AD.v, therefore no longer this being repeated.The main time control flow of AD_top_control.v is:

(1) be in during electrification reset in DUMMY_WR state, by AD conversion call number register Num_CALL_AD clear 0 current in current for AD ALT-CH alternate channel register AD_Channel and CALL_AD state, call AD.v and 5 16'hffff are write to AD7928 void, entirely true to the read-write operation of AD7928 after guaranteeing, enter CALL_AD state after 5 times void writes into;

(2) in CALL_AD state, call 7 AD.v and AD1.v, 7 AD conversion are carried out to the AD_Channel input channel of 2 AD7928,6 effective transformation result AD_DATA and AD_DATA1 be temporarily stored into respectively in Parasites Fauna reg [15:0] AD_Temp [5:0] and reg [15:0] AD_Temp1 [5:0] call at every turn rear all to current AD conversion call number register Num_CALL_AD from increasing 1, represent 7 AD conversion having completed current AD_Channel passage when Num_CALL_AD increases to 7, SORT state need be entered;

(3) in SORT state, first by clear for Num_CALL_AD 0, then 6 16 bit registers in 2 groups of effective AD conversion result register group AD_Temp [5:0] and AD_Temp1 [5:0] are sorted by simple selected and sorted algorithm, after completing sort operation, enter WR_RAM_Channel state;

(4) in WR_RAM_Channel state, be in the unit of AD_Channel by the address that mean value (AD_Temp [2]+AD_Temp [the 3]) >>1'b1 of 2 intermediate values in Parasites Fauna AD_Temp [5:0] is written to RAM_AD module and RAM_AD1 module, therefore complete by the filtering of the AD_Channel passage AD conversion result of first AD7928 and stored in, then enter WR_RAM_Channel_plus8 state;

(5) in WR_RAM_Channel_plus8 state, be in the unit of AD_Channel+4 ' d8 by the address that mean value (AD_Temp1 [2]+AD_Temp1 [the 3]) >>1'b1 of 2 intermediate values in Parasites Fauna AD_Temp1 [5:0] is written to RAM_AD module and RAM_AD1 module, therefore complete by the filtering of the AD_Channel passage of second AD7928 (also i.e. 2 AD7928 AD_Channel+4 ' d8 passage in totally 16 analog input channels, tunnel) AD conversion result and stored in, then NEXT_Channel state is entered,

(6) in NEXT_Channel state, to WrEn_Sig1 clear 0 to terminate the write operation of laststate to RAM_AD module and RAM_AD1 module, judge whether current AD_Channel is 7: if not AD_Channel is increased 1 by 7, and get back to the AD sample conversion that CALL_AD state starts next passage of 2 AD7928; If AD_Channel is 7, represents that transformation result has also write in 0 ~ address, address 15 unit of RAM_AD module and RAM_AD1 module by the poll AD sample conversion completing whole 16 road analog input signals, now should enter next state---Toggle_Ts state;

(7) in Toggle_Ts state, to AD_Channel clear 0, by the level upset of output signal Ts, show the end of a control cycle (0.2896667ms), the change that another module DA_top_control.v detects this signal starts to read 16 tunnel AD conversion values from RAM_AD2 module, and carry out the analog output process such as pid algorithm, this Ts signal visible serves the synchronizing signal of a mark control cycle, get back to CALL_AD state afterwards, start the poll AD sample conversion of the 16 road analog input signals next time of 2 AD7928.

From AD top level control modules A D_top_control.v state transition graph above, whenever completing the cycle of states of a CALL_AD → SORT → WR_RAM_Channel → WR_RAM_Channel_plus8 → NEXT_Channel → Toggle_Ts → CALL_AD, namely complete the poll AD sample conversion of the whole 16 road analog input signals of this control cycle and transformation result write in 0 ~ address, address 15 unit of RAM_AD module and RAM_AD1 module, FPGA clock periodicity used is: ((229+2+11+2) × 7+ (7+6+5+4+3+1)+4) × 8=13904, FPGA clock 48MHz, therefore control cycle is 22913904 × 1/48 (us)=0.2896667 (ms).

As shown in Figure 5, one AD bottom layer driving module 2, for receiving the 16 bit parallel control words that AD top level control module (4) sends, convert SPI serial line interface sequential to, write is based on 12 the 8 passage A/D converter circuit of the first in the hypervelocity industrial control unit (ICU) of FPGA, control this circuit and carry out AD conversion, and the data parallel of transformation result is outputted to AD top level control module 4, 2nd AD bottom module 3, for receiving the 16 bit parallel control words that AD top level control module (4) sends, convert SPI serial line interface sequential to, write is based on 12 the 8 passage A/D converter circuit of second in the hypervelocity industrial control unit (ICU) of FPGA, control this circuit and carry out AD conversion, and the data parallel of transformation result is outputted to AD top level control module 4, a described AD bottom layer driving module 2 is identical with the 2nd AD bottom module 3 structure, wherein, a described AD bottom layer driving module 2 is in the read-write cycle 4.770833us of an A/D converter (AD7928), convert the parallel control word that reception AD top level control module 4 sends to SPI serial line interface sequential, write is based on 12 8 passage A/D converter (AD7928) circuit 73 of the first in the hypervelocity industrial control unit (ICU) of FPGA, and 16 data parallels comprising a upper read-write cycle AD conversion result read from first 12 8 passage A/D converter circuit serial are outputted to AD top level control module 4, the 2nd described AD bottom module 3 is in the read-write cycle 4.770833us of an A/D converter (AD7928), parallel control word for reception AD top level control module 4 being sent converts SPI serial line interface sequential to, 16 data parallels comprising a upper read-write cycle AD conversion result read from second 12 8 passage A/D converter circuit serial based on 12 8 passage A/D converter (AD7928) circuit 74 of second in the hypervelocity industrial control unit (ICU) of FPGA, and are outputted to AD top level control module 4 by write.

In the state transition graph of AD bottom layer driving modules A D.v, the major function that AD bottom layer driving modules A D.v completes is: in the read-write cycle 4.770833us of an AD7928, the AD_CMD [15:0] sent by upper layer module AD_top_control.v according to the SPI serial interface operations sequential serial write AD7928 by turn of the first high-order rear low level of AD7928, and will output to AD_DATA [15:0] for AD_top_control.v reading from 16 data comprising a upper read-write cycle AD conversion result of AD7928 reading simultaneously.

AD bottom layer driving modules A D.v adopts Verilog HDL language to programme, and program is divided into 9 states.Main AD sequential control flow process is:

(1) in IDLE state, by clear for AD_Done_Sig 0, this module is in idle idle waiting status, at this moment the AD_En_Sig input signal that the upper layer module (AD_top_control.v) of calling this module is sent can be detected in real time, if AD_En_Sig=0, just keep IDLE state, as long as AD_En_Sig=1 detected at the rising edge of continuous 2 FPGA clock CLK, enter CS_LOW state immediately;

(2), in CS_LOW state, AD_CS output signal is set to low level, the read-write operation of enable AD7928; 16 data AD_CMD to be sent [15:0] that the temporary upper layer module (AD_top_control.v) calling this module inputs are in register rAD_CMD [15:0]; Current transmission position indicator register Index_Bit is initialized as 15(16 bit data and first sends out most significant digit), Index_Bit be used to refer to current just the external serial of AD_DATA send pin exporting in rAD_CMD [15:0] who, complete this process laggard enter CLK_HIGH state;

(3) in CLK_HIGH state, AD_CLK output signal is set to high level, simultaneously by rAD_CMD [Index_Bit] position State-output on AD_MOSI pin, read for AD7928, record be input as the counter CiShu_1 clear 0 of 1 from AD7928 sense data AD_MISO; In this state, when each FPGA clock CLK rising edge triggers, counter C1 from increasing 1, enters Rd_MISO state as C1=4;

(4) in Rd_MISO state, because CLK_HIGH state provides enough data write Times Created to AD7928, therefore the level state of AD_MISO input pin can be read in this state, implementation method just CiShu_1 is increased 1 when often detecting that AD_MISO is input as 1 to read serial data with record from AD7928 be the number of times of 1, in this state, when each FPGA clock CLK rising edge triggers, counter C1 from increasing 1, enters CLK_LOW state as C1=7;

(5) in CLK_LOW state, AD_CLK output signal is set to low level, and AD7928 latches the AD_MOSI pin state set in CLK_HIGH state at the negative edge of AD_CLK, complete a write operation to AD7928; Cause CiShu_1 in Rd_MISO state have recorded and inputs to the AD_MISO of AD7928 the number of times that 3 times are sampled as high level, then according to " the minority is subordinate to the majority " principle of signal condition sampling, think that AD_MISO is input as high level when CiShu_1 is greater than 1, by AD_DATA [Index_Bit] position 1, otherwise AD_DATA [Index_Bit] position clear 0, counter C1 is entered MOSI_HOLD state after increasing 1;

(6) in MOSI_HOLD state, the CLK clock period of time delay 6 FPGA, to provide enough data write retention times to AD7928, when implementation method is the triggering of each FPGA clock CLK rising edge, counter C1 from increasing 1, enters NEXT_BIT state as C1=13;

(7) in NEXT_BIT state, first by clear for C1 0, judge whether current I ndex_Bit is 0: if not 0 expression not yet completes the 16 bit data write/reads of AD7928, then Index_Bit is subtracted 1, and get back to the data write/read that CLK_HIGH state starts next bit; If Index_Bit is 0, represents and this time the 16 bit data write/reads of AD7928 all completed, at this moment should enter next state---CS_HIGH state;

(8) in CS_HIGH state, AD_CS output signal is set to high level, terminates the read-write operation this time to AD7928, AD_CLK signal is drawn high simultaneously, enter ACK state;

(9) in ACK state, AD_Done_Sig output signal is set to high level, only namely the AD_Done_Sig signal of 1 FPGA clock can be used as feeding back ACK and informs the upper layer module (AD_top_control.v) calling this module: the AD_CMD [15:0] that AD_top_control.v has sent by this A/D module writes AD7928 according to the SPI serial interface operations sequential serial-by-bit of low level after AD7928 first a high position, and 16 data comprising a upper read-write cycle AD conversion result simultaneously read from AD7928 are outputted to AD_DATA [15:0] for AD_top_control.v reading, so far, this A/D module completes the read-write cycle of an AD7928, returns to IDLE state and waits for upper layer module next time calling this A/D module.

From AD bottom layer driving modules A D.v state transition graph above, CLK_HIGH → Rd_MISO → CLK_LOW → MOSI_HOLD → NEXT_BIT is as the main transition status read and write AD7928 according to SPI protocol, circulate 16 times altogether, the rising edge at every turn circulating in clock AD_CLK exports AD_MOSI, AD_MISO was read before the negative edge of clock AD_CLK, and subtract 1, to complete the displacement send/receive operation of 16 bit registers in the last value by current transmission position indicator register Index_Bit of each circulation.In each circulation, the rising edge of each FPGA clock CLK all can flip-flop number C1 from increase 1(C1 increase to 13 after by clear for C1 0), C1 enters after being incremented to 13 by 0 and circulates next time, visible each cycle period is 14 FPGA clock period, this cycle period is exactly the cycle of this module output clock AD_CLK, the frequency of AD_CLK is 14 frequency divisions of FPGA clock 48MHz: 48 (MHz)/14=3.429 (MHz), meet the requirement of AD7928 to input clock frequency≤20MHz.

This A/D module returns IDLE state FPGA clock periodicity used by IDLE state execution one circle: 2+16 × 14+3=229, FPGA clock 48MHz, therefore the read-write cycle of an AD7928 of this A/D module is 229 × 1/48 (us)=4.770833 (us)=4770.833 (ns).

As shown in Figure 6, be the serial line interface sequential chart of AD7928.

As shown in Figure 7, be the position definition figure of 12 control registers of AD7928.Numerical value in control register can under control AD7928 be operated in specific operation mode, and 16 bit data forms to AD7928 write used in my design (12 control registers+4 independent bits, high-order at front low level rear) are as follows.

WRITE|SEQ| independent bit | ADD2|ADD1|ADD0|PM1|PM0|SHADOW| independent bit | RANGE|CODING| independent bit [3:0]

1 0 1 ADD2|ADD1|ADD0 1 1 0 1 0/1 1 0000

In 2 AD7928 of controller, the 8 road analog inputs corresponding with the AD7928 of AD.v interface are AI0 ~ AI7, and the CODING position in its command word is set to 0, represent that AI0 ~ AI7 analog input scope is configured to 0V ~ 2 × REFin, i.e. 0V ~ 5V; The 8 road analog inputs corresponding with the AD7928 of AD1.v interface are AI8 ~ AI15, and the CODING position in its command word is set to 1, represent that AI8 ~ AI15 analog input scope is configured to 0V ~ REFin, i.e. 0V ~ 2.5V.Wherein, REFin is the external reference-voltage source 2.5V of AD7928.

The 16 bit data forms (high-order at front low level rear) read from AD7928 are:

0|ADD2|ADD1|ADD0(3 bit port identifier) | DB [11:0] (12 AD conversion results of a upper read-write cycle)

The input channel determined by ADD [2:0] of these 16 the data representation AD7928 read has collected the magnitude of voltage (AI0 ~ AI7 be 0 ~ 5V, AI8 ~ AI15 be 0 ~ 2.5V) corresponding with 12 bit value DB [11:0] (0 ~ 4095).Input voltage vin=2.5V × the DB [11:0]/4096 of input voltage vin=5V × DB [11:0]/4096, the AI8 ~ AI15 of AI0 ~ AI7.

In strict accordance with the above-mentioned 16 bit data forms to AD7928 write, 16 bit data write to AD7928 are exported to AD_CMD [15:0] by upper layer module AD_top_control.v, output AD_En_Sig is put 1 simultaneously, then just wait for until the AD_Done_Sig output of AD.v just will export AD_En_Sig clear 0 after putting 1, this represents AD.v according to the SPI serial interface operations sequential serial-by-bit write AD7928 of low level after AD7928 first a high position, and 16 data comprising a upper read-write cycle AD conversion result simultaneously read from AD7928 are outputted to AD_DATA [15:0], at this moment AD_top_control.v reads AD_DATA [15:0] numerical value, and in strict accordance with the above-mentioned 16 bit data forms read from AD7928 stored in 12 AD conversion results of a upper read-write cycle.

As shown in Figure 8, DA bottom layer driving module 5, converts SPI serial line interface sequential to for 32 bit parallel control words DA top level control module 1 sent, and writes based on 14 8 passage D/A converter (AD5648) circuit 82 in the hypervelocity industrial control unit (ICU) of FPGA.

In DA bottom layer driving module DA.v state transition graph, the major function that DA bottom layer driving module DA.v completes is: the DA_DATAIN [31:0] sent by upper layer module DA_top_control.v is according to SPI serial interface operations sequential serial write D/A converter (AD5648) by turn of low level after D/A converter (AD5648) first a high position.

DA bottom layer driving module DA.v adopts Verilog HDL language to programme, and program is divided into 8 states.Main DA sequential control flow process is:

(1) in IDLE state, by clear for DA_Done_Sig 0, this module is in idle idle waiting status, at this moment the DA_En_Sig input signal that the upper layer module (DA_top_control.v) of calling this module is sent can be detected in real time, if DA_En_Sig=0, just keep IDLE state, as long as DA_En_Sig=1 detected at the rising edge of continuous 2 FPGA clock CLK, enter SYNC_LOW state immediately;

(2), in SYNC_LOW state, DA_SYNC output signal is set to low level, the write operation of enable D/A converter (AD5648); 32 data DA_DATAIN to be sent [31:0] that the temporary upper layer module (DA_top_control.v) calling this module inputs are in register da_ram [31:0]; Current transmission position indicator register Index_Bit is initialized as 31(32 bit data and first sends out most significant digit), Index_Bit be used to refer to current just the external serial of da_data send pin exporting in da_ram [31:0] who, complete this process laggard enter CLK_HIGH state;

(3) in CLK_HIGH state, by da_clk output signal be set to high level, simultaneously by da_ram [Index_Bit] position State-output on da_data pin, read for D/A converter (AD5648); In this state, when each FPGA clock CLK rising edge triggers, counter C1 from increasing 1, enters CLK_LOW state as C1=8;

(4) in CLK_LOW state, provide enough data to D/A converter (AD5648) because of CLK_HIGH state and write Time Created, so time can by da_clk output signal be set to low level, D/A converter (AD5648) latches the da_data pin state set in CLK_HIGH state at the negative edge of da_clk, complete a write operation to D/A converter (AD5648), counter C1 enters data_HOLD state after increasing 1;

(5) in data_HOLD state, the CLK clock period of time delay 5 FPGA, with the data write retention time providing enough to D/A converter (AD5648), when implementation method is the triggering of each FPGA clock CLK rising edge, counter C1 from increasing 1, enters NEXT_BIT state as C1=14;

(6) in NEXT_BIT state, first by clear for C1 0, judge whether current I ndex_Bit is 0: if not the 0 32 bit data writes of expression to D/A converter (AD5648) not yet completes, then Index_Bit is subtracted 1, and get back to the data write that CLK_HIGH state starts next bit; If Index_Bit is 0, represents and this time 32 bit data writes of D/A converter (AD5648) all completed, at this moment should enter next state---SYNC_HIGH state;

(7) in SYNC_HIGH state, da_sync output signal is set to high level, terminates the write operation this time to D/A converter (AD5648), da_ldac signal is dragged down simultaneously, enter ACK state;

(8) in ACK state, DA_Done_Sig output signal is set to high level, and only namely the DA_Done_Sig signal of 1 FPGA clock can be used as feeding back ACK and informs the upper layer module (DA_top_control.v) calling this module: the DA_DATAIN [31:0] that DA_top_control.v has sent by this D/A module writes D/A converter (AD5648) according to the SPI serial interface operations sequential serial-by-bit of low level after D/A converter (AD5648) first a high position; So far, this D/A module completes the write cycle time of a D/A converter (AD5648), returns to IDLE state and waits for upper layer module next time calling this D/A module.

From DA bottom layer driving module DA.v state transition graph above, CLK_HIGH → CLK_LOW → data_HOLD → NEXT_BIT is as the main transition status write D/A converter (AD5648) according to SPI protocol, circulate 32 times altogether, the rising edge at every turn circulating in clock da_clk exports da_data, and subtract 1, to complete the displacement transmit operation of 32 bit registers in the last value by current transmission position indicator register Index_Bit of each circulation.In each circulation, the rising edge of each FPGA clock CLK all can flip-flop number C1 from increase 1(C1 increase to 14 after by clear for C1 0), C1 enters after being incremented to 14 by 0 and circulates next time, visible each cycle period is 15 FPGA clock period, this cycle period is exactly the cycle of this module output clock da_clk, the frequency of da_clk is 15 frequency divisions of FPGA clock 48MHz: 48 (MHz)/15=3.2 (MHz), meets D/A converter (AD5648) to the requirement of input clock frequency≤50MHz.

This D/A module returns IDLE state FPGA clock periodicity used by IDLE state execution one circle: 2+32 × 15+2=484, FPGA clock 48MHz, therefore the write cycle time of a D/A converter (AD5648) of this D/A module is 484 × 1/48 (us)=10.08333 (us).

As shown in Figure 9, be the serial line interface sequential chart of D/A converter (AD5648).

As shown in Figure 10, be D/A converter (AD5648) 32 input registers position definition figure.Numerical value in input register can control under D/A converter (AD5648) is operated in specific operation mode, uses maximum to write and to upgrade the 32 bit data forms that DAC passage A [3:0] orders as follows to D/A converter (AD5648) in my design.

Independent bit [3:0] | C3|C2|C1|C0|A3|A2|A1|A0 | D [13:0] | independent bit [5:0]

1111 0 0 1 1 A3|A2|A1|A0 |D[13:0]| 111111

This order represents that the passage determined by A [3:0] to D/A converter (AD5648) exports the magnitude of voltage (0 ~ 5V) corresponding with 14 bit value D [13:0] (0 ~ 16383).Output voltage Vout=5V × D [13:0]/16384.

In strict accordance with the above-mentioned 32 bit data forms write to D/A converter (AD5648), 32 bit data that upper layer module DA_top_control.v will write to D/A converter (AD5648) export to DA_DATAIN [31:0], output DA_En_Sig is put 1 simultaneously, then just wait for until the DA_Done_Sig of DA.v export put 1 after just by clear for DA_En_Sig 0, this represent DA.v first high-order according to D/A converter (AD5648) after SPI serial interface operations sequential serial-by-bit write D/A converter (AD5648) of low level.

As shown in figure 11, asynchronous serial communication receiving interface 7, for receiving the signal inputted based on the communication numeral buffer circuit 111 in the hypervelocity industrial control unit (ICU) of FPGA, and the asynchronous serial communication of write inside receives in fifo module, receives control module 8 read for controller communications command word.Described asynchronous serial communication receiving interface 7 includes, asynchronous serial communication bottom receives driver module 71rx_module.v, asynchronous serial communication upper strata receives control module 72rx_top_control_module.v, asynchronous serial communication receives fifo module 73rx_fifo_module, wherein, described asynchronous serial communication upper strata receives control module 72 and calls the reception that asynchronous serial communication bottom reception driver module 71 completes frame data, receive to asynchronous serial communication 8 bit parallel data just received that fifo module 73 writes 1 byte, move in circles; Described asynchronous serial communication bottom receives driver module 71 under the control of asynchronous serial communication upper strata reception control module 72, to input port RX_Pin_In state according to 1 start bit in asynchronous serial communication (' 0')+8 data bit+1 position of rests (' 1'), the timing conversion of the frame format of no parity check position becomes 8 bit parallel data to read for asynchronous serial communication upper strata reception control module 72, and described input port RX_Pin_In is configured to the reception pin of 1 road RS422 or full duplex RS485 or the reception pin of 2 road RS232-C; The information that described asynchronous serial communication reception fifo module 73 receives the write of asynchronous serial communication upper strata reception control module 72 reads for controller communications command word reception control module 8.

In the block scheme of asynchronous serial communication receiving interface rx_interface.bdf, the major function that rx_interface.bdf completes is: this module is by inner rx_module.v, rx_top_control_module.v, the cooperation control of rx_fifo_module module, input port RX_Pin_In completes asynchronous serial communication Frame reception and write 1024 × 8bit asynchronous serial communication receive FIFO---in rx_fifo_module module, this serial communication receives FIFO and other external module interfaces, as long as external module detects to receive in FIFO have number (Empty_Sig=1 ' b0), namely after Read_Req_Sig being set to high level FPGA clock, FIFO_Read_Data [7:0] is read in again as 1 byte data received by asynchronous serial communication.The degree of depth be 1024 asynchronous serial communication receive FIFO can greatly alleviate other external modules receive request of data therewith receiving interface externally carry out the speed mismatch problem of Asynchronous Reception by specific baud rate.The module that asynchronous serial communication receiving interface rx_interface.bdf uses comprises: asynchronous serial communication bottom receives driver module rx_module.v, asynchronous serial communication upper strata receives control module rx_top_control_module.v, and asynchronous serial communication receives fifo module rx_fifo_module.

As shown in figure 12, asynchronous serial communication bottom receives in the state transition graph of driver module rx_module.v, the major function that rx_module.v completes is: when the RX_En_Sig of upper layer module rx_top_control_module.v is high level, to RX_Pin_In input port state according to 1 start bit in asynchronous serial communication (' 0')+8 data bit+1 position of rests (' 1'), the sequential of the frame format of no parity check position outputs to RX_Data [7:0] by turn and reads for rx_top_control_module.v, RX_Pin_In can be configured to 1 road RS422(full duplex RS485) reception pin or the reception pin of 2 road RS232-C.

Asynchronous serial communication bottom receives driver module rx_module.v and adopts Verilog HDL language to programme, and program is divided into 8 states.Main asynchronous serial communication bottom receives sequential control flow process:

(1) in IDLE state, by clear for RX_Done_Sig 0, by clear for Index_Bit 0, this module is in idle idle waiting status, at this moment the input port state of RX_Pin_In can be detected in real time, if RX_Pin_In input signal detected by high level to low level saltus step, enter Start_Bit state immediately, and by counter C1 assignment for 2 to compensate 2 the FPGA clocks detecting level saltus step and spend; If the negative edge of RX_Pin_In do not detected, just keep IDLE state;

(2) in Start_Bit state, the baud rate provided according to asynchronous serial communication receiving-transmitting sides carries out the time delay of a period of time, delay time constant Delay_BaudRate=(1/ baud rate (bps))/(1/48000000)-2, when time delay implementation method is the triggering of each FPGA clock CLK rising edge, if current C 1<Delay_BaudRate+1, by counter C1 from increasing 1, otherwise Delay_Half_Bit state need be entered by clear for C1 0 as C1=Delay_BaudRate+1;

(3) in Delay_Half_Bit state, need the half the time Delay_BaudRate>>1 of time delay Delay_BaudRate, when time delay implementation method is the triggering of each FPGA clock CLK rising edge, counter C1 from increasing 1, enters Middle_Sample state as C1=Delay_BaudRate>>1 ' b1;

(4) in Middle_Sample state, the input state of now RX_Pin_In is assigned to RX_Data [Index_Bit], this moment is the middle moment in asynchronous serial communication 1 bit data, the level state now receiving line RX_Pin_In is the most stable, and therefore the effect of Delay_Half_Bit state is above exactly ensure to sample when appearing at half bit time after receiving on line to bits per inch certificate in this state this bit data; Delay2_Half_Bit state is entered after 1 is increased to C1

(5) in Delay2_Half_Bit state, need the residue half the time of time delay Delay_BaudRate, when time delay implementation method is the triggering of each FPGA clock CLK rising edge, counter C1 from increasing 1, enters NEXT_BIT state as C1=Delay_BaudRate;

(6) in NEXT_BIT state, first by clear for C1 0, judge whether current I ndex_Bit is 7: if not 7 represent that 8 valid data positions in frame data not yet all receive and read in RX_Data [7:0], then Index_Bit is added 1, and get back to the data receiver that Delay_Half_Bit state starts next bit; If Index_Bit is 7, represent that 8 valid data positions in these frame data have all received and read in RX_Data [7:0], only remain last position of rest, at this moment should enter next state---Stalk_Bit state;

(7) in Stalk_Bit state, for ensureing that this module gets back to IDLE state in time to detect the negative edge of RX_Pin_In and the Frame can not missed on RX_Pin_In input port, the delay clock number that does need be less than Delay_BaudRate and leave surplus, here the half the time Delay_BaudRate>>1 of we time delay Delay_BaudRate, when time delay implementation method is the triggering of each FPGA clock CLK rising edge, counter C1 is from increasing 1, ACK state is entered as C1=Delay_BaudRate>>1 ' b1,

(8) in ACK state, RX_Done_Sig output signal is set to high level, only namely the RX_Done_Sig signal of 1 FPGA clock can be used as feeding back ACK and informs the upper layer module (rx_top_control_module.v) calling this module: this rx_module.v module from RX_Pin_In receiving port according to 1 start bit asynchronous serial communication (' 0')+8 data bit+1 position of rests (' 1'), the sequential of the frame format of no parity check position outputs in RX_Data [7:0] by turn; So far, this rx_module.v module completes the reception of an asynchronous serial frame, returns to the reception that IDLE state waits for next frame data.

Upper layer module rx_top_control_module.v waits for until the RX_Done_Sig output of rx_module.v just can read in RX_Data [7:0] after putting 1, at this moment RX_Data [7:0] is exactly 8 valid data positions in the frame data that just received of RX_Pin_In input port, RX_Pin_Out is configured to respective pins and can realizes RS422(full duplex RS485) or the reception of RS232-C.

As shown in figure 13, asynchronous serial communication upper strata receives in the state transition graph of control module rx_top_control_module.v, the major function that rx_top_control_module.v completes is: call asynchronous serial communication bottom and receive driver module rx_module.v and complete the reception of frame data (concrete grammar is: RX_En_Sig is exported perseverance and is set to high level, wait for until the feedback input signal RX_Done_Sig that completes of rx_module.v is high level always, at this moment RX_Data [7:0] input is just by byte data that asynchronous serial communication receives), to asynchronous serial communication reception, FIFO---rx_fifo_module module writes the data RX_Data [7:0] just received of 1 byte, move in circles.

Asynchronous serial communication upper strata receives control module rx_top_control_module.v and adopts Verilog HDL language to programme, and program is divided into 4 states.The main time control flow of rx_top_control_module.v is:

(1) in CALL_rx_module state, RX_En_Sig is exported perseverance and be set to high level to call asynchronous serial communication bottom reception driver module rx_module.v, wait for until the feedback input signal RX_Done_Sig that completes of rx_module.v is high level in this state always, at this moment the reception of frame data has been completed, the byte data now just received by asynchronous serial communication in the input line of RX_Data [7:0] effectively, enter Is_Full state.

(2) in Is_Full state, asynchronous serial communication can be detected in real time and receive FIFO---whether rx_fifo_module module is full, if receive FIFO for full (Full_Sig=1), waits in this state; If receiving FIFO is not full (Full_Sig=0), a byte data write rx_fifo_module module that can will just receive is described, enters Write_HIGH state;

(3) in Write_HIGH state, RX_Data [7:0] is assigned to FIFO_Write_Data [7:0], and will writes after FIFO request signal Write_Req_Sig puts 1, enter Write_LOW state immediately;

(4) in Write_LOW state, FIFO request signal Write_Req_Sig in time clear 0 will be write, and ensure the data just received only writing 1 byte in rx_fifo_module module, return CALL_rx_module state.

As shown in figure 14, controller communications command word receives control module 8, for from asynchronous serial communication receiving interface 7 sense data, all School Affairs calculating is carried out after often reading 10 byte command words of host computer transmission, (table 37) controller communications command word according to setting receives resolution table, separated out the implication of host computer command word by the first character joint received and function code numerical solution, thus carry out corresponding command analysis and optimum configurations.

Controller communications command word receives in the state transition graph of control module rx_control.v, the major function that rx_control.v completes is: from rx_interface.v sense data, all School Affairs calculating is carried out after often reading 10 byte command words of host computer transmission, resolution table is received according to the controller communications command word shown in table 1, separated out the implication of host computer command word by the first character joint received and function code numerical solution, thus carry out corresponding command analysis and optimum configurations.

Table 1

Controller communications command word receives control module rx_control.v and adopts Verilog HDL language to programme, and program is divided into 11 states.Main controller communications command word receives Control timing sequence flow process:

(1) in Rec_10Byte state, as long as the reception FIFO of rx_interface.v is not empty just continuous from rx_interface.v sense data, and by the data of reading stored in Parasites Fauna reg [7:0] Rec [9:0], enter Resolve state when the serial communication of reading enough 10 bytes receives data;

(2) in Resolve state, because last byte in we the 10 byte command words that send of regulation host computer is the School Affairs of front 9 bytes, therefore first calculate School Affairs by Rec [0]-Rec [8], if this School Affairs and unequal explanation of Rec [9] receive mistake, then by clear for Num_Rec_Byte 0, return Rec_10Byte state; If School Affairs is equal, saves Rec [0] i.e. function code numerical value by the first character received and determine that will enter which state carries out related command parsing and optimum configurations: if Rec [0]=0, enter DO_SET state; If Rec [0]=0, enters DO_SET state; If Rec [0]=1, enters AO_HAND state; If Rec [0]=2, enters AO_Fang state; If Rec [0]=3, enters AO_San state; If Rec [0]=4, enters AO_Sine state; If Rec [0]=5, enters AO_PID_Enable state; If Rec [0]=6, enters AI_SP state; If Rec [0]=7, enters AI_PID_PARAMETER state;

(3) in DO_SET state, output switch parameter DO hand/Lookup protocol is carried out according to Rec [1] numerical value, revise the interface line of this module and DO.v: the manual setting value of DO---Hand_DOData [7:0], DO automatically (0)/manually (1) selects position---Auto_Hand_Select [7:0], automatically refer to by the logic control DO state of DO.v inside modules, it is corresponding that this two group interfaces line big-endian exports DO7 ~ DO0 with 8 way switch amounts respectively, enters LED_Toggle state after completing the whole process in this state;

(4) in AO_HAND state, the DA value of carrying out certain road analog output AO according to Rec [1]-Rec [3] numerical value is manually arranged, DA is manually worth in the write RAM_DA_HAND module Ram unit corresponding with this road AO, and export 0001 by corresponding for AUTO_HAND_DA [31:0] Zhong Yugai road AO passage 4, represent that this road AO path manual exports DA value, after completing the whole process in this state, enter LED_Toggle state;

(5) in AO_Fang state, the setting that certain road analog output AO generates square wave is automatically carried out according to Rec [1]-Rec [8] numerical value, the cycle relative value (the control cycle Ts relative to controller) of waveform, peak value, valley are write in the RAM_BOXING_PARAMETER module Ram unit corresponding with this road AO, and export 0010 by corresponding with this road AO 4 of AUTO_HAND_DA [31:0], represent that this road AO passage exports square wave automatically, after completing the whole process in this state, enter LED_Toggle state;

(6) in AO_San state, the setting that certain road analog output AO generates triangular wave is automatically carried out according to Rec [1]-Rec [8] numerical value, the cycle relative value (the control cycle Ts relative to controller) of waveform, peak value, valley are write in the RAM_BOXING_PARAMETER module Ram unit corresponding with this road AO, and export 0100 by corresponding with this road AO 4 of AUTO_HAND_DA [31:0], represent that this road AO passage exports triangular wave automatically, after completing the whole process in this state, enter LED_Toggle state;

(7) in AO_Sine state, carry out certain road analog output AO according to Rec [1]-Rec [8] numerical value and automatically generate sinusoidal wave setting, the cycle relative value (the control cycle Ts relative to controller) of waveform, peak value, valley are write in the RAM_BOXING_PARAMETER module Ram unit corresponding with this road AO, and export 0110 by corresponding with this road AO 4 of AUTO_HAND_DA [31:0], represent the automatic sine wave output of this road AO passage, after completing the whole process in this state, enter LED_Toggle state;

(8) in AO_PID_Enable state, closed loop PID according to Rec [1] numerical value certain road enable analog output AO regulates automatically, 0000 is exported by corresponding with this road AO for AUTO_HAND_DA [31:0] 4, represent that this road AO passage is configured to closed loop PID automatic regulation output DA value, after completing the whole process in this state, enter LED_Toggle state;

(9) in AI_SP state, the closed loop set-point carrying out certain road analog input AI according to Rec [1]-Rec [2] numerical value is arranged, by in unit corresponding with this road AI for the closed loop set-point of this road AI write RAM_AD_SP module Ram, after completing the whole process in this state, enter LED_Toggle state;

(10) in AI_PID_PARAMETER state, the closed loop PID control optimum configurations of certain road analog input AI is carried out according to Rec [1]-Rec [7] numerical value, by in unit corresponding with this road AI for the closed loop PID control parameter read-in RAM_PID_PARAMETER module Ram of this road AI, after completing the whole process in this state, enter LED_Toggle state;

(11), in LED_Toggle state, overturn the level thus the light on and off change of generation LED that externally export Rec_LED, carry out indicating control with this and carried out optimum configurations by the command word of 10 bytes of host computer transmission; Byte counter Num_Rec_Byte clear 0 will be received simultaneously, get back to Rec_10Byte state.

When described function code numerical value is 0, described controller communications command word receives control module 8 and refreshes the data exporting to output switch parameter DO Logic control module 10 according to received command word; When described function code numerical value is 2,3 and 4, described controller communications command word receives control module 8, according to received command word, waveform parameter is write waveform parameter module Ram20, and refreshes analog quantity DA output mode selection position AUTO_HAND_DA [31:0] data exporting to DA top level control module 1; When described function code numerical value is 1, described controller communications command word receives control module 8, according to received command word, the DA of analog output AO is manually worth the manual setting value module Ram18 of write analog output DA, and refreshes analog quantity DA output mode selection position AUTO_HAND_DA [31:0] data exporting to DA top level control module 1; When described function code numerical value is 5, described controller communications command word receives control module 8 and refreshes analog quantity DA output mode selection position AUTO_HAND_DA [31:0] data exporting to DA top level control module 1 according to received command word; When described function code numerical value is 6, described controller communications command word receives control module 8 according to received command word by the closed loop set-point of road analog input write analog quantity AI set-point module Ram19; When described function code numerical value is 7, described controller communications command word receives control module 8 according to the closed loop PID control parameter read-in analog quantity closed loop PID control parameter module Ram17 of received command word by a road analog input.

Output switch parameter DO Logic control module 10, for reading in 16 way switch amount input state signals, and exports 8 way switch amount output status signals according to the pattern that controller communications command word reception control module 8 sets.The major function that output switch parameter DO Logic control module DO.v completes is: when input Auto_Hand_Select [7:0] corresponding positions is 0, exported by the self-defined logical drive of this module this road DO; When Auto_Hand_Select [7:0] corresponding positions inputted is 1, this road DO is driven to export by input Hand_DOData [7:0] corresponding position; Reading in 16 way switch amount input states exports as DI_STATE [15:0], exports 8 way switch amount output states for DO_STATE [7:0].

As shown in figure 15, controller information sends control module 9, respectively: the numerical value reading 16 way switch amount input states and 8 way switch amount output states from output switch parameter DO Logic control module 10,12,16 analog input channel, tunnel AD conversion value is read from the first AD conversion value module Ram14,14,8 analog output channel, tunnel DA numerical value is read from analog quantity DA real output value module Ram16, and by the numerical value that the reads order format write asynchronous serial communication transmission interface 6 by setting, and this process of transmitting is moved in circles carry out.Described controller information sends control module 9 to host computer circulation transmit control device status information, in each transmission circulation, this controller information sends the controller state information that control module 9 sends 52 bytes altogether: the reception synchronizing information of 0x55 as host computer first sending a byte, then from first AD conversion value module Ram14 read 16 × 12bit totally 32 bytes 16 road AI numerical value and send, then from analog quantity DA real output value module Ram16 read 8 × 14bit totally 16 bytes 8 road AO numerical value and send, the numerical value of 16 way switch amount input states and 8 way switch amount output states totally 3 bytes is finally read from output switch parameter DO Logic control module 10.

Controller information sends in the state transition graph of control module tx_control.v, the major function that tx_control.v completes is: be responsible for 12,16 analog input channel, the tunnel AD conversion value collected by controller, 14,8 analog output channel, the tunnel DA numerical value that controller provides, the 16 way switch amount input states that controller collects, the 8 way switch amount output states that controller provides, by particular order form write tx_interface.v, complete controller and send status information to host computer by asynchronous serial communication interface, and this process of transmitting is moved in circles carry out.In each transmission circulation greatly, this module sends the controller state information of 52 bytes altogether: this module first sends the reception synchronizing information (1 byte) of 0x55 as host computer of a byte, then read the 16 road AI numerical value of 16 × 12bit from RAM_AD module Ram and send (32 byte), then read the 8 road AO numerical value of 8 × 14bit from RAM_AO module Ram and send (16 byte), finally from inputting DI_STATE [15:0] and exporting DO_STATE [7:0] read switch amount IO state and send (3 byte).

Controller information sends control module tx_control.v and adopts Verilog HDL language to programme, and program is divided into 11 states.Main information sends Control on Communication sequential flow process:

(1) in TX_0x55 state, by the time the transmission FIFO of tx_interface.v is not for just writing 1 byte 8'h55 by Write_Req_Sig being put 1 to tx_interface.v time full, send the sync byte 0x55 that host computer receives data---as the first byte that each 52 byte cycle send, and by OPADD signal wire RdAddr1 [3:0] and RdAddr [3:0] clear 0, counter C1 clear 0, enters AD_RAM_HIGH state immediately;

(2) in AD_RAM_HIGH state, because being 0 ~ 15 by the address wire RdAddr1 assignment of RAM_AD module Ram before, therefore at this moment from low 12 the data RdData1 [15:0] that RAM_AD module Ram reads be exactly the AD conversion numerical value of analog quantity RdAddr1 input channel, by the time the transmission FIFO of tx_interface.v is not for just writing RdData1 [15:8] by Write_Req_Sig being put 1 to tx_interface.v time full, send the high byte of the AD conversion numerical value of analog quantity RdAddr1 input channel, enter AD_RAM_LOW state immediately;

(3) in AD_RAM_LOW state, by the time the transmission FIFO of tx_interface.v is not for just writing RdData1 [7:0] by Write_Req_Sig being put 1 to tx_interface.v time full, send the low byte of the AD conversion numerical value of analog quantity RdAddr1 input channel, enter NEXT_RdAddr1 state immediately;

(4) in NEXT_RdAddr1 state, first by Write_Req_Sig in time clear 0 to suspend to the write of tx_interface.v, judge whether current RdAddr1 is 15: if not 15 represent that the AD conversion value of all 16 analog input channels, tunnel is not yet all sent by tx_interface.v, then RdAddr1 is added 1 to read the AD conversion value of next channel number from RAM_AD module Ram, and get back to the transmission that AD_RAM_HIGH state starts the AD conversion value of next channel number; If RdAddr1 is 15, represents that the AD conversion value of all 16 analog input channels, tunnel is all sent by tx_interface.v, at this moment should enter next state---AO_RAM_HIGH state;

(5) in AO_RAM_HIGH state, because being 0 ~ 7 by the address wire RdAddr assignment of RAM_AO module Ram before, therefore at this moment from low 14 the data RdData [15:0] that RAM_AO module Ram reads be exactly the DA numerical value of analog quantity RdAddr output channel, by the time the transmission FIFO of tx_interface.v is not for just writing RdData [15:8] by Write_Req_Sig being put 1 to tx_interface.v time full, send the high byte of the DA numerical value of analog quantity RdAddr output channel, enter AO_RAM_LOW state immediately;

(6) in AO_RAM_LOW state, by the time the transmission FIFO of tx_interface.v is not for just writing RdData [7:0] by Write_Req_Sig being put 1 to tx_interface.v time full, send the low byte of the DA numerical value of analog quantity RdAddr output channel, enter NEXT_RdAddr state immediately;

(7) in NEXT_RdAddr state, first by Write_Req_Sig in time clear 0 to suspend to the write of tx_interface.v, judge whether current RdAddr is 7: if not 7 represent that the DA numerical value of all 8 analog output channels, tunnel is not yet all sent by tx_interface.v, then RdAddr is added 1 to read the DA numerical value of next channel number from RAM_AO module Ram, and get back to the transmission that AO_RAM_HIGH state starts the DA numerical value of next channel number; If RdAddr is 7, represents that the DA numerical value of all 8 analog output channels, tunnel is all sent by tx_interface.v, at this moment should enter next state---DI_STATE_HIGH state;

(8) in DI_STATE_HIGH state, by the time the transmission FIFO of tx_interface.v is not for just writing DI_STATE [15:8] by Write_Req_Sig being put 1 to tx_interface.v time full, send the most-significant byte of 16 way switch amount input states, enter DI_STATE_LOW state immediately;

(9) in DI_STATE_LOW state, by the time the transmission FIFO of tx_interface.v is not for just writing DI_STATE [7:0] by Write_Req_Sig being put 1 to tx_interface.v time full, send the least-significant byte of 16 way switch amount input states, enter DO_STATE state immediately;

(10) in DO_STATE state, by the time the transmission FIFO of tx_interface.v is not for just writing DO_STATE [7:0] by Write_Req_Sig being put 1 to tx_interface.v time full, send 8 way switch amount output states, enter Delay_TX state immediately;

(11) in Delay_TX state, the requirement in cycle can be sent to controller state information according to host computer, carry out the time delay of a period of time, delay time constant Delay_TX, when time delay implementation method is the triggering of each FPGA clock CLK rising edge, counter C1, from increasing 1, gets back to TX_0x55 state to start the transmission circulation of next 52 bytes as C1=Delay_TX.

As shown in figure 16, asynchronous serial communication transmission interface 6, utilizes inner asynchronous serial communication to send FIFO and receives the written information that controller information sends control module 9, on delivery outlet, finally complete the transmission of asynchronous serial communication Frame.Described asynchronous serial communication transmission interface 6 includes, asynchronous serial communication bottom sends driver module 63tx_module.v, asynchronous serial communication upper strata sends control module 62tx_top_control_module.v, asynchronous serial communication sends fifo module 61tx_fifo_module, wherein, described asynchronous serial communication sends fifo module 61 and receives the information that controller information sends control module 9 write; Described asynchronous serial communication upper strata sends control module 62 and sends from described asynchronous serial communication the data to be sent that fifo module 61 reads 1 byte, calls asynchronous serial communication bottom and sends the transmission that driver module 63 completes frame data, move in circles; Described asynchronous serial communication bottom sends driver module 63 and asynchronous serial communication upper strata is sent 8 bit parallel data to be sent that control module 62 sends according to 1 start bit in asynchronous serial communication (' 0')+8 data bit+1 position of rests (' 1'), the sequential of the frame format of no parity check position outputs to delivery outlet TX_Pin_Out by turn, and described delivery outlet TX_Pin_Out is configured to the transmission pin of 1 road RS422 or full duplex RS485 or the transmission pin of 2 road RS232-C.

In the block scheme of the asynchronous serial communication transmission interface tx_interface.bdf shown in Figure 16, the major function that tx_interface.bdf completes is: utilize the asynchronous serial communication of a 1024 × 8bit to send FIFO---tx_fifo_module and other external module interfaces, external module needs to send 1 byte data by asynchronous serial communication, only FIFO_Write_Data [7:0] assignment need be byte data to be sent and Write_Req_Sig be set to high level FPGA clock, this module is just by the tx_fifo_module module of inside, tx_top_control_module.v, the cooperation control of tx_module.v, the final transmission completing frame data on delivery outlet TX_Pin_Out.The degree of depth be 1024 asynchronous serial communication send FIFO can greatly alleviate other external modules send request of data therewith transmission interface externally carry out the speed mismatch problem of asynchronous transmission by specific baud rate.The module that asynchronous serial communication transmission interface tx_interface.bdf uses comprises: asynchronous serial communication bottom sends driver module tx_module.v, asynchronous serial communication upper strata sends control module tx_top_control_module.v, and asynchronous serial communication sends fifo module tx_fifo_module.

As shown in figure 17, asynchronous serial communication bottom sends in driver module tx_module.v state transition graph, the major function that tx_module.v completes is: the TX_Data [7:0] sent by upper layer module tx_top_control_module.v is according to 1 start bit in asynchronous serial communication (' 0')+8 data bit+1 position of rests (' 1'), the sequential of the frame format of no parity check position outputs to TX_Pin_Out by turn, and TX_Pin_Out can be configured to 1 road RS422(full duplex RS485) transmission pin or the transmission pin of 2 road RS232-C.

Asynchronous serial communication bottom sends driver module tx_module.v and adopts Verilog HDL language to programme, and program is divided into 6 states.Main asynchronous serial communication bottom transmission timing control flow is:

(1) in IDLE state, by clear for TX_Done_Sig 0, this module is in idle idle waiting status, at this moment the TX_En_Sig input signal that the upper layer module (tx_top_control_module.v) of calling this module is sent can be detected in real time, if TX_En_Sig=0, just keep IDLE state, as long as TX_En_Sig=1 detected at the rising edge of continuous 2 FPGA clock CLK, enter FRAME_PREPARE state immediately;

(2) in FRAME_PREPARE state, 8 the data TX_Data to be sent [7:0] upper layer module (tx_top_control_module.v) calling this module inputted add 1 start bit (' 0') and 1 position of rest (' 1'), and the frame data forming 10 are deposited in register rData [9:0]; Current transmission position indicator register Index_Bit is initialized as 0, Index_Bit be used to refer to current just the external serial of TX_Pin_Out send pin exporting in rData [9:0] who, complete this process laggard enter TX_Change state;

(3) in TX_Change state, by rData [Index_Bit] position State-output on TX_Pin_Out pin, then Delay_1bit state is entered immediately;

(4) in Delay_1bit state, because having set TX_Pin_Out pin state in TX_Change state, so the baud rate that only need provide according to asynchronous serial communication receiving-transmitting sides in state carries out the time delay of a period of time, delay time constant Delay_BaudRate=(1/ baud rate (bps))/(1/48000000)-2, when time delay implementation method is the triggering of each FPGA clock CLK rising edge, counter C1 from increasing 1, enters NEXT_BIT state as C1=Delay_BaudRate;

(5) in NEXT_BIT state, first by clear for C1 0, judge whether current I ndex_Bit is 9: if not 9 represent that the not yet whole serial of the data rData [9:0] of a frame 10 sends, then Index_Bit is added 1, and get back to the data transmission that TX_Change state starts next bit; If Index_Bit is 9, the data rData [9:0] representing this frame 10 all on TX_Pin_Out pin serial send, this frame sends and completes, and at this moment should enter next state---ACK state;

(6) in ACK state, TX_Done_Sig output signal is set to high level, only namely the TX_Done_Sig signal of 1 FPGA clock can be used as feeding back ACK and informs the upper layer module (tx_top_control_module.v) calling this module: the TX_Data [7:0] that sent by tx_top_control_module.v of this tx_module.v module is according to 1 start bit in asynchronous serial communication (' 0')+8 data bit+1 position of rests (' 1'), and the sequential of the frame format of no parity check position outputs to TX_Pin_Out by turn; So far, this tx_module.v module completes the transmission of an asynchronous serial frame, returns to IDLE state and waits for upper layer module next time calling this tx_module.v module.

This tx_module.v module by IDLE state perform a circle return the IDLE state time used approximate (slightly larger than) baud rate that provides by asynchronous serial communication receiving-transmitting sides sends time of 10 bit data, when using slower baud rate as RS232-C agreement 9600bps, the frame time used that sends is 10 × (1/9600)=1.0416667ms, when use very fast baud rate as RS422(full duplex RS485) agreement 115200bps time, the frame time used that sends is 10 × (1/115200)=86.805556us, a frame transmission cycle of this tx_module.v module approximates this evaluation.

Upper layer module tx_top_control_module.v by need serial to send 1 byte 8 bit data (high-order at front low level rear, need not convert) export to TX_Data [7:0], output TX_En_Sig is put 1 simultaneously, then just wait for until tx_module.v TX_Done_Sig export put 1 after just by clear for TX_En_Sig 0, this represents tx_module.v according to 1 start bit in asynchronous serial communication (' 0')+8 data bit+1 position of rests (' 1'), the sequential of the frame format of no parity check position outputs to TX_Pin_Out by turn, TX_Pin_Out is configured to respective pins and can realizes RS422(full duplex RS485) or the transmission of RS232-C.

As shown in figure 18, asynchronous serial communication upper strata sends in the state transition graph of control module tx_top_control_module.v, the major function that tx_top_control_module.v completes is: from asynchronous serial communication transmission, FIFO---tx_fifo_module module reads the data to be sent of 1 byte, call asynchronous serial communication bottom to send driver module tx_module.v and complete the transmission of frame data (concrete grammar is: export the outgoing data read from tx_fifo_module module to TX_Data [7:0], TX_En_Sig is exported and sets high level until TX_En_Sig output is set low level by tx_module.v complete when feedback input signal TX_Done_Sig is high level again), move in circles.

Asynchronous serial communication upper strata sends control module tx_top_control_module.v and adopts Verilog HDL language to programme, and program is divided into 4 states.The main time control flow of tx_top_control_module.v is:

(1) in IDLE state, by clear for TX_En_Sig 0, this module is in idle idle waiting status, at this moment can detect asynchronous serial communication in real time and send FIFO---and whether tx_fifo_module module is empty, if send FIFO for empty (Empty_Sig=1), waits in this state; If sending FIFO is not empty (Empty_Sig=0), data to be sent is described, at this moment should enters Read_HIGH state;

(2) in Read_HIGH state, will read after FIFO request signal Read_Req_Sig puts 1, to enter Read_LOW state immediately;

(3) in Read_LOW state, FIFO request signal Read_Req_Sig in time clear 0 will be read, and ensure the data to be sent only reading 1 byte from tx_fifo_module module, enter CALL_tx_module state immediately;

(4) in CALL_tx_module state, now effective on the input line of FIFO_Read_Data [7:0] from the 1 byte data to be sent of tx_fifo_module module reading, therefore export FIFO_Read_Data [7:0] to TX_Data [7:0], TX_En_Sig is exported and sets high level to call asynchronous serial communication bottom transmission driver module tx_module.v, wait for until TX_En_Sig output is set low level by tx_module.v complete when feedback input signal TX_Done_Sig is high level again in this state, at this moment the transmission of frame data has been completed, IDLE state should be got back to immediately.

PLL phase-locked loop module 12, inputs with the 48MHz clock of automatic/hand reset circuit unit 5 based on the clock input in the hypervelocity industrial control unit (ICU) of FPGA for receiving, and provides global clock signal for system.

Pid algorithm module PID_CAL_CONTROL.v is used for realizing increment type PID algorithm, and it exports and is formulated as with the relational expression of input:

△u(kT)=u(kT)-u[(k-1)T]

=K _p{e(kT)-e[(k-1)T]}+K _ie(kT)+K _d{e(kT)-2e[(k-1)T]+e[(k-2)T]}。

u(kT)=u[(k-1)T]+△u(kT)。

Wherein, e (kT) represents the deviate in a kth sampling period, K _prepresent the numerical value of proportional action P, K _irepresent the numerical value of integral action I, K _drepresent the numerical value of differential action D, u (kT) represents the controlled quentity controlled variable output that a kth sampling period calculates.

PID_CAL_CONTROL.v read in DA_top_control.v export pid parameter and nearest 3 deviate e (k), e (k-1), e (k-2), calculate controlled quentity controlled variable increment delta_u export to DA_top_control.v read.The LPM_MULT that MegaWizard generates under Quartus II is used in multiplying wherein.

Except each Verilog hdl file functional module of above-mentioned detailed introduction, some other functional module has also been used in whole engineering, such as use the PLL phase-locked loop module that MegaWizard generates under Quartus II, LPM_MULT multiplier, LPM_DIVIDE divider, ROM sine values storer, FIFO asynchronous serial communication sending/receiving impact damper, Verilog HDL language is adopted to carry out each dual port RAM module following of programming for another example: AD conversion value module Ram(16 × 16bit) RAM_AD.v and RAM_AD2.v, analog quantity AI set-point module Ram(8 × 16bit) RAM_AD_SP.v, analog quantity DA real output value module Ram(8 × 16bit) RAM_AO.v, waveform parameter module Ram(32 × 16bit) RAM_BOXING_PARAMETER.v, the manual setting value module Ram(8 × 16bit of analog output DA) RAM_DA_HAND.v, analog quantity closed loop PID control parameter module Ram(48 × 16bit) RAM_PID_PARAMETER.v.When writing the code of these twoports Ram module, add particular statement can automatically the memory block M9K in these module Ram FPGA be generated when compiling to make Quartus II, and the logical block LE of FPGA can not be taken, this process saves the logical resource of FPGA preciousness greatly, improves the utilization factor of FPGA internal storage block simultaneously.

Claims (8)

1., based on a FPGA hypervelocity industrial control system of Verilog HDL, it is characterized in that, comprising:

DA top level control module (1), for in a control cycle Ts, receiving control module (8) the analog quantity DA output mode that exports according to controller communications command word selects position AUTO_HAND_DA [31:0] data to carry out the calculating of DA numerical value by a kind of mode in following five kinds of modes, and call the voltage output refreshing that DA bottom layer driving module (5) completes 8 road analog outputs, and stored in analog quantity DA real output value module Ram (16), five kinds of described modes are:

First kind of way, manually arranges DA value according to the numerical value read from the manual setting value module Ram (18) of analog output DA and exports;

The second way, exports square wave automatically according to the cycle relative value read from waveform parameter module Ram (20), peak value, valley;

The third mode, exports triangular wave automatically according to the cycle relative value read from waveform parameter module Ram (20), peak value, valley;

4th kind of mode, according to the cycle relative value, peak value, the valley that read from waveform parameter module Ram (20), and according to the automatic sine wave output of numerical value read from sine values Rom storer (13);

5th kind of mode, according to the closed loop set-point of the analog input AI corresponding with each road AO passage of 8 road analog outputs read from analog quantity AI set-point module Ram (19), with the corresponding closed loop PID control parameter read from analog quantity closed loop PID control parameter module Ram (17), call the pid algorithm module (11) for realizing increment type PID algorithm, the PID carrying out single closed loop or two close cycles regulates automatically, calculates DA numerical value and exports;

AD top level control module (4), the poll AD sample conversion of whole 16 road analog input signals is completed for calling an AD bottom layer driving module (2) and the 2nd AD bottom layer driving module (3), and by transformation result stored in the first AD conversion value module Ram (14) and the second AD conversion value module Ram (15), provide the control cycle synchronizing signal Ts of whole system to DA top level control module (1);

One AD bottom layer driving module (2), for receiving the 16 bit parallel control words that AD top level control module (4) sends, convert SPI serial line interface sequential to, write is based on 12 the 8 passage A/D converter circuit of the first in the hypervelocity industrial control unit (ICU) of FPGA, control this circuit and carry out AD conversion, and the data parallel of transformation result is outputted to AD top level control module (4);

2nd AD bottom layer driving module (3), for receiving the 16 bit parallel control words that AD top level control module (4) sends, convert SPI serial line interface sequential to, write is based on 12 the 8 passage A/D converter circuit of second in the hypervelocity industrial control unit (ICU) of FPGA, control this circuit and carry out AD conversion, and the data parallel of transformation result is outputted to AD top level control module (4);

DA bottom layer driving module (5), converts SPI serial line interface sequential to for 32 bit parallel control words DA top level control module (1) sent, and writes based on 14 8 passage D/A converter circuit in the hypervelocity industrial control unit (ICU) of FPGA;

Asynchronous serial communication receiving interface (7), for receiving the signal inputted based on the communication numeral buffer circuit 111 in the hypervelocity industrial control unit (ICU) of FPGA, and the asynchronous serial communication of write inside receives in fifo module, receive control module (8) for controller communications command word and read;

Controller communications command word receives control module (8), for from asynchronous serial communication receiving interface (7) sense data, all School Affairs calculating is carried out after often reading 10 byte command words of host computer transmission, controller communications command word according to setting receives resolution table, separated out the implication of host computer command word by the first character joint received and function code numerical solution, thus carry out corresponding command analysis and optimum configurations;

Output switch parameter DO Logic control module (10), for reading in 16 way switch amount input state signals, and exports 8 way switch amount output status signals according to the pattern that controller communications command word reception control module (8) sets;

Controller information sends control module (9), respectively: the numerical value reading 16 way switch amount input states and 8 way switch amount output states from output switch parameter DO Logic control module (10), 12,16 analog input channel, tunnel AD conversion value is read from the first AD conversion value module Ram (14), 14,8 analog output channel, tunnel DA numerical value is read from analog quantity DA real output value module Ram (16), and by the numerical value that reads order format write asynchronous serial communication transmission interface (6) by setting, and this process of transmitting is moved in circles carry out;

Asynchronous serial communication transmission interface (6), utilize inner asynchronous serial communication to send fifo module and receive the written information that controller information sends control module (9), on delivery outlet, finally complete the transmission of asynchronous serial communication Frame;

PLL phase-locked loop module (12), inputs with the 48MHz clock of automatic/hand reset circuit unit based on the clock input in the hypervelocity industrial control unit (ICU) of FPGA for receiving, and provides global clock signal for system.

2. a kind of FPGA hypervelocity industrial control system based on Verilog HDL according to claim 1, it is characterized in that, a described AD bottom layer driving module (2) is identical with the 2nd AD bottom layer driving module (3) structure, wherein, a described AD bottom layer driving module (2) is in the read-write cycle 4.770833us of an A/D converter, SPI serial line interface sequential is converted to by receiving the parallel control word that AD top level control module (4) sends, write is based on 12 the 8 passage A/D converter circuit of the first in the hypervelocity industrial control unit (ICU) of FPGA, and 16 data parallels comprising a upper read-write cycle AD conversion result read from first 12 8 passage A/D converter circuit serial are outputted to AD top level control module (4), the 2nd described AD bottom layer driving module (3) is in the read-write cycle 4.770833us of an A/D converter, for converting SPI serial line interface sequential to by receiving the parallel control word that AD top level control module (4) sends, 16 data parallels comprising a upper read-write cycle AD conversion result read from second 12 8 passage A/D converter circuit serial based on 12 the 8 passage A/D converter circuit of second in the hypervelocity industrial control unit (ICU) of FPGA, and are outputted to AD top level control module (4) by write.

3. a kind of FPGA hypervelocity industrial control system based on Verilog HDL according to claim 1, it is characterized in that, described AD top level control module (4), for in each control cycle Ts=0.2896667ms, call the poll AD sample conversion that an AD bottom layer driving module (2) and the 2nd AD bottom layer driving module (3) complete whole 16 road analog input signals, complete based on after the synchronous AD conversion of continuous 7 times an of input channel in 12 the 8 passage A/D converter circuit of the first in the hypervelocity industrial control unit (ICU) of FPGA and second 12 8 passage A/D converter circuit at every turn, after 7 subsynchronous AD conversion results of first 12 8 passage A/D converter circuit and second 12 8 passage A/D converter circuit rear is carried out simple selected and sorted 6 times, again by the middle AD conversion value of first 12 8 passage A/D converter circuit and second 12 8 passage A/D converter circuit, stored in the first AD conversion value module Ram (14) and the second AD conversion value module Ram (15), the control cycle synchronizing signal Ts of whole system is provided to DA top level control module (1).

4. a kind of FPGA hypervelocity industrial control system based on Verilog HDL according to claim 1, it is characterized in that, described asynchronous serial communication transmission interface (6) includes, asynchronous serial communication bottom sends driver module (63), asynchronous serial communication upper strata sends control module (62), asynchronous serial communication sends fifo module (61), wherein, described asynchronous serial communication sends the information that fifo module (61) reception controller information transmission control module (9) writes; Described asynchronous serial communication upper strata sends control module (62) and sends from described asynchronous serial communication the data to be sent that fifo module (61) reads 1 byte, call asynchronous serial communication bottom and send the transmission that driver module (63) completes frame data, and move in circles; Described asynchronous serial communication bottom sends driver module (63) and the 8 bit parallel data to be sent that asynchronous serial communication upper strata transmission control module (62) is sent is outputted to delivery outlet by turn according to the sequential of the frame format of 1 start bit+8 data bit+1 position of rest, no parity check position in asynchronous serial communication, and described delivery outlet is configured to the transmission pin of 1 road RS422 or full duplex RS485 or the transmission pin of 2 road RS232-C.

5. a kind of FPGA hypervelocity industrial control system based on Verilog HDL according to claim 1, it is characterized in that, described asynchronous serial communication receiving interface (7) includes, asynchronous serial communication bottom receives driver module (71), asynchronous serial communication upper strata receives control module (72), asynchronous serial communication receives fifo module (73), wherein, described asynchronous serial communication upper strata receives control module (72) and calls the reception that asynchronous serial communication bottom reception driver module (71) completes frame data, 8 bit parallel data just received that fifo module (73) writes 1 byte are received to asynchronous serial communication, move in circles, described asynchronous serial communication bottom receives driver module (71) under the control on asynchronous serial communication upper strata reception control module (72), become 8 bit parallel data to receive control module (72) for asynchronous serial communication upper strata to input port state according to the timing conversion of the frame format of 1 start bit+8 data bit+1 position of rest, no parity check position in asynchronous serial communication to read, described input port is configured to the reception pin of 1 road RS422 or full duplex RS485 or the reception pin of 2 road RS232-C, the information that described asynchronous serial communication reception fifo module (73) reception asynchronous serial communication upper strata reception control module (72) writes receives control module (8) reading for controller communications command word.

6. a kind of FPGA hypervelocity industrial control system based on Verilog HDL according to claim 1, is characterized in that, the described controller communications command word controller communications command word received in control module (8) receives resolution table setting:

When first character joint and function code numerical value are 0, the numerical value in resolve command word, and carry out a way switch amount output DO hand/Lookup protocol;

When first character joint and function code numerical value are 1, the numerical value in resolve command word, and the DA value of carrying out a road analog output AO is manually arranged;

When first character joint and function code numerical value are 2, the numerical value in resolve command word, and the setting carrying out that a road analog output AO generates square wave automatically;

When first character joint and function code numerical value are 3, the numerical value in resolve command word, and the setting carrying out that a road analog output AO generates triangular wave automatically;

When first character joint and function code numerical value are 4, the numerical value in resolve command word, and the setting carrying out that a road analog output AO generates sine wave automatically;

When first character joint and function code numerical value are 5, the numerical value in resolve command word, and carry out a road analog output AO cut automatic PID regulate enable;

When first character joint and function code numerical value are 6, the numerical value in resolve command word, and the closed loop set-point carrying out a road analog input AI is arranged;

When first character joint and function code numerical value are 7, the numerical value in resolve command word, and the closed loop PID control optimum configurations carrying out a road analog input AI.

7. a kind of FPGA hypervelocity industrial control system based on Verilog HDL according to claim 6, it is characterized in that, when described function code numerical value is 0, described controller communications command word receives control module (8) and refreshes the data exporting to output switch parameter DO Logic control module (10) according to received command word; When described function code numerical value is 2,3 and 4, described controller communications command word receives control module (8), according to received command word, waveform parameter is write waveform parameter module Ram (20), and refreshes analog quantity DA output mode selection position AUTO_HAND_DA [31:0] data exporting to DA top level control module (1); When described function code numerical value is 1, described controller communications command word receives control module (8), according to received command word, the DA of analog output AO is manually worth the manual setting value module Ram (18) of write analog output DA, and refreshes analog quantity DA output mode selection position AUTO_HAND_DA [31:0] data exporting to DA top level control module (1); When described function code numerical value is 5, described controller communications command word receives control module (8) and refreshes analog quantity DA output mode selection position AUTO_HAND_DA [31:0] data exporting to DA top level control module (1) according to received command word; When described function code numerical value is 6, described controller communications command word receives control module (8) according to received command word by the closed loop set-point of road analog input write analog quantity AI set-point module Ram (19); When described function code numerical value is 7, described controller communications command word receives control module (8) according to closed loop PID control parameter read-in analog quantity closed loop PID control parameter module Ram (17) of received command word by a road analog input.

8. a kind of FPGA hypervelocity industrial control system based on Verilog HDL according to claim 1, it is characterized in that, described controller information sends control module (9) to host computer circulation transmit control device status information, in each transmission circulation, this controller information sends the controller state information that control module (9) sends 52 bytes altogether: the reception synchronizing information of 0x55 as host computer first sending a byte, then from first AD conversion value module Ram (14) read 16 × 12bit totally 32 bytes 16 road AI numerical value and send, then from analog quantity DA real output value module Ram (16) read 8 × 14bit totally 16 bytes 8 road AO numerical value and send, the numerical value of 16 way switch amount input states and 8 way switch amount output states totally 3 bytes is finally read from output switch parameter DO Logic control module (10).