CN106100635A - The emulation mode of phase-locked loop clock shake and system - Google Patents
The emulation mode of phase-locked loop clock shake and system Download PDFInfo
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- CN106100635A CN106100635A CN201610335079.2A CN201610335079A CN106100635A CN 106100635 A CN106100635 A CN 106100635A CN 201610335079 A CN201610335079 A CN 201610335079A CN 106100635 A CN106100635 A CN 106100635A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Abstract
The present invention provides the emulation mode and system that a kind of phase-locked loop clock shakes, it is applicable to noise information corresponding for modules in phaselocked loop is embedded in voltage domain behavioral scaling model, to obtain the clock jitter signal of phaselocked loop, the method includes: step 1, use the modules in this steady-state analysis of week and periodic noise analyzing and processing phaselocked loop, obtain the clock jitter signal of each described module；Step 2, uses Verilog A language to build the behavioral scaling model of phaselocked loop, emulates the clock jitter signal embedding each described module；Step 3, when the phase lock loop locks of behavioral scaling model, records described phaselocked loop output waveform Cycle Length information in Preset Time；Step 4, calculates meansigma methods and the standard deviation of Cycle Length information, obtains the clock jitter signal of behavioral scaling model phaselocked loop and the power spectral density of phase place.The present invention improves the efficiency of the emulation of phase-locked loop clock shake.
Description
Technical field
The present invention relates to simulation technical field, particularly relate to emulation mode and the system of the shake of a kind of phase-locked loop clock,
When being applied to design of integrated circuit, the noiseproof feature of phase-locked loop circuit can be entered by the simulation stage at circuit theory diagrams
Row prediction.
Background technology
When cycle of phase-locked loop exists stable state, utilize the noiseproof feature of emulation tool SpectreRF prediction phaselocked loop.Noise
The process analyzed includes: static work when utilizing the PSS (week this steady-state analysis) of emulation tool SpectreRF to obtain stable state
Point；When phase-locked loop does not exists stable state, carry out the analysis result that PSS obtains and show and cannot restrain, be i.e. clock and data recovery electricity
The phaselocked loop of the phase discriminator in road, fractional-type phaselocked loop and any employing dead band all can not use this emulation；When phaselocked loop ring
Road stable state is, emulation tool SpectreRF can be used in theory to carry out noise analysis.On the one hand, the noise analysis on basis is carried out
Time, at least need to carry out PSS and Pnoise (periodic noise analysis), and PSS analyzes after there is convergence and can carry out
PNoise analyzes, and i.e. needs etc. one section " treating convergence time " to appear, and needs during this period of time to arrange long enough, just can ensure that
PSS analyzes convergence state, and this " treats convergence time " and be roughly equivalent to the locking time of phaselocked loop.On the other hand, carry out
When PNoise analyzes, need to observe the signal period that output is abundant, and each cycle also needs many time points accurately to resolve.
So, if the frequency dividing ratio of phaselocked loop is excessive, then the PSS of whole cycle of phase-locked loop analyzes plus PNoise needs emulation a large amount of
Time point, the longest, therefore, directly use emulation tool SpectreRF emulation phaselocked loop noise unrealistic.
The most common phaselocked loop behavioral scaling model is frequency-domain model.First, SpectreRF emulation is utilized to obtain each mould
The phase noise of block, is embedded into phase noise the individual module that behavioral scaling model is corresponding, then is connected by the model of all modules
Become complete cycle of phase-locked loop, emulate this loop and obtain overall noise situation.Wherein, the behavioral scaling model of each module by
Verilog-A language describes.Verilog-A is the hardware description language for describing analog circuit, has stronger readability.
Big to whole system, little to the analog switch being made up of single transistor or current source, all can use Verilog-A to be described.
The behavioral scaling model that it is set up can be mapped to netlist as the emulation of Spice circuit compiles.As long as it is to say, can be to mould
Intending circuit realiration precisely enough behavior modeling, the model of Verilog-A just can accurately reflect the performance of circuit；And it is smart with emulation
Degree requires that higher Spice emulates difference, and the simulation velocity of Verilog-A model much faster, can within a short period of time
Completion system checking and parameter determination.
Wherein, the main contents of Verilog-A modeling include the setting of model name, port and parameter, circuit function
Description.Verilog-A for phaselocked loop models the most common, and difficulty is the highest.Verilog-A set up model and
The schematic diagram of analog circuit transistor level is the same, can be packaged into the symbol called for upper strata circuit.With charge pump type phaselocked loop
As a example by tri-state phase frequency detector, the emphasis describing its function is when rising (or decline) edge of two input signals occurs, defeated
Go out switching signal and become high level；When two input signals are high level simultaneously, circuit resets after certain delay.Its
In, time delay, length just could be arranged to adjustable parameter, in order to simulate the impact of dead time effect.And the function of voltage controlled oscillator
Description then concentrates on output frequency and changes with the change controlling voltage.Gain KVCO and mid frequency fc is all outside adjustable
Parameter.
Therefore, a kind of method that noise information that can emulate phaselocked loop can improve again its simulation velocity is needed badly.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide the imitative of a kind of phase-locked loop clock shake
True method and system, the slowest for solving clock jitter based on the frequency domain behavioral scaling model simulation velocity of phaselocked loop in prior art
Problem.
For achieving the above object and other relevant purposes, the present invention provides the emulation mode that a kind of phase-locked loop clock is shaken,
Be applicable to noise information corresponding for modules in phaselocked loop is embedded in voltage domain behavioral scaling model, with obtain phaselocked loop time
Clock dither signal, the method includes:
Step 1, uses the modules in this steady-state analysis of week and periodic noise analyzing and processing phaselocked loop, obtains each
The clock jitter signal of described module；
Step 2, use Verilog-A language build phaselocked loop behavioral scaling model, to embed each described module time
Clock dither signal emulates；
Step 3, when the phase lock loop locks of behavioral scaling model, records described phaselocked loop output waveform in Preset Time
Cycle Length information；
Step 4, calculates meansigma methods and the standard deviation of Cycle Length information, obtains the clock jitter of behavioral scaling model phaselocked loop
Signal and the power spectral density of phase place.
Another object of the present invention is to the analogue system providing a kind of phase-locked loop clock to shake, it is adaptable to by phaselocked loop
The noise information that modules is corresponding is embedded in voltage domain behavioral scaling model, and to obtain the clock jitter signal of phaselocked loop, this is
System includes:
Processing module, is suitable for use with the modules in this steady-state analysis of week and periodic noise analyzing and processing phaselocked loop,
Obtain the clock jitter signal of each described module；
Model emulation module, is adapted in use to Verilog-A language to build the behavioral scaling model of phaselocked loop, to embedding each institute
The clock jitter signal stating module emulates；
Logging modle, is suitable to when the phase lock loop locks of behavioral scaling model, records described phaselocked loop output waveform and is presetting
Cycle Length information in time；
Computing module, is suitable to calculate meansigma methods and the standard deviation of Cycle Length information, obtains behavioral scaling model phaselocked loop
Clock jitter signal and the power spectral density of phase place.
As it has been described above, the emulation mode of the phase-locked loop clock shake of the present invention and system, have the advantages that
The present invention sets up the behavioral scaling model of voltage domain by Verilog-A language, by phaselocked loop modules time
Clock dither signal embeds behavior level model, and when in behavioral scaling model, phaselocked loop is in locking, a large amount of cycles obtaining output are long
Degree information, by calculating meansigma methods and the standard deviation of Cycle Length information, obtains the clock jitter letter of behavioral scaling model phaselocked loop
Number with the power spectral density of phase place.When the emulation of voltage domain, it is not necessary to the least time step resolves, and greatly reduces
Simulation time；Meanwhile, use Verilog-A language to set up the behavioral scaling model of voltage domain, can exchange with schematic and use,
Be conducive to improving design efficiency；When the phase-locked loop clock shaking way of emulation and result are used for innovative design, can quickly compare
The quality of different phase-locked loop structures performances.
Accompanying drawing explanation
Fig. 1 is shown as the flow chart of the emulation mode of phase-locked loop clock of the present invention shake；
Fig. 2 is shown as voltage controlled oscillator and the phase frequency detector using Verilog-A language to describe；
Fig. 3 is shown as voltage controlled oscillator and the symbol of phase frequency detector behavioral scaling model using Verilog-A language to describe
Number display；
Fig. 4 is shown as that voltage controlled oscillator carries out PSS and PNOISE and analyzes the phase noise curve obtained；
Fig. 5 is illustrated by the power spectral density plot of the phase noise that this method obtains；
Fig. 6-1,6-2 are illustrated by the power spectral density plot of the phase noise of two kinds of phaselocked loops that this method obtains；
Fig. 7 is shown as the structure chart of the analogue system of phase-locked loop clock of the present invention shake.
Element numbers illustrates:
1 processing module
2 model emulation modules
3 logging modles
4 computing modules
5 display modules
S1～S5 step 1 is to step 5
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by the most different concrete realities
The mode of executing is carried out or applies, the every details in this specification can also based on different viewpoints and application, without departing from
Various modification or change is carried out under the spirit of the present invention.It should be noted that, in the case of not conflicting, following example and enforcement
Feature in example can be mutually combined.
It should be noted that the diagram provided in following example illustrates the basic structure of the present invention the most in a schematic way
Think, the most graphic in component count, shape and size time only display with relevant assembly in the present invention rather than is implemented according to reality
Drawing, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is also
It is likely more complexity.
Described phaselocked loop at least includes: phase discriminator (Phase Detector, PD): compare input reference signal with by voltage-controlled
The phase contrast of the output signal that agitator generates, exports this phase contrast to loop filter.
Loop filter (Loop Filter): usually low pass filter, the HFS in filter phase difference,
Retain direct current component signal to send to voltage controlled oscillator.
Voltage controlled oscillator (Voltage Controlled Oscillator, VOC): produce one according to direct current component signal
Individual oscillator signal.
Technology path according to phaselocked loop divides, and mainly includes following four classes phaselocked loop:
Analog phase-locked look (Analog or Linear PLL, LPLL): all use Analogical Circuit Technique to realize.
Digital phase-locked loop (Digital PLL, DPLL): phase discriminator uses digital circuit technique to realize, and remainder uses
Analogical Circuit Technique realizes.
All-digital phase-locked loop (All Digital PLL, ADPLL): all use digital circuit technique to realize.
Software phase-lock loop (Software PLL, SPLL): all functional modules use software to realize, generally runs with in real time
(such as single-chip microcomputer, DSP, FPGA etc.) in control system.
The described phaselocked loop of the above-mentioned type all can use this method, now enumerates emphatically the electric charge pump in digital phase-locked loop phase-locked
Ring, wherein, charge pump phase lock loop is compared with analog phase-locked look, and unique difference is that phase frequency detector is collectively referred to as with charge pump circuit (CP)
For electric charge pump phase demodulation, described charge pump circuit carries out discharge and recharge to loop filter.
As it is shown in figure 1, the emulation mode of a kind of phase-locked loop clock shake, it is adaptable to by corresponding for modules in phaselocked loop
Noise information is embedded in voltage domain behavioral scaling model, and to obtain the clock jitter signal of phaselocked loop, the method includes:
Step 1, uses the modules in this steady-state analysis of week and periodic noise analyzing and processing phaselocked loop, obtains each
The clock jitter signal of described module；
Wherein, in using this steady-state analysis of week and the periodic noise analyzing and processing phaselocked loop of emulation tool SpectreRF
Each module, wherein, time when using this steady-state analysis of week to process certain module until it enters stable state, according to its static work
Make point and determine whether convergence；When there is the module of quiescent point convergence, the module of quiescent point convergence is carried out the cycle
Property noise analysis, obtains phase noise signal；
Described phase noise signal is integrated, obtains the clock jitter signal of correspondence.
Specifically, in the simulation architecture of charge pump phase lock loop, when needing to obtain the clock jitter of voltage controlled oscillator output
Situation, the simulation architecture built at least includes the load circuit of voltage controlled oscillator and the input circuit of frequency divider, according to above-mentioned side
Formula, correspondence obtains phase noise of voltage controlled oscillator curve, is integrated phase noise curve, obtains the cycle on a certain frequency band
Jitter value.
When for phase frequency detector, charge pump circuit and divider circuit, the purpose of emulation is to obtain each of which to exist
Edge is to the clock jitter at edge, because these modules belong to edging trigger, sees edge to limit according to the mode of step 1
The clock jitter value on edge.When loop filter uses passive device, emulate the module called from technology library and comprised its noise
Information (phase noise curve), it is not necessary to carry out extra emulation.
Step 2, use Verilog-A language build phaselocked loop behavioral scaling model, to embed each described module time
Clock dither signal emulates；
As in figure 2 it is shown, the voltage controlled oscillator described for use Verilog-A language and phase frequency detector, by using
Phaselocked loop behavioral scaling model based on voltage domain set up in Verilog-A language, by phase frequency detector, electric charge pump electricity in phaselocked loop
Road, loop filter, clock jitter information that voltage controlled oscillator is corresponding with divider circuit have fully embedded into behavior level model,
By whole phaselocked loop simulation architecture is emulated, Transient in emulation tool SpectreRF is used to analyze whole phase-locked
Ring, obtains artificial intelligence.
Wherein, describe the modules of phaselocked loop by Verilog-A language and build the behavioral scaling model of voltage domain, can be with
Schematic exchanges use, is conducive to improving design efficiency.Such as, as it is shown on figure 3, be by Fig. 2 by Verilog-A language
Described in the corresponding module circuit structure that changes into of voltage controlled oscillator and phase frequency detector.
Wherein, as shown in Figure 4, carry out PSS and PNOISE for voltage controlled oscillator and analyze the phase noise curve obtained, horizontal seat
Mark represents relative frequency, and vertical coordinate represents phase noise, i.e. can get voltage-controlled voltage controlled oscillator by which without modeling and imitates
The phase noise curve of true time, has saved simulation time.
Step 3, when the phase lock loop locks of behavioral scaling model, records described phaselocked loop output waveform in Preset Time
Cycle Length information；
When the phase lock loop locks of the behavioral scaling model constituted, the reference clock of its phase frequency detector rises with local oscillator clock
The time delay on edge, this time delay is phase error；When this phaselocked loop model is in the lock state, this phase error i.e. phaselocked loop
Stable state difference parameter；It addition, the output waveform of the phaselocked loop in record behavioral scaling model, Preset Time need at least meet at this
Time period can export multiple complete Cycle Length information.
The mode of the detection locking of charge pump phase lock loop includes simulating lock-in detection and digital phase-locking regular inspection surveys two kinds of methods.Its
In, analogue detection circuitry uses the phase error through phase frequency detector PFD output, produces pulse signal and fills external capacitive
Electricity and electric discharge, need the longer time to export to reach stable level, to indicate current phaselocked loop state to be locked out or losing lock.
Number lock detection method has the advantages such as accuracy height, programmability and circuit design are easily achieved and is widely used.Mesh
Before, number lock detection is typically employed in phase frequency detector PFD circuit the reference clock detected after frequency dividing and inputs and same
The phase error of the local oscillator feedback signal after sample is divided realizes, when phase error exceedes certain lock-in detection window, and lock
Phase loop circuit just reports losing lock indication signal.
Step 4, calculates meansigma methods and the standard deviation of Cycle Length information, obtains the clock jitter of behavioral scaling model phaselocked loop
Signal and the power spectral density of phase place.
Wherein, use the mean function in Matlab to process described Cycle Length information respectively with std function, obtain the cycle
Meansigma methods and standard deviation, i.e. standard deviation that length information is corresponding are the root-mean-square value that cycle clock shakes (period jitter)
(RMS value)；And the cumsum function that is respectively adopted in Matlab and psd function long processing period degree information successively,
To the power spectral density of phase place, the most first use cumsum function to obtain the phase noise curve in Cycle Length information, then use
Psd function calculates the power spectral density of this phase noise curve.
Specifically, as it is shown in figure 5, be the power spectral density plot of the phase noise obtained by this method；The horizontal stroke of this figure
Coordinate representation frequency, vertical coordinate represents decibel every hertz, period (cycle)=1e-009s, Frequency (frequency)=1e+
009HZ, Jitter (shake)=2.09e-012S, max dT=1.2%, periods (periodicity)=194921, Nifft are (fast
Speed Fourier's computing)=32768, Resolution Bandwidth (resolution bandwidth)=45776HZ (47dB), to whole electricity
The power spectral density plot of the phase noise of lotus pump phaselocked loop simulation architecture.
As shown in Fig. 6-1,6-2, the power spectrum of the phase noise of the two kinds of phaselocked loops respectively obtained by this method
Write music line.
Wherein, the respectively power spectral density plot of the phase noise of electric charge pump, Sampling Phase-Locked, the abscissa table of this figure
Show that frequency, vertical coordinate represent decibel every hertz.Charge pump phase lock loop: period (cycle)=1e-009s, Frequency is (frequently
Rate)=1e+009HZ, Jitter (shake)=3.38e-013S, max dT=0.19%, periods (periodicity)=92273,
Nifft (fast Fourier computing)=32768, Resolution Bandwidth (resolution bandwidth)=45776HZ (47dB)
Sampling Phase-Locked: period (cycle)=1e-009s, Frequency (frequency)=1e+009HZ, Jitter (trembles
Dynamic)=1.6e-013S, max dT=0.071%, periods (periodicity)=99990, Nifft (fast Fourier computing)=
32768, Resolution Bandwidth (resolution bandwidth)=45776HZ (47dB) is from the shake journey of power spectral density plot
Degree, the simulation architecture of Sampling Phase-Locked is more suitable for this emulation mode.
As it is shown in fig. 7, the structure chart of the analogue system for phase-locked loop clock of the present invention shake, it is adaptable to by each in phaselocked loop
Noise information corresponding to individual module is embedded in voltage domain behavioral scaling model, to obtain the clock jitter signal of phaselocked loop, this system
Including:
Processing module 1, is suitable for use with the modules in this steady-state analysis of week and periodic noise analyzing and processing phaselocked loop,
Obtain the clock jitter signal of each described module；
Model emulation module 2, is adapted in use to Verilog-A language to build the behavioral scaling model of phaselocked loop, each to embedding
The clock jitter signal of described module emulates；
Logging modle 3, is suitable to when the phase lock loop locks of behavioral scaling model, records described phaselocked loop output waveform and is presetting
Cycle Length information in time；
Computing module 4, is suitable to calculate meansigma methods and the standard deviation of Cycle Length information, obtains behavioral scaling model phaselocked loop
Clock jitter signal and the power spectral density of phase place.
Specifically, the analogue system of phase-locked loop clock shake includes display module 5, is suitable to the behavioral scaling model lock that will calculate
The clock jitter signal of phase ring shows with the power spectral density of phase place.
In sum, the present invention sets up the behavioral scaling model of voltage domain by Verilog-A language, by phaselocked loop each
The clock jitter signal of module embeds behavior level model, when phaselocked loop is in locking in behavioral scaling model, obtains the big of output
Amount Cycle Length information, by calculating the meansigma methods of Cycle Length information and standard deviation, obtain behavioral scaling model phaselocked loop time
Clock dither signal and the power spectral density of phase place.When the emulation of voltage domain, it is not necessary to the least time step resolves, greatly
Decrease greatly simulation time；Meanwhile, Verilog-A language is used to set up the behavioral scaling model of voltage domain, can be mutual with schematic
Change use, be conducive to improving design efficiency；When the phase-locked loop clock shaking way of emulation and result are used for innovative design, can be fast
The quality of speed ratio more different phase-locked loop structures performance.So, the present invention effectively overcomes various shortcoming of the prior art and has
High industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any ripe
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage knowing this technology.Cause
This, have usually intellectual such as complete with institute under technological thought without departing from disclosed spirit in art
All equivalences become are modified or change, and must be contained by the claim of the present invention.
Claims (6)
1. the emulation mode of a phase-locked loop clock shake, it is characterised in that be applicable to corresponding for modules in phaselocked loop
Noise information is embedded in voltage domain behavioral scaling model, and to obtain the clock jitter signal of phaselocked loop, the method includes:
Step 1, uses the modules in this steady-state analysis of week and periodic noise analyzing and processing phaselocked loop, obtains each described
The clock jitter signal of module；
Step 2, uses Verilog-A language to build the behavioral scaling model of phaselocked loop, trembles the clock embedding each described module
Dynamic signal emulates；
Step 3, when the phase lock loop locks of behavioral scaling model, records the described phaselocked loop output waveform cycle in Preset Time
Length information；
Step 4, calculates meansigma methods and the standard deviation of Cycle Length information, obtains the clock jitter signal of behavioral scaling model phaselocked loop
Power spectral density with phase place.
The emulation mode of phase-locked loop clock the most according to claim 1 shake, it is characterised in that described step 1, uses week
Each module in this steady-state analysis and periodic noise analyzing and processing phaselocked loop, obtains the clock jitter letter of each described module
Number, including:
This steady-state analysis of week and the periodic noise that use emulation tool SpectreRF analyze and process each mould in phaselocked loop
Block, wherein, time when using this steady-state analysis of week to process certain module until it enters stable state, judges according to its quiescent point
Whether restrain；
When there is the module of quiescent point convergence, the module restraining this quiescent point carries out periodic noise analysis,
Obtain phase noise signal；
Described phase noise signal is integrated, obtains the clock jitter signal of correspondence.
The emulation mode of phase-locked loop clock the most according to claim 1 shake, it is characterised in that described step 2, uses
Verilog-A language builds the behavioral scaling model of phaselocked loop, emulates the clock jitter signal embedding each described module；
Including:
Each module in using Verilog-A language to describe phaselocked loop, builds behavioral scaling model based on voltage domain；
The clock jitter signal of each described module is embedded in the behavioral scaling model of voltage domain, with emulation tool SpectreRF
Middle Transient analyzes whole phaselocked loop and obtains artificial intelligence.
The emulation mode of phase-locked loop clock the most according to claim 1 shake, it is characterised in that described step 4, calculates week
The meansigma methods of phase length information and standard deviation, obtain the clock jitter signal of behavioral scaling model phaselocked loop and the power spectrum of phase place
Degree, including:
Use the mean function in Matlab to process described Cycle Length information respectively with std function, obtain Cycle Length information
Corresponding meansigma methods and standard deviation；And the cumsum function that is respectively adopted in Matlab and psd function long processing period successively
Degree information, obtains the power spectral density of phase place.
5. the analogue system of a phase-locked loop clock shake, it is characterised in that be applicable to corresponding for modules in phaselocked loop
Noise information is embedded in voltage domain behavioral scaling model, and to obtain the clock jitter signal of phaselocked loop, this system includes:
Processing module, is suitable for use with the modules in this steady-state analysis of week and periodic noise analyzing and processing phaselocked loop, obtains
The clock jitter signal of each described module；
Model emulation module, is adapted in use to Verilog-A language to build the behavioral scaling model of phaselocked loop, to embedding each described mould
The clock jitter signal of block emulates；
Logging modle, is suitable to when the phase lock loop locks of behavioral scaling model, records described phaselocked loop output waveform at Preset Time
Interior Cycle Length information；
Computing module, is suitable to calculate meansigma methods and the standard deviation of Cycle Length information, obtains the clock of behavioral scaling model phaselocked loop
Dither signal and the power spectral density of phase place.
The analogue system of phase-locked loop clock the most according to claim 5 shake, it is characterised in that also include display module,
Be suitable to show the clock jitter signal of the behavioral scaling model phaselocked loop of calculating with the power spectral density of phase place.
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| CN106897506A (en) * | 2017-02-09 | 2017-06-27 | 中国科学院微电子研究所 | The Forecasting Methodology of output signal dither cycle in Design of PLL |
| CN106953635A (en) * | 2017-02-21 | 2017-07-14 | 江汉大学 | A kind of frequency source modeling method and system |
| CN110268404A (en) * | 2019-05-09 | 2019-09-20 | 长江存储科技有限责任公司 | For the emulation mode in functional equivalence detection |
| CN113138318A (en) * | 2021-04-27 | 2021-07-20 | 山东英信计算机技术有限公司 | Phase jitter test method and system |
| CN115361015A (en) * | 2022-10-14 | 2022-11-18 | 成都本原聚能科技有限公司 | Phase-locked loop circuit, control method thereof and phase-locked loop chip |
| CN117054847A (en) * | 2023-07-31 | 2023-11-14 | 中国矿业大学 | Method for evaluating VCO phase noise sensitivity |
| CN117054847B (en) * | 2023-07-31 | 2024-04-19 | 中国矿业大学 | Method for evaluating VCO phase noise sensitivity |
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| CN106897506B (en) * | 2017-02-09 | 2020-05-01 | 中国科学院微电子研究所 | Method for predicting output signal period jitter in phase-locked loop design |
| CN106953635A (en) * | 2017-02-21 | 2017-07-14 | 江汉大学 | A kind of frequency source modeling method and system |
| CN110268404A (en) * | 2019-05-09 | 2019-09-20 | 长江存储科技有限责任公司 | For the emulation mode in functional equivalence detection |
| CN110268404B (en) * | 2019-05-09 | 2020-09-25 | 长江存储科技有限责任公司 | Simulation method for function peer detection |
| CN113138318A (en) * | 2021-04-27 | 2021-07-20 | 山东英信计算机技术有限公司 | Phase jitter test method and system |
| CN113138318B (en) * | 2021-04-27 | 2022-05-06 | 山东英信计算机技术有限公司 | Phase jitter test method and system |
| CN115361015A (en) * | 2022-10-14 | 2022-11-18 | 成都本原聚能科技有限公司 | Phase-locked loop circuit, control method thereof and phase-locked loop chip |
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