CN103441069A - Method for improving active area - Google Patents
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- CN103441069A CN103441069A CN201310337067XA CN201310337067A CN103441069A CN 103441069 A CN103441069 A CN 103441069A CN 201310337067X A CN201310337067X A CN 201310337067XA CN 201310337067 A CN201310337067 A CN 201310337067A CN 103441069 A CN103441069 A CN 103441069A
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- active area
- polycrystalline silicon
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- hard mask
- area damage
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Abstract
The invention relates to a method for improving an active area. The method includes the steps that a silicon substrate provided with a polycrystalline silicon layer is provided; a pre-injection ion technology is performed on the polycrystalline silicon layer, and a PETEOS oxidation film is deposited for covering the surface of the polycrystalline silicon layer; the oxidation film serves as a hard mask to etch the polycrystalline silicon layer, and a polycrystalline silicon grid electrode is formed. The PETEOS oxidation film prepared on a semiconductor component through a plasma enhance chemical vapor deposition technology serves as the hard mask in a polycrystalline silicon etching technology, therefore, in the process of etching the polycrystalline silicon grid electrode, the phenomenon that the hard mask and pre-injection ions are reacted mutually to cause aggregation can be avoided, and damage to the active area of the semiconductor component after the etching technology is further effectively avoided. Meanwhile, due to the fact that the PETEOS oxidation film is adopted as the polycrystalline silicon hard mask, the heat treatment technological step following the pre-injection ion technology is indirectly omitted, and the beneficial effect that technological time is saved is achieved.
Description
Technical field
The present invention relates to a kind of process of semiconductor device, relate in particular to a kind of method of improving the active area damage.
Background technology
At present, along with constantly dwindling of semiconductor device critical size, the gate isolation layer thickness also dwindles thereupon, makes the thickness of gate depletion layer increasing on the impact of performance of semiconductor device.
In the semiconductor technology of 55 nanometers, in order to reduce the electrical thickness of grid, industry often adopts the pre-injection technique of grid.This technology often is used to the N-type device area.
After grid is injected in advance, the ion injected can present inhomogeneous distributions in injection zone, at this moment usually this semiconductor device after Implantation is heat-treated to technique, thereby make the ion injected close with the silicon bond of grid better or promote ion near the grid oxygen interface.But, for considering with static memory device needing of being complementary, do not heat-treat technique after Implantation.At this moment, most pre-injection ion can accumulate in the surface of polysilicon, make N/P type region surface property difference strengthen, and, follow-up, polysilicon is carried out to etching while forming grid structure, the plasma enhanced silicon that in prior art, normal employing PEOX(raw material is silane and nitrous oxide) as the hard mask in polycrystalline silicon etching process, this oxide-film is relatively fine and close, and growing environment vacuum degree is higher, therefore, be prone to the phenomenon that pre-injection ion is separated out in the process of the follow-up hard mask of growing polycrystalline silicon, thereby in hard mask surface and the inner cavity of reuniting that forms, and these cavities can be delivered to step by step the surface of active area after polycrystalline silicon etching process, and then cause the damage of active area.
Fig. 1 injects the device architecture schematic diagram of ion processes in advance to semiconductor device in prior art; Fig. 2 is to heat-treat the device architecture schematic diagram of technique through the pre-semiconductor device injected in prior art.As shown in Figure 1, this semiconductor device comprises a P type substrate 1 ', be provided with fleet plough groove isolation structure 2 ' in this P type substrate, be coated with one deck grid oxide layer 3 ' on this P type substrate 1 ', be coated with one deck polycrystalline silicon membrane 4 ' on this grid oxide layer, this polycrystalline silicon membrane 4 ' is for follow-up polycrystalline silicon etching process, to form polysilicon gate.As Figure 1 illustrates in, after this semiconductor device is carried out to the pre-injection technology of N-type ion, the ion 5 ' of injection presents uneven distribution in this polycrystalline silicon membrane 4 ', and most of ion 5 ' is positioned at the surface of this polycrystalline silicon membrane 4 '; Continuation is heat-treated technique to this semiconductor device, and as shown in Figure 2, the injection ion 5 ' that is positioned at polycrystalline silicon membrane 4 ' in the semiconductor device after Technology for Heating Processing is close towards the grid oxygen interface.
Fig. 3 A is the device architecture schematic diagram after preparing hard mask polysilicon in prior art on the semiconductor device after Technology for Heating Processing; Fig. 3 B is the device architecture schematic diagram after preparing hard mask polysilicon in prior art on the semiconductor device without after Overheating Treatment technique.As shown in Figure 3A, prepare the plasma enhanced silicon that one deck PEOX(raw material is silane and nitrous oxide on the grid oxide layer of semiconductor device) hard mask polysilicon 6 ', the injection ion 5 ' in the polycrystalline silicon membrane of the semiconductor device after the preorder Technology for Heating Processing presents normal distribution; As shown in Figure 3 B, prepare one deck PEOX hard mask polysilicon 6 ' on the grid oxide layer of semiconductor device ', do not pass through the semiconductor device of preorder Technology for Heating Processing, while after pre-injection technology, carrying out the preparation of hard mask polysilicon, the injection ion 5 ' that is arranged in this polycrystalline silicon membrane can be separated out, in surface and the inner cavity of reuniting that forms of hard mask polysilicon.
Fig. 4 A is to the device architecture schematic diagram after the polycrystalline silicon membrane etching of pre-injection ion normal distribution in prior art; Fig. 4 B is the device architecture schematic diagram after the polycrystalline silicon membrane after in prior art, pre-injection ion being separated out carries out etching.As shown in Figure 4 A, the polycrystalline silicon membrane of pre-injection ion normal distribution is carried out to the process of etching formation polysilicon gate 7 ', the active area of the previous ion pair device injected can not cause damage; As shown in Figure 4 B, owing to after previous pre-injection technology, not adopting Technology for Heating Processing, make and pre-the separating out of ion of injecting occur in preparing the process of hard mask polysilicon, surface and the inner cavity of reuniting that forms at hard mask, these cavities form polysilicon gate 7 ' after etching polysilicon ' process in, be delivered to step by step the surface of device active region, and then cause the damage of device active region.
Chinese patent (application publication number: CN102655088A) disclose a kind of method of repairing ion implantation damage, comprise the following steps: semi-conductive substrate is provided, described Semiconductor substrate is implemented to ion implantation technology: in the atmosphere of hydrogen, described Semiconductor substrate is heat-treated to technique, to repair ion implantation damage; Described Semiconductor substrate is carried out to metalized; Form metal connecting line above described Semiconductor substrate.This patented method can be repaired the lattice damage of Implantation to semiconductor substrate surface.The method of its use is still Technology for Heating Processing, when the process conditions limit value can not be used Technology for Heating Processing, just can not solve by the method the problem of active area damage.
Therefore, at present for after pre-injection technology, omitting Technology for Heating Processing, can not guarantee to avoid the damage that device active region is caused follow-up after polysilicon is carried out to etching.
Summary of the invention
In view of the above problems, the invention provides a kind of method of improving the active area damage.
The technical scheme that technical solution problem of the present invention adopts is:
A kind of method of improving the active area damage, be applied to reduce in the technique of the electrical thickness of polysilicon gate, wherein,
One silicon substrate that is provided with polysilicon layer is provided;
After described polysilicon layer is injected to ion processes in advance, deposition PETEOS oxide-film covers the surface of described polysilicon layer;
Take described oxide-film as the described polysilicon layer of hard mask etching, form polysilicon gate.
The described method of improving the active area damage, wherein, be provided with fleet plough groove isolation structure and P well region in described silicon substrate, described fleet plough groove isolation structure is isolated two adjacent P well regions;
Wherein, described polysilicon gate is positioned at the top of described P well region.
The described method of improving the active area damage, wherein, the surface coverage of described silicon substrate has oxidation insulating layer, and described polycrystalline silicon membrane covers the upper surface of this oxidation insulating layer.
The described method of improving the active area damage, wherein, adopt tetraethoxysilane and oxygen as raw material, in the described PETEOS oxide-film of upper surface deposition formation of described polysilicon layer.
The described method of improving the active area damage, wherein, adopt the N-type ion to carry out described pre-injection ion processes.
The described method of improving the active area damage, wherein, described N-type ion is P or As ion.
The described method of improving the active area damage, wherein, using plasma strengthens chemical vapor deposition method and prepares described PETEOS oxide-film.
The described method of improving the active area damage, wherein, under the process conditions that are 350 ℃～450 ℃ in temperature, carry out described plasma enhanced chemical vapor deposition technique.
The described method of improving the active area damage, wherein, under the process conditions that are 10Torr at pressure, carry out described plasma enhanced chemical vapor deposition technique.
The described method of improving the active area damage, wherein, the thickness of described PETEOS oxide-film is
Technique scheme has following advantage or beneficial effect:
After the present invention injects ion processes in advance by the polycrystalline silicon membrane to semiconductor device, existing Technology for Heating Processing step is omitted, and using plasma on semiconductor device is strengthened to chemical vapor deposition method and prepare the PETEOS oxide layer, make this PETEOS oxide layer carry out etching as hard mask polysilicon to polysilicon.Form in the process of polysilicon gate in etching, can avoid hard mask to inject with pre-the agglomeration caused after the ion interreaction, and then avoid the damage to active area of semiconductor device.
The accompanying drawing explanation
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.Yet appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
Fig. 1 injects the device architecture schematic diagram of ion processes in advance to semiconductor device in prior art;
Fig. 2 is to heat-treat the device architecture schematic diagram of technique through the pre-semiconductor device injected in prior art;
Fig. 3 A is the device architecture schematic diagram after preparing hard mask polysilicon in prior art on the semiconductor device after Technology for Heating Processing;
Fig. 3 B is the device architecture schematic diagram after preparing hard mask polysilicon in prior art on the semiconductor device without after Overheating Treatment technique;
Fig. 4 A is to the device architecture schematic diagram after the polycrystalline silicon membrane etching of pre-injection ion normal distribution in prior art;
Fig. 4 B is the device architecture schematic diagram after the polycrystalline silicon membrane after in prior art, pre-injection ion being separated out carries out etching;
Fig. 5 is the device architecture schematic diagram prepared on the semiconductor device of the embodiment of the present invention after polycrystalline silicon membrane;
Fig. 6 injects ion processes semiconductor device structure schematic diagram afterwards in advance in the embodiment of the present invention;
Fig. 7 is the semiconductor device structure schematic diagram after the hard mask of preparation PETEOS in the embodiment of the present invention;
Fig. 8 carries out the semiconductor device structure schematic diagram after etching to polycrystalline silicon membrane in the embodiment of the present invention.
Embodiment
The invention provides a kind of process of semiconductor device, especially a kind of method of improving the active area damage.The present invention can be used in semiconductor technology that technology node is 65/55nm; The present invention can be used in the technology platforms such as Logic.
The inventive method is by after injecting ion processes in advance on the polycrystalline silicon membrane on semiconductor device, save Technology for Heating Processing step of the prior art, and continue to pass through plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition on the surface of this polycrystalline silicon membrane, abbreviation PECVD) process prepares TEOS(raw material tetraethoxysilane and oxygen, wherein, the molecular formula of tetraethoxysilane is Si (OC
2h
5)
4) oxide-film is as the hard mask in polycrystalline silicon etching process, take and replace the plasma enhanced oxidation silicon that PEOX(raw material of the prior art is silane and nitrous oxide) hard mask polysilicon, the plasma enhanced oxidation silicon that the PETEOS(raw material of usining is tetraethoxysilane and oxygen) as hard mask polysilicon can avoid with polycrystalline silicon membrane in pre-injection ionic reaction form the cavity of reuniting, at the polycrystalline silicon membrane to follow-up, carry out in the process of etching technics formation polysilicon gate, avoided the step by step transmission of cavity in etching process of reuniting, and then avoid the damage of active area of semiconductor device.
Below in conjunction with specific embodiments and the drawings, the method for improving the active area damage of the present invention is elaborated.
Fig. 5 is the device architecture schematic diagram prepared on the semiconductor device of the embodiment of the present invention after polycrystalline silicon membrane; As shown in Figure 5, semiconductor structure in the embodiment of the present invention comprises a silicon substrate 1, this silicon substrate 1 is P type silicon substrate, be formed with shallow trench isolation from (shallow trench isolation in this P type silicon substrate, be called for short STI) structure 2, upper surface in this silicon substrate 1 is coated with oxidation insulating layer 3, and this oxidation insulating layer 3 can be used to grid oxide layer after follow-up grid etch technique.
Take above-mentioned semiconductor structure as basis, prepare one deck polycrystalline silicon membrane 4 on oxidation insulating layer 3, to cover the upper surface of this oxidation insulating layer 3, this polycrystalline silicon membrane 4 can form polysilicon gate after follow-up grid etch technique.
Fig. 6 injects ion processes semiconductor device structure schematic diagram afterwards in advance in the embodiment of the present invention; As shown in Figure 6, this semiconductor device that is prepared with polycrystalline silicon membrane 4 is carried out to the pre-injection technology of N-type ion 5, so that N-type foreign ion 5 is distributed in the inside of this polycrystalline silicon membrane 4.Can adopt phosphorus (P) ion, arsenic (As) ion etc. according to the concrete technology demand for the N-type foreign ion 5 injected, concrete technology method for pre-injection ion processes can be determined according to the actual process demand, owing to injecting in advance the known technology means that ion processes is this area, therefore do not do and repeat at this.
Fig. 7 is the semiconductor device structure schematic diagram after the hard mask of preparation PETEOS in the embodiment of the present invention; As shown in Figure 7, preparation PETEOS(Plasma Enhanced TEOS on the polycrystalline silicon membrane 4 prepared in preorder) oxide-film, to cover the upper surface of this polycrystalline silicon membrane 4, and using this PETEOS oxide-film as hard mask 6 in the etching technics of follow-up polycrystalline silicon membrane.
The concrete grammar for preparing this PETEOS oxide-film comprises: take tetraethoxysilane and oxygen as raw material, by plasma enhanced chemical vapor deposition technique, in temperature, be to prepare thickness under 350 ℃～450 ℃ (as 350 ℃, 370 ℃, 400 ℃, 420 ℃, 450 ℃ etc.), the pressure process conditions that are 10 holders (Torr) to be
the PETEOS oxide-film; Wherein, for above-mentioned process conditions, preferably temperature is 400 ℃ in the present embodiment, and pressure is 10 holders, and the thickness of the prepared hard mask of PETEOS is
Fig. 8 carries out the semiconductor device structure schematic diagram after etching to polycrystalline silicon membrane in the embodiment of the present invention; As shown in Figure 8, polycrystalline silicon membrane 4 after etching forms grid structure 7, in this etching process, can first on hard mask polysilicon 6, prepare photoresist (PR) (not illustrating in the drawings), then form photoresistance pattern (not illustrating in the drawings), take this photoresistance pattern carries out etching to the hard mask of this PETEOS as mask, remove remaining photoresistance, then, the hard mask of PETEOS of then take after etching, as stopping the etching of the oxidation insulating layer that carries out polycrystalline silicon membrane 6 and below, finally forms polysilicon gate construction 7 as shown in Figure 7.In above-mentioned etching technics, can adopt the conventional etching process such as dry etching and wet etching according to the concrete technology demand, in embodiments of the present invention, preferably adopt dry etching to carry out etching to above-mentioned step.
The semiconductor device structure illustrated according to Fig. 8, do not form the cavity of reuniting in the active area of semiconductor device, visible, after the etching of having carried out polycrystalline silicon membrane 4, the active area of semiconductor device does not cause damage because of the injection ion 5 of the pre-injection ion processes of preorder, this is because the hard mask of PETEOS prepared by plasma enhanced chemical vapor deposition technique is so fine and close not as the hard mask of PEOX of the prior art, comparatively loose, thereby make the pre-injection ion distribution in preorder technique more even, improve the post-depositional ion of hard mask polysilicon and separate out agglomeration, the damage of the device active region while having avoided forming polysilicon gate after the etching polysilicon.
In sum, the present invention is directed to the preparation technology of the polysilicon gate that is not suitable for using Technology for Heating Processing, PEOX hard mask polysilicon used in the prior art is replaced to the PETEOS hard mask polysilicon, material behavior by the hard mask of this material, reach pre-injection ion distribution even, and the effect that is difficult for separating out, avoided after the etching technics of polysilicon gate in damage that device active region is formed.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.In claims scope, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. a method of improving the active area damage, be applied to reduce, in the technique of the electrical thickness of polysilicon gate, it is characterized in that,
One silicon substrate that is provided with polysilicon layer is provided;
After described polysilicon layer is injected to ion processes in advance, deposition PETEOS oxide-film covers the surface of described polysilicon layer;
Take described oxide-film as the described polysilicon layer of hard mask etching, form polysilicon gate.
2. the method for improving the active area damage as claimed in claim 1, is characterized in that, be provided with fleet plough groove isolation structure and P well region in described silicon substrate, described fleet plough groove isolation structure is isolated two adjacent P well regions;
Wherein, described polysilicon gate is positioned at the top of described P well region.
3. the method for improving the active area damage as claimed in claim 1, is characterized in that, the surface coverage of described silicon substrate has oxidation insulating layer, and described polycrystalline silicon membrane covers the upper surface of this oxidation insulating layer.
4. the method for improving the active area damage as claimed in claim 1, is characterized in that, adopts tetraethoxysilane and oxygen as raw material, in the described PETEOS oxide-film of upper surface deposition formation of described polysilicon layer.
5. the method for improving the active area damage as claimed in claim 1, is characterized in that, adopts the N-type ion to carry out described pre-injection ion processes.
6. the method for improving the active area damage as claimed in claim 5, is characterized in that, described N-type ion is P or As ion.
7. the method for improving the active area damage as claimed in claim 1, is characterized in that, using plasma strengthens chemical vapor deposition method and prepares described PETEOS oxide-film.
8. the method for improving the active area damage as claimed in claim 7, is characterized in that, under the process conditions that are 350 ℃～450 ℃ in temperature, carries out described plasma enhanced chemical vapor deposition technique.
9. the method for improving the active area damage as claimed in claim 7, is characterized in that, under the process conditions that are 10Torr at pressure, carries out described plasma enhanced chemical vapor deposition technique.
10. the method for improving the active area damage as claimed in claim 1, is characterized in that, the thickness of described PETEOS oxide-film is
.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106876322A (en) * | 2017-01-19 | 2017-06-20 | 武汉新芯集成电路制造有限公司 | The zanjon groove forming method and semiconductor structure of a kind of silicon |
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| CN1612312A (en) * | 2003-10-31 | 2005-05-04 | 中芯国际集成电路制造(上海)有限公司 | Method for monitoring ion disposing process |
| CN1716541A (en) * | 2004-06-30 | 2006-01-04 | 海力士半导体有限公司 | Gate structure of semiconductor memory device |
| US20070275532A1 (en) * | 2006-05-24 | 2007-11-29 | International Business Machines Corporation | Optimized deep source/drain junctions with thin poly gate in a field effect transistor |
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| US5431770A (en) * | 1993-10-13 | 1995-07-11 | At&T Corp. | Transistor gate formation |
| CN1612312A (en) * | 2003-10-31 | 2005-05-04 | 中芯国际集成电路制造(上海)有限公司 | Method for monitoring ion disposing process |
| CN1716541A (en) * | 2004-06-30 | 2006-01-04 | 海力士半导体有限公司 | Gate structure of semiconductor memory device |
| US20070275532A1 (en) * | 2006-05-24 | 2007-11-29 | International Business Machines Corporation | Optimized deep source/drain junctions with thin poly gate in a field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106876322A (en) * | 2017-01-19 | 2017-06-20 | 武汉新芯集成电路制造有限公司 | The zanjon groove forming method and semiconductor structure of a kind of silicon |
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