CN103414525A - System and method for automatically adjusting channel output level of superheterodyne receiving analytical instrument - Google Patents
System and method for automatically adjusting channel output level of superheterodyne receiving analytical instrument Download PDFInfo
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Abstract
The invention discloses a system and method for automatically adjusting channel output level of a superheterodyne receiving analytical instrument. The system for automatically adjusting the channel output level of the superheterodyne receiving analytical instrument comprises a radio frequency channel, a medium frequency channel, an analog-to-digital converter, an FPGA/DSP, a scanning controller, a CPU, a timer, a channel output level controller, a counter, a coupler, a power detection unit and an interrupt controller. Compared with the prior art, due to the fact that the channel output level controller is used in cooperation with the coupler, the power detection unit, the timer, the counter and the interrupt controller to achieve the function of automatic control over the channel output level in the process of scanning, the purpose of protecting the superheterodyne receiving analytical instrument and the purpose of improving signal measurement accuracy are achieved. In addition, the number of times of interference of the CPU to the scanning process is greatly reduced, the measuring time is reduced, and smoothness of integral operation of the superheterodyne receiving analytical instrument is improved.
Description
Technical field
The present invention relates to a kind of automatic regulating system of superheterodyne reception analytical instrument passage output level and the Automatic adjustment method of passage output level.
Background technology
While using the superheterodyne reception analytical instrument to measure unknown electromagnetic environment, in unknown electromagnetic environment, may there be some high-power signals, these high-power signals the lighter affects the nonlinear device in the superheterodyne reception analytical instrument, cause measurement inaccurate, severe one can be damaged those power easily worn parts, causes equipment fault.How the control channel output level becomes the important topic of research with protection superheterodyne reception analytical instrument the certainty of measurement that improves high-power signal.
When carrying out the unknown signaling measurement; the superheterodyne reception analytical instrument should be able to change path gain automatically according to the watt level of measured signal: if measured signal is low-power level signal; the superheterodyne reception analytical instrument should be able to provide maximum path gain to improve receiving sensitivity; if measured signal is high-power signal, the superheterodyne reception analytical instrument should reduce path gain to improve certainty of measurement and to protect those power easily worn parts.
The superheterodyne reception analytical instrument adopts following three kinds of methods to regulate the passage output level usually at present.First method is manually to be arranged by the user, and the user, by amplifier and the attenuator of superheterodyne reception analytical instrument front radio-frequency path and intermediate-frequency channel are set, manually changes the output level of passage; Second method is the change that superheterodyne reception analytical instrument mainframe program participates in channel gain, before each Frequency point carries out power measurement, at first mainframe program carries out, and then according to the premeasuring result, attenuator and amplifier etc. is set, and finally formally measures.The third mode is to increase automatic gain control circuit in the intermediate-frequency channel of superheterodyne reception analytical instrument, before each Frequency point carries out power measurement, mainframe program or FPGA adjust the intermediate-frequency channel gain, make the signal power substantially constant that enters digital to analog converter.
Yet there is following technical deficiency in above-mentioned three kinds of passage output level control methods:
(1) shortcoming that adopts the manual method arranged of user to change the passage output level is that control rate is slow, which partly transships to need judgement superheterodyne reception analytical instrument, require operating personnel to have more rich experience, while carrying out the measurement of a plurality of Frequency points, workload is large;
(2) shortcoming that adopts mainframe program to participate in the change of channel gain is that mainframe program needs to participate in the hardware controls such as channel power detection, attenuator and amplifier, sweep parameter setting, digital to analog converter employing control etc. on each measuring frequency point, thereby greatly increased the control time, measuring speed has slowed down, in addition, the occupancy of CPU is high, can have influence on the processes such as data are processed, demonstration refreshes, measuring speed has further slowed down;
(3) shortcoming that adopts the intermediate frequency automatic gain method to change the passage output level is that automatic gain method can not be controlled the scanning sequence control gained and do not participate in complete machine in radio-frequency channel, and sphere of action is limited.
Fig. 1 shows mainframe program and participates in the control flow chart that the passage output level changes.As shown in Figure 1, general superheterodyne reception analytical instrument radio frequency and the regulating system of intermediate-frequency channel output level, comprise radio-frequency channel, intermediate-frequency channel, analog to digital converter, FPGA/DSP, scanning monitor and CPU.
Wherein, the functions such as the decay of the general settling signal in radio-frequency channel, amplification, filtering and mixing, the attenuator in radio-frequency channel and amplifier can be used for regulating the passage output level.
The functions such as the general settling signal channel selecting of intermediate-frequency channel, channel compensation, decay, amplification, filtering and mixing, the attenuator of intermediate-frequency channel and amplifier can be used for regulating the passage output level.
Analog to digital converter completes the translation function of analog signal to digital signal.
FPGA/DSP completes various Digital Signal Processing and analytic function.
Scanning monitor produces various synchronizing signals, makes the mixing local oscillator in radio-frequency channel, compensating circuit, analog to digital converter, the FPGA/DSP synchronous operation in intermediate-frequency channel.
CPU is responsible for arranging scanning monitor and controls parameter, and radio-frequency channel and intermediate-frequency channel attenuator, amplifier and filter status are set, response user command and to processing and the demonstration of FPGA/DSP operation result.
General superheterodyne reception analytical instrument radio frequency and the control method of intermediate-frequency channel output level comprise:
(1) the initial setting up state of the state that arranges according to the user of CPU or program acquiescence pre-sets the attenuator of radio frequency and intermediate-frequency channel, amplifier etc.;
(2) CPU arranges the scanning monitor parameter, and the gated sweep controller starts scanning;
(3) scanning monitor produces synchronizing signal, acts on respectively radio-frequency channel, intermediate-frequency channel, analog to digital converter and FPGA/DSP, makes each several part start linkage work;
(4) CPU analyzes the signal amplitude that FPGA/DSP processes, if signal amplitude does not meet the amplitude range of procedure stipulation, CPU will control attenuator, amplifier according to the rule of setting in program so, changes the output level of passage;
(5) repeating step (2) is to step (4), until the signal amplitude amplitude range up to specification of measuring;
(6) the final signal measurement result of reality;
(7) CPU carries out the measurement of next Frequency point, and repeating step (1) is to step (6).
By the control method with the upper channel output level, can find, CPU needs to participate in scanning process at any time, thereby has greatly affected sweep speed.Based on this, passage output level control method of the prior art requires further improvement.
Summary of the invention
Based on above-mentioned technical problem, the present invention proposes a kind of automatic regulating system of superheterodyne reception analytical instrument passage output level, it adopts following technical scheme:
The automatic regulating system of superheterodyne reception analytical instrument passage output level, comprise radio-frequency channel, intermediate-frequency channel, analog to digital converter, FPGA/DSP, scanning monitor and CPU, also comprises:
Timer, for the pulse signal of the parameter generating constant duration according to the CPU setting;
Passage output level controller, for responding the control command that CPU sends, for generation of end interrupt and send to CPU, for attenuator and the amplifier of radio-frequency channel and intermediate-frequency channel are controlled, for the scanning time started of the pulse signal gated sweep controller that scanning monitor carried out to the parameter setting and produce according to timer, be used to FPGA/DSP that current radio-frequency channel and intermediate-frequency channel facilities are provided and arrange this result be whether current/recalculate sign;
Counter, for the count pulse that passage output level controller is produced, count, when count value equates with the pre-set count values of CPU, counter produces interrupt signal and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response count device produces;
Coupler, for the output that will be coupled through the signal of radio-frequency channel and intermediate-frequency channel output;
Power detecting unit, for amplifying and detection through the signal of coupler coupling output;
Interrupt control unit, for the signal after the power detecting unit detection is detected, if the detection signal range value does not meet the default amplitude range of CPU, interrupt control unit produces interrupt signal, and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response interrupt control unit produces is also carried out the interruptions reason, and the passage output level is carried out the interruption reset condition operation to interrupt control unit.
In the automatic regulating system of above-mentioned superheterodyne reception analytical instrument passage output level,
Radio-frequency channel, for input signal is decayed, amplification, filtering and mixing operation, the attenuator in radio-frequency channel and amplifier are for regulating the passage output level;
Intermediate-frequency channel, carry out channel selecting, channel compensation, decay, amplification, filtering and mixing operation for the signal to radio-frequency channel output, and the attenuator of intermediate-frequency channel and amplifier can be used for regulating the passage output level;
Analog to digital converter be digital signal for the analog signal conversion that will export through intermediate-frequency channel;
FPGA/DSP, be used to receiving the digital signal of analog converter output, and process and analysis operation digital signal;
Scanning monitor, for generation of various synchronizing signals, make the mixing local oscillator in radio-frequency channel, compensating circuit, analog to digital converter, the FPGA/DSP synchronous operation in intermediate-frequency channel;
CPU, for passage output level controller is carried out to the initial condition setting, for timer is carried out reset operation and according to scanning mode, timer carried out to the parameter setting, for counter being carried out to reset operation and according to scanning mode, counter being carried out to the parameter setting.
In the automatic regulating system of above-mentioned superheterodyne reception analytical instrument passage output level, timer, counter, interrupt control unit and passage output level controller are positioned at FPGA/DSP inside.
In the automatic regulating system of above-mentioned superheterodyne reception analytical instrument passage output level, passage output level controller comprises: data register, and the data that produce be used to storing CPU, comprise scan-data and control data; Interrupt register, the interruption produced be used to storing interrupt control unit; The channel status register, be sent to the state of FPGA/DSP/sign for storage; Interruption processing module, for producing scanning impulse, count pulse, reset signal, end interrupt signal and state/flag data according to commutator pulse, control data, interrupt signal and built-in interruption processing rule; Sweep parameter arranges module, according to scan-data and scanning pulse signal gated sweep counter; The radio-frequency channel control module, control radio-frequency channel according to the radio-frequency channel status data in the channel status register; The intermediate-frequency channel control module, control intermediate-frequency channel according to the intermediate-frequency channel status data in the channel status register.
Another object of the present invention is to propose a kind of Automatic adjustment method of superheterodyne reception analytical instrument passage output level, and it comprises following job step:
A, CPU carry out the initial condition setting to passage output level controller;
B, passage output level controller arrange scanning monitor according to the parameter that CPU arranges;
C, CPU carry out reset operation and counter are arranged counter;
D, CPU carry out reset operation and timer are carried out to the parameter setting timer, and timer starts to produce the pulse signal of constant duration according to parameters;
E, passage output level controller are carried out following operation after receiving the pulse signal that timer produces: 1. interrupt control unit is carried out to reset operation, 2. attenuator, the amplifier of radio-frequency channel and intermediate-frequency channel are pre-seted, whether 3. notify the current radio-frequency channel of FPGA/DSP and intermediate-frequency channel facilities and this result is set is current calculation flag, 4. produce count pulse to counter, 5. the gated sweep controller starts scanning;
F, scanning monitor produce synchronizing signal, and radio-frequency channel, intermediate-frequency channel, analog to digital converter and FPGA/DSP start linkage work;
The signal of g, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, interrupt control unit judges according to the amplitude of rectified signal;
Within if the rectified signal amplitude of h radio-frequency channel, intermediate-frequency channel is in respectively interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range simultaneously, interrupt control unit does not produce interrupt signal, current Frequency point is measured and is completed, when the next pulse signal of waiting timer arrives, forward step e to, start to carry out the measurement of next Frequency point;
Within if the rectified signal amplitude of i radio-frequency channel is in outside the default radio-frequency channel amplitude range of interrupt control unit and the rectified signal amplitude of intermediate-frequency channel is in the default intermediate-frequency channel amplitude range of interrupt control unit, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier state of radio-frequency channel; Within if the rectified signal amplitude of intermediate-frequency channel is in outside the default intermediate-frequency channel amplitude range of interrupt control unit and the rectified signal amplitude of radio-frequency channel is in the default radio-frequency channel amplitude range of interrupt control unit, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier state of intermediate-frequency channel; If the rectified signal amplitude of radio-frequency channel, intermediate-frequency channel is in respectively outside interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range simultaneously, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier state of radio-frequency channel; When the next pulse signal of waiting timer arrives, passage output level controller carries out following operation and 1. interrupt control unit is carried out to reset operation, 2. notify FPGA/DSP current radio-frequency channel facilities and intermediate-frequency channel facilities, and this result of calculation is set is calculation flag again, 3. the gated sweep controller starts scanning;
J, scanning monitor produce synchronizing signal, radio-frequency channel, intermediate-frequency channel, analog to digital converter and beginning linkage work; This calculation process result of FPGA/DSP covers calculation process result last time;
The signal of k, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, interrupt control unit rejudges according to the amplitude of rectified signal;
Within if the rectified signal amplitude of l radio-frequency channel, intermediate-frequency channel is in respectively interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range simultaneously, interrupt control unit does not produce interrupt signal, current Frequency point is measured and is completed, when the next pulse signal of waiting timer arrives, forward step e to, start to carry out the measurement of next Frequency point;
If the rectified signal range value of m radio-frequency channel and/or intermediate-frequency channel still is in outside interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range, repeated execution of steps i is to step l, until within the rectified signal amplitude of radio-frequency channel, intermediate-frequency channel is in respectively the default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range of interrupt control unit simultaneously, current Frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start to carry out the measurement of next Frequency point;
N, when the count value of counter equates with the pre-set count values of CPU, counter produce to interrupt, and shows that current measurement point be last measurement point, repeated execution of steps e arrives step m;
O, passage output level controller produce end interrupt and notify CPU, and this scanning process finishes;
P, CPU carry out display operation to the result that FPGA/DSP processes.
Advantage of the present invention is:
Compared with prior art, the present invention uses the channel levels o controller and in conjunction with coupler, power detecting unit, timer, counter and interrupt control unit complete the automatic control function of passage output level in scanning process, thereby reach the purpose of protection superheterodyne reception analytical instrument and raising signal measurement precision, in addition, the present invention has greatly reduced the intervention number of times of CPU to scan procedure, reduced Measuring Time, the channel levels o controller has alleviated the workload of CPU to a great extent, CPU can carry out algorithm calculating, show and to refresh and the work such as man-machine interaction, improved the fluency of superheterodyne reception analytical instrument overall operation.
The accompanying drawing explanation
Fig. 1 is the structured flowchart of the automatic regulating system of prior art superheterodyne reception analytical instrument passage output level;
Fig. 2 is the structured flowchart of the automatic regulating system of superheterodyne reception analytical instrument passage output level of the present invention;
Fig. 3 is the cut-away view of passage output level controller in the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is described in further detail:
In conjunction with shown in Figure 2, the automatic regulating system of superheterodyne reception analytical instrument passage output level, comprise radio-frequency channel, intermediate-frequency channel, analog to digital converter, FPGA/DSP, scanning monitor, CPU, timer, passage output level controller, counter, coupler, power detecting unit and interrupt control unit.
Radio-frequency channel, for input signal is decayed, amplification, filtering and mixing operation, the attenuator in radio-frequency channel and amplifier are for regulating the passage output level.
Intermediate-frequency channel, carry out channel selecting, channel compensation, decay, amplification, filtering and mixing operation for the signal to radio-frequency channel output, and the attenuator of intermediate-frequency channel and amplifier can be used for regulating the passage output level.
Analog to digital converter be digital signal for the analog signal conversion that will export through intermediate-frequency channel.
FPGA/DSP, be used to receiving the digital signal of analog converter output, and process and analysis operation digital signal.
Scanning monitor, for generation of various synchronizing signals, make the mixing local oscillator in radio-frequency channel, compensating circuit, analog to digital converter, the FPGA/DSP synchronous operation in intermediate-frequency channel.
CPU, for passage output level controller is carried out to the initial condition setting, for timer is carried out reset operation and according to scanning mode, timer carried out to the parameter setting, for counter being carried out to reset operation and according to scanning mode, counter being carried out to the parameter setting.
Timer, for the pulse signal of the parameter generating constant duration according to the CPU setting.
Passage output level controller, for responding the control command that CPU sends, for generation of end interrupt and send to CPU, for attenuator and the amplifier of radio-frequency channel and intermediate-frequency channel are controlled, for the scanning time started of the pulse signal gated sweep controller that scanning monitor carried out to the parameter setting and produce according to timer, be used to FPGA/DSP that current radio-frequency channel and intermediate-frequency channel facilities are provided and arrange this result be whether current/recalculate sign.
Counter, for the count pulse that passage output level controller is produced, count, when count value equates with the pre-set count values of CPU, counter produces interrupt signal and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response count device produces.
Coupler, for the output that will be coupled through the signal of radio-frequency channel and intermediate-frequency channel output.
Power detecting unit, for amplifying and detection through the signal of coupler coupling output.
Interrupt control unit, for the signal after the power detecting unit detection is detected, if the detection signal range value does not meet the default amplitude range of CPU, interrupt control unit produces interrupt signal, and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response interrupt control unit produces is also carried out the interruptions reason, and the passage output level is carried out the interruption reset condition operation to interrupt control unit.
In actual use, preferably timer, counter, interrupt control unit and passage output level controller all are incorporated into to a FPGA/DSP inside.
In conjunction with shown in Figure 3, passage output level controller comprises:
Data register, the data that produce be used to storing CPU, comprise scan-data and control data;
Interrupt register, the interruption produced be used to storing interrupt control unit;
The channel status register, be sent to the state of FPGA/DSP/sign for storage;
Interruption processing module, for producing scanning impulse, count pulse, reset signal, end interrupt signal and state/flag data according to commutator pulse, control data, interrupt signal and built-in interruption processing rule;
Sweep parameter arranges module, according to scan-data and scanning pulse signal gated sweep counter;
The radio-frequency channel control module, control radio-frequency channel according to the radio-frequency channel status data in the channel status register;
The intermediate-frequency channel control module, control intermediate-frequency channel according to the intermediate-frequency channel status data in the channel status register.
The Automatic adjustment method of superheterodyne reception analytical instrument passage output level is as follows:
A, CPU carry out the initial condition setting to passage output level controller;
B, passage output level controller arrange scanning monitor according to the parameter that CPU arranges;
C, CPU carry out reset operation and counter are arranged counter;
D, CPU carry out reset operation and timer are carried out to the parameter setting timer, and timer starts to produce the pulse signal of constant duration according to parameters;
E, passage output level controller are carried out following operation after receiving the pulse signal that timer produces: 1. interrupt control unit is carried out to reset operation, 2. attenuator, the amplifier of radio-frequency channel and intermediate-frequency channel are pre-seted, whether 3. notify the current radio-frequency channel of FPGA/DSP and intermediate-frequency channel facilities and this result is set is current calculation flag, 4. produce count pulse to counter, 5. the gated sweep controller starts scanning;
F, scanning monitor produce synchronizing signal, and radio-frequency channel, intermediate-frequency channel, analog to digital converter and FPGA/DSP start linkage work;
The signal of g, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, interrupt control unit judges according to the amplitude of rectified signal;
Within if the rectified signal amplitude of h radio-frequency channel, intermediate-frequency channel is in respectively interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range simultaneously, interrupt control unit does not produce interrupt signal, current Frequency point is measured and is completed, when the next pulse signal of waiting timer arrives, forward step e to, start to carry out the measurement of next Frequency point;
Within if the rectified signal amplitude of i radio-frequency channel is in outside the default radio-frequency channel amplitude range of interrupt control unit and the rectified signal amplitude of intermediate-frequency channel is in the default intermediate-frequency channel amplitude range of interrupt control unit, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier state of radio-frequency channel; Within if the rectified signal amplitude of intermediate-frequency channel is in outside the default intermediate-frequency channel amplitude range of interrupt control unit and the rectified signal amplitude of radio-frequency channel is in the default radio-frequency channel amplitude range of interrupt control unit, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier state of intermediate-frequency channel; If the rectified signal amplitude of radio-frequency channel, intermediate-frequency channel is in respectively outside interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range simultaneously, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier state of radio-frequency channel; When the next pulse signal of waiting timer arrives, passage output level controller carries out following operation and 1. interrupt control unit is carried out to reset operation, 2. notify FPGA/DSP current radio-frequency channel facilities and intermediate-frequency channel facilities, and this result of calculation is set is calculation flag again, 3. the gated sweep controller starts scanning;
J, scanning monitor produce synchronizing signal, radio-frequency channel, intermediate-frequency channel, analog to digital converter and beginning linkage work; This calculation process result of FPGA/DSP covers calculation process result last time;
The signal of k, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, interrupt control unit rejudges according to the amplitude of rectified signal;
Within if the rectified signal amplitude of l radio-frequency channel, intermediate-frequency channel is in respectively interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range simultaneously, interrupt control unit does not produce interrupt signal, current Frequency point is measured and is completed, when the next pulse signal of waiting timer arrives, forward step e to, start to carry out the measurement of next Frequency point;
If the rectified signal range value of m radio-frequency channel and/or intermediate-frequency channel still is in outside interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range, repeated execution of steps i is to step l, until within the rectified signal amplitude of radio-frequency channel, intermediate-frequency channel is in respectively the default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range of interrupt control unit simultaneously, current Frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start to carry out the measurement of next Frequency point;
N, when the count value of counter equates with the pre-set count values of CPU, counter produce to interrupt, and shows that current measurement point be last measurement point, repeated execution of steps e arrives step m;
O, passage output level controller produce end interrupt and notify CPU, and this scanning process finishes;
P, CPU carry out display operation to the result that FPGA/DSP processes.
Certainly; above explanation is only preferred embodiment of the present invention; the present invention is not limited to enumerate above-described embodiment; should be noted that; any those of ordinary skill in the art are under the instruction of this specification; that makes allly is equal to alternative, obvious variant, within all dropping on the essential scope of this specification, ought to be subject to protection of the present invention.
Claims (5)
1. the automatic regulating system of superheterodyne reception analytical instrument passage output level, comprise radio-frequency channel, intermediate-frequency channel, analog to digital converter, FPGA/DSP, scanning monitor and CPU, characterized by further comprising:
Timer, for the pulse signal of the parameter generating constant duration according to the CPU setting;
Passage output level controller, for responding the control command that CPU sends, for generation of end interrupt and send to CPU, for attenuator and the amplifier of radio-frequency channel and intermediate-frequency channel are controlled, for the scanning time started of the pulse signal gated sweep controller that scanning monitor carried out to the parameter setting and produce according to timer, be used to FPGA/DSP that current radio-frequency channel and intermediate-frequency channel facilities are provided and arrange this result be whether current/recalculate sign;
Counter, for the count pulse that passage output level controller is produced, count, when count value equates with the pre-set count values of CPU, counter produces interrupt signal and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response count device produces;
Coupler, for the output that will be coupled through the signal of radio-frequency channel and intermediate-frequency channel output;
Power detecting unit, for amplifying and detection through the signal of coupler coupling output;
Interrupt control unit, for the signal after the power detecting unit detection is detected, if the detection signal range value does not meet the default amplitude range of CPU, interrupt control unit produces interrupt signal, and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response interrupt control unit produces is also carried out the interruptions reason, and the passage output level is carried out the interruption reset condition operation to interrupt control unit.
2. the automatic regulating system of superheterodyne reception analytical instrument passage output level according to claim 1, it is characterized in that, described radio-frequency channel, for input signal is decayed, amplification, filtering and mixing operation, the attenuator in radio-frequency channel and amplifier are for regulating the passage output level;
Intermediate-frequency channel, carry out channel selecting, channel compensation, decay, amplification, filtering and mixing operation for the signal to radio-frequency channel output, and the attenuator of intermediate-frequency channel and amplifier can be used for regulating the passage output level;
Analog to digital converter be digital signal for the analog signal conversion that will export through intermediate-frequency channel;
FPGA/DSP, be used to receiving the digital signal of analog converter output, and process and analysis operation digital signal;
Scanning monitor, for generation of various synchronizing signals, make the mixing local oscillator in radio-frequency channel, compensating circuit, analog to digital converter, the FPGA/DSP synchronous operation in intermediate-frequency channel;
CPU, for passage output level controller is carried out to the initial condition setting, for timer is carried out reset operation and according to scanning mode, timer carried out to the parameter setting, for counter being carried out to reset operation and according to scanning mode, counter being carried out to the parameter setting.
3. the automatic regulating system of superheterodyne reception analytical instrument passage output level according to claim 1, is characterized in that, described timer, counter, interrupt control unit and passage output level controller are positioned at FPGA/DSP inside.
4. the automatic regulating system of superheterodyne reception analytical instrument passage output level according to claim 1, is characterized in that, described passage output level controller comprises:
Data register, the data that produce be used to storing CPU, comprise scan-data and control data;
Interrupt register, the interruption produced be used to storing interrupt control unit;
The channel status register, be sent to the state of FPGA/DSP/sign for storage;
Interruption processing module, for producing scanning impulse, count pulse, reset signal, end interrupt signal and state/flag data according to commutator pulse, control data, interrupt signal and built-in interruption processing rule;
Sweep parameter arranges module, according to scan-data and scanning pulse signal gated sweep counter;
The radio-frequency channel control module, control radio-frequency channel according to the radio-frequency channel status data in the channel status register;
The intermediate-frequency channel control module, control intermediate-frequency channel according to the intermediate-frequency channel status data in the channel status register.
5. the Automatic adjustment method of superheterodyne reception classifying apparatus passage output level, is characterized in that comprising the steps:
A, CPU carry out the initial condition setting to passage output level controller;
B, passage output level controller arrange scanning monitor according to the parameter that CPU arranges;
C, CPU carry out reset operation and counter are arranged counter;
D, CPU carry out reset operation and timer are carried out to the parameter setting timer, and timer starts to produce the pulse signal of constant duration according to parameters;
E, passage output level controller are carried out following operation after receiving the pulse signal that timer produces: 1. interrupt control unit is carried out to reset operation, 2. attenuator, the amplifier of radio-frequency channel and intermediate-frequency channel are pre-seted, whether 3. notify the current radio-frequency channel of FPGA/DSP and intermediate-frequency channel facilities and this result is set is current calculation flag, 4. produce count pulse to counter, 5. the gated sweep controller starts scanning;
F, scanning monitor produce synchronizing signal, and radio-frequency channel, intermediate-frequency channel, analog to digital converter and FPGA/DSP start linkage work;
The signal of g, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, interrupt control unit judges according to the amplitude of rectified signal;
Within if the rectified signal amplitude of h radio-frequency channel, intermediate-frequency channel is in respectively interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range simultaneously, interrupt control unit does not produce interrupt signal, current Frequency point is measured and is completed, when the next pulse signal of waiting timer arrives, forward step e to, start to carry out the measurement of next Frequency point;
Within if the rectified signal amplitude of i radio-frequency channel is in outside the default radio-frequency channel amplitude range of interrupt control unit and the rectified signal amplitude of intermediate-frequency channel is in the default intermediate-frequency channel amplitude range of interrupt control unit, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier state of radio-frequency channel; Within if the rectified signal amplitude of intermediate-frequency channel is in outside the default intermediate-frequency channel amplitude range of interrupt control unit and the rectified signal amplitude of radio-frequency channel is in the default radio-frequency channel amplitude range of interrupt control unit, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier state of intermediate-frequency channel; If the rectified signal amplitude of radio-frequency channel, intermediate-frequency channel is in respectively outside interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range simultaneously, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier state of radio-frequency channel; When the next pulse signal of waiting timer arrives, passage output level controller carries out following operation and 1. interrupt control unit is carried out to reset operation, 2. notify FPGA/DSP current radio-frequency channel facilities and intermediate-frequency channel facilities, and this result of calculation is set is calculation flag again, 3. the gated sweep controller starts scanning;
J, scanning monitor produce synchronizing signal, radio-frequency channel, intermediate-frequency channel, analog to digital converter and beginning linkage work; This calculation process result of FPGA/DSP covers calculation process result last time;
The signal of k, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, interrupt control unit rejudges according to the amplitude of rectified signal;
Within if the rectified signal amplitude of l radio-frequency channel, intermediate-frequency channel is in respectively interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range simultaneously, interrupt control unit does not produce interrupt signal, current Frequency point is measured and is completed, when the next pulse signal of waiting timer arrives, forward step e to, start to carry out the measurement of next Frequency point;
If the rectified signal range value of m radio-frequency channel and/or intermediate-frequency channel still is in outside interrupt control unit default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range, repeated execution of steps i is to step l, until within the rectified signal amplitude of radio-frequency channel, intermediate-frequency channel is in respectively the default radio-frequency channel amplitude range and intermediate-frequency channel amplitude range of interrupt control unit simultaneously, current Frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start to carry out the measurement of next Frequency point;
N, when the count value of counter equates with the pre-set count values of CPU, counter produce to interrupt, and shows that current measurement point be last measurement point, repeated execution of steps e arrives step m;
O, passage output level controller produce end interrupt and notify CPU, and this scanning process finishes;
P, CPU carry out display operation to the result that FPGA/DSP processes.
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