CN103414525B - System and method for automatically adjusting channel output level of superheterodyne receiving analytical instrument - Google Patents
System and method for automatically adjusting channel output level of superheterodyne receiving analytical instrument Download PDFInfo
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Abstract
The invention discloses a system and method for automatically adjusting channel output level of a superheterodyne receiving analytical instrument. The system for automatically adjusting the channel output level of the superheterodyne receiving analytical instrument comprises a radio frequency channel, a medium frequency channel, an analog-to-digital converter, an FPGA/DSP, a scanning controller, a CPU, a timer, a channel output level controller, a counter, a coupler, a power detection unit and an interrupt controller. Compared with the prior art, due to the fact that the channel output level controller is used in cooperation with the coupler, the power detection unit, the timer, the counter and the interrupt controller to achieve the function of automatic control over the channel output level in the process of scanning, the purpose of protecting the superheterodyne receiving analytical instrument and the purpose of improving signal measurement accuracy are achieved. In addition, the number of times of interference of the CPU to the scanning process is greatly reduced, the measuring time is reduced, and smoothness of integral operation of the superheterodyne receiving analytical instrument is improved.
Description
Technical field
The present invention relates to a kind of automatic regulating system of superheterodyne reception analytical instrument passage output level and the Automatic adjustment method of passage output level.
Background technology
When using superheterodyne reception analytical instrument to measure unknown electromagnetic environment, some high-power signals may be there are in unknown electromagnetic environment, these high-power signals the lighter affects the nonlinear device in superheterodyne reception analytical instrument, cause measurement inaccurate, severe one can damage those power easily worn parts, causes equipment fault.How control channel output level is to protect superheterodyne reception analytical instrument and the certainty of measurement improving high-power signal becomes the important topic of research.
When carrying out unknown signaling and measuring; superheterodyne reception analytical instrument should be able to change path gain automatically according to the watt level of measured signal: if measured signal is low-power level signal; superheterodyne reception analytical instrument should be able to provide maximum path gain to improve receiving sensitivity; if measured signal is high-power signal, superheterodyne reception analytical instrument should reduce path gain to improve certainty of measurement and to protect those power easily worn parts.
Current superheterodyne reception analytical instrument adopts following three kinds of methods to regulate passage output level usually.First method is manually arranged by user, and user, by arranging amplifier and the attenuator of superheterodyne reception analytical instrument front radio-frequency path and intermediate-frequency channel, manually changes the output level of passage; Second method is the change that superheterodyne reception analytical instrument mainframe program participates in channel gain, before each Frequency point carries out power measurement, first mainframe program carries out, and then arranges attenuator and amplifier etc. according to premeasuring result, finally formally measures.The third mode increases automatic gain control circuit in the intermediate-frequency channel of superheterodyne reception analytical instrument, before each Frequency point carries out power measurement, mainframe program or FPGA adjust intermediate-frequency channel gain, make the signal power substantially constant entering digital to analog converter.
But there is following technical deficiency in above-mentioned three kinds of passage output level control methods:
(1) shortcoming that the method adopting user manually to arrange changes passage output level is that control rate is slow, which need to judge superheterodyne reception analytical instrument overburden portion, require that operating personnel have more rich experience, when carrying out the measurement of multiple Frequency point, workload is large;
(2) shortcoming adopting mainframe program to participate in the change of channel gain is that mainframe program needs to participate in the hardware controls such as channel power detection, attenuator and amplifier on each measuring frequency point, sweep parameter is arranged, digital to analog converter adopts and controls, thus considerably increase the control time, slowed down measuring speed, in addition, the occupancy of CPU is high, can have influence on the process such as data processing, display refreshing, slowed down measuring speed further;
(3) shortcoming adopting IF AGC method to change passage output level is that automatic gain method can not control radio-frequency channel gain and not participate in the scanning sequence control of complete machine, and sphere of action is limited.
Fig. 1 shows the control flow chart that mainframe program participates in the change of passage output level.As shown in Figure 1, general superheterodyne reception analytical instrument radio frequency and the regulating system of intermediate-frequency channel output level, comprise radio-frequency channel, intermediate-frequency channel, analog to digital converter, FPGA/DSP, scanning monitor and CPU.
Wherein, the functions such as the decay of the general settling signal in radio-frequency channel, amplification, filtering and mixing, the attenuator in radio-frequency channel and amplifier can be used for regulating passage output level.
The functions such as the general settling signal channel selecting of intermediate-frequency channel, channel compensation, decay, amplification, filtering and mixing, the attenuator of intermediate-frequency channel and amplifier can be used for regulating passage output level.
Analog to digital converter completes the translation function of analog signal to digital signal.
FPGA/DSP completes various Digital Signal Processing and analytic function.
Scanning monitor produces various synchronizing signal, makes the mixing local oscillator in radio-frequency channel, the compensating circuit in intermediate-frequency channel, analog to digital converter, FPGA/DSP synchronous operation.
CPU is responsible for arranging scanning monitor controling parameters, arranges radio-frequency channel and intermediate-frequency channel attenuator, amplifier and filter status, response user command and to the process of FPGA/DSP operation result and display.
General superheterodyne reception analytical instrument radio frequency and the control method of intermediate-frequency channel output level comprise:
(1) state that arranges according to user of CPU or the initial setting up state radio frequency of program acquiescence and the attenuator, amplifier etc. of intermediate-frequency channel pre-set;
(2) CPU arranges scanning monitor parameter, and gated sweep controller starts scanning;
(3) scanning monitor produces synchronizing signal, acts on radio-frequency channel, intermediate-frequency channel, analog to digital converter and FPGA/DSP respectively, makes each several part start linkage work;
(4) signal amplitude of CPU to FPGA/DSP process is analyzed, if signal amplitude does not meet the amplitude range of procedure stipulation, so CPU controls according to the rule set in program attenuator, amplifier, changes the output level of passage;
(5) step (2) is repeated to step (4), until the amplitude range that the signal amplitude measured conforms with the regulations;
(6) the signal measurement result that reality is final;
(7) CPU carries out the measurement of next Frequency point, repeats step (1) to step (6).
By finding with the control method of upper channel output level, CPU needs to participate in scanning process at any time, thus greatly have impact on sweep speed.Based on this, passage output level control method of the prior art requires further improvement.
Summary of the invention
Based on above-mentioned technical problem, the present invention proposes a kind of automatic regulating system of superheterodyne reception analytical instrument passage output level, it adopts following technical scheme:
The automatic regulating system of superheterodyne reception analytical instrument passage output level, comprises radio-frequency channel, intermediate-frequency channel, analog to digital converter, FPGA/DSP, scanning monitor and CPU, also comprises:
Timer, the parameter for arranging according to CPU produces the pulse signal of constant duration;
Passage output level controller, for responding the control command that CPU sends, CPU is sent to for generation of end interrupt, control for the attenuator of radio frequency passage and intermediate-frequency channel and amplifier, for carrying out optimum configurations to scanning monitor and the scanning time started of pulse signal gated sweep controller produced according to timer, for current radio frequency passage and intermediate-frequency channel facilities are provided for FPGA/DSP and arrange this result be whether current/recalculate mark;
Counter, count pulse for producing passage output level controller counts, when count value is equal with the pre-set count values of CPU, counter produces interrupt signal and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response count device produces;
Coupler, for carrying out coupling output by the signal exported through radio-frequency channel and intermediate-frequency channel;
Power detecting unit, for being undertaken amplifying and detection by the signal through coupler coupling output;
Interrupt control unit, for detecting the signal after power detecting unit detection, if detection signal range value does not meet the predetermined amplitude scope of CPU, interrupt control unit produces interrupt signal, and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response interrupt control unit produces also carries out interrupt processing, and passage output level performs interruption reset condition operation to interrupt control unit.
In the automatic regulating system of above-mentioned superheterodyne reception analytical instrument passage output level,
Radio-frequency channel, for decaying to input signal, amplifying, filtering and mixing operation, the attenuator in radio-frequency channel and amplifier are for regulating passage output level;
Intermediate-frequency channel, the signal exported for radio frequency passage carries out channel selecting, channel compensation, decay, amplification, filtering and mixing operation, and the attenuator of intermediate-frequency channel and amplifier can be used for regulating passage output level;
Analog to digital converter, for being converted to digital signal by the analog signal exported through intermediate-frequency channel;
FPGA/DSP, for receiving the digital signal that analog converter exports, and processes and analysis operation digital signal;
Scanning monitor, for generation of various synchronizing signal, makes the mixing local oscillator in radio-frequency channel, the compensating circuit in intermediate-frequency channel, analog to digital converter, FPGA/DSP synchronous operation;
CPU, for carrying out initial condition setting to passage output level controller, for carrying out reset operation to timer and carrying out optimum configurations according to scanning mode to timer, for carrying out reset operation to counter and carrying out optimum configurations according to scanning mode to counter.
In the automatic regulating system of above-mentioned superheterodyne reception analytical instrument passage output level, timer, counter, interrupt control unit and passage output level controller are positioned at FPGA/DSP inside.
In the automatic regulating system of above-mentioned superheterodyne reception analytical instrument passage output level, passage output level controller comprises: data register, for storing the data that CPU produces, comprises scan-data and control data; Interrupt register, for storing the interruption that interrupt control unit produces; Channel status register, for storing the state/mark being sent to FPGA/DSP; Interruption processing module, for producing scanning impulse, count pulse, reset signal, end interrupt signal and state/flag data according to commutator pulse, control data, interrupt signal and built-in interrupt processing rule; Sweep parameter arranges module, according to scan-data and scanning pulse signal gated sweep counter; Radio-frequency channel control module, controls according to the radio-frequency channel status data radio frequency passage in channel status register; Intermediate-frequency channel control module, controls intermediate-frequency channel according to the intermediate-frequency channel status data in channel status register.
Another object of the present invention is the Automatic adjustment method proposing a kind of superheterodyne reception analytical instrument passage output level, and it comprises following job step:
A, CPU carry out initial condition setting to passage output level controller;
The parameter that b, passage output level controller are arranged according to CPU is arranged scanning monitor;
C, CPU carry out reset operation to counter and arrange counter;
D, CPU carry out reset operation to timer and carry out optimum configurations to timer, and timer starts according to parameters the pulse signal producing constant duration;
Following operation is performed: 1. reset operation is carried out to interrupt control unit after e, passage output level controller receive the pulse signal of timer generation, 2. the attenuator of radio frequency passage and intermediate-frequency channel, amplifier pre-set, whether 3. notify FPGA/DSP current radio frequency passage and intermediate-frequency channel facilities and arrange this result is current calculation flag, 4. produce count pulse to counter, 5. gated sweep controller starts scanning;
F, scanning monitor produce synchronizing signal, and radio-frequency channel, intermediate-frequency channel, analog to digital converter and FPGA/DSP start linkage work;
The signal of g, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, and interrupt control unit judges according to the amplitude of rectified signal;
If the detected signal amplitude of h radio-frequency channel, intermediate-frequency channel is within the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range respectively simultaneously, interrupt control unit does not produce interrupt signal, ongoing frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start the measurement carrying out next Frequency point;
If the detected signal amplitude of i radio-frequency channel is in outside radio-frequency channel amplitude range that interrupt control unit presets and the detected signal amplitude of intermediate-frequency channel is within the intermediate-frequency channel amplitude range that interrupt control unit presets, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier status of radio-frequency channel; If the detected signal amplitude of intermediate-frequency channel is in outside intermediate-frequency channel amplitude range that interrupt control unit presets and the detected signal amplitude of radio-frequency channel is within the radio-frequency channel amplitude range that interrupt control unit presets, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier status of intermediate-frequency channel; If the detected signal amplitude of radio-frequency channel, intermediate-frequency channel is in outside the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range respectively simultaneously, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier status of radio-frequency channel; When the next pulse signal of waiting timer arrives, passage output level controller carries out following operation and 1. carries out reset operation to interrupt control unit, 2. FPGA/DSP current radio frequency channel setting situation and intermediate-frequency channel facilities is notified, and this result of calculation is set for calculation flag again, 3. gated sweep controller starts scanning;
J, scanning monitor produce synchronizing signal, radio-frequency channel, intermediate-frequency channel, analog to digital converter and beginning linkage work; This calculation process result of FPGA/DSP covers calculation process result last time;
The signal of k, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, and interrupt control unit rejudges according to the amplitude of rectified signal;
If the detected signal amplitude of l radio-frequency channel, intermediate-frequency channel is within the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range respectively simultaneously, interrupt control unit does not produce interrupt signal, ongoing frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start the measurement carrying out next Frequency point;
If the detected signal amplitude value of m radio-frequency channel and/or intermediate-frequency channel is still in outside the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range, repeated execution of steps i is to step l, until within the detected signal amplitude of radio-frequency channel, the intermediate-frequency channel default radio-frequency channel amplitude range that is in interrupt control unit respectively and intermediate-frequency channel amplitude range simultaneously, present frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start the measurement carrying out next Frequency point;
N, when the count value of counter is equal with the pre-set count values of CPU, counter produce interrupt, show that current measurement point is last measurement point, repeated execution of steps e is to step m;
O, passage output level controller produce end interrupt and notify CPU, and present scan process terminates;
P, CPU carry out display operation to the result of FPGA/DSP process.
Advantage of the present invention is:
Compared with prior art, the present invention uses channel levels o controller and in conjunction with coupler, power detecting unit, timer, counter and interrupt control unit complete the automatic control function of passage output level in scanning process, thus reach the object of protection superheterodyne reception analytical instrument and raising signal measurement precision, in addition, present invention substantially reduces the intervention number of times of CPU to scan procedure, decrease Measuring Time, channel levels o controller alleviates the workload of CPU to a great extent, CPU can carry out algorithm calculating, the work such as display refreshing and man-machine interaction, improve the fluency of superheterodyne reception analytical instrument overall operation.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the automatic regulating system of prior art superheterodyne reception analytical instrument passage output level;
Fig. 2 is the structured flowchart of the automatic regulating system of superheterodyne reception analytical instrument passage output level of the present invention;
Fig. 3 is the cut-away view of passage output level controller in the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is described in further detail:
Shown in composition graphs 2, the automatic regulating system of superheterodyne reception analytical instrument passage output level, comprises radio-frequency channel, intermediate-frequency channel, analog to digital converter, FPGA/DSP, scanning monitor, CPU, timer, passage output level controller, counter, coupler, power detecting unit and interrupt control unit.
Radio-frequency channel, for decaying to input signal, amplifying, filtering and mixing operation, the attenuator in radio-frequency channel and amplifier are for regulating passage output level.
Intermediate-frequency channel, the signal exported for radio frequency passage carries out channel selecting, channel compensation, decay, amplification, filtering and mixing operation, and the attenuator of intermediate-frequency channel and amplifier can be used for regulating passage output level.
Analog to digital converter, for being converted to digital signal by the analog signal exported through intermediate-frequency channel.
FPGA/DSP, for receiving the digital signal that analog converter exports, and processes and analysis operation digital signal.
Scanning monitor, for generation of various synchronizing signal, makes the mixing local oscillator in radio-frequency channel, the compensating circuit in intermediate-frequency channel, analog to digital converter, FPGA/DSP synchronous operation.
CPU, for carrying out initial condition setting to passage output level controller, for carrying out reset operation to timer and carrying out optimum configurations according to scanning mode to timer, for carrying out reset operation to counter and carrying out optimum configurations according to scanning mode to counter.
Timer, the parameter for arranging according to CPU produces the pulse signal of constant duration.
Passage output level controller, for responding the control command that CPU sends, CPU is sent to for generation of end interrupt, control for the attenuator of radio frequency passage and intermediate-frequency channel and amplifier, for carrying out optimum configurations to scanning monitor and the scanning time started of pulse signal gated sweep controller produced according to timer, for current radio frequency passage and intermediate-frequency channel facilities are provided for FPGA/DSP and arrange this result be whether current/recalculate mark.
Counter, count pulse for producing passage output level controller counts, when count value is equal with the pre-set count values of CPU, counter produces interrupt signal and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response count device produces.
Coupler, for carrying out coupling output by the signal exported through radio-frequency channel and intermediate-frequency channel.
Power detecting unit, for being undertaken amplifying and detection by the signal through coupler coupling output.
Interrupt control unit, for detecting the signal after power detecting unit detection, if detection signal range value does not meet the predetermined amplitude scope of CPU, interrupt control unit produces interrupt signal, and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response interrupt control unit produces also carries out interrupt processing, and passage output level performs interruption reset condition operation to interrupt control unit.
In actual use, preferably timer, counter, interrupt control unit and passage output level controller are all incorporated into a FPGA/DSP inside.
Shown in composition graphs 3, passage output level controller comprises:
Data register, for storing the data that CPU produces, comprises scan-data and control data;
Interrupt register, for storing the interruption that interrupt control unit produces;
Channel status register, for storing the state/mark being sent to FPGA/DSP;
Interruption processing module, for producing scanning impulse, count pulse, reset signal, end interrupt signal and state/flag data according to commutator pulse, control data, interrupt signal and built-in interrupt processing rule;
Sweep parameter arranges module, according to scan-data and scanning pulse signal gated sweep counter;
Radio-frequency channel control module, controls according to the radio-frequency channel status data radio frequency passage in channel status register;
Intermediate-frequency channel control module, controls intermediate-frequency channel according to the intermediate-frequency channel status data in channel status register.
The Automatic adjustment method of superheterodyne reception analytical instrument passage output level is as follows:
A, CPU carry out initial condition setting to passage output level controller;
The parameter that b, passage output level controller are arranged according to CPU is arranged scanning monitor;
C, CPU carry out reset operation to counter and arrange counter;
D, CPU carry out reset operation to timer and carry out optimum configurations to timer, and timer starts according to parameters the pulse signal producing constant duration;
Following operation is performed: 1. reset operation is carried out to interrupt control unit after e, passage output level controller receive the pulse signal of timer generation, 2. the attenuator of radio frequency passage and intermediate-frequency channel, amplifier pre-set, whether 3. notify FPGA/DSP current radio frequency passage and intermediate-frequency channel facilities and arrange this result is current calculation flag, 4. produce count pulse to counter, 5. gated sweep controller starts scanning;
F, scanning monitor produce synchronizing signal, and radio-frequency channel, intermediate-frequency channel, analog to digital converter and FPGA/DSP start linkage work;
The signal of g, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, and interrupt control unit judges according to the amplitude of rectified signal;
If the detected signal amplitude of h radio-frequency channel, intermediate-frequency channel is within the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range respectively simultaneously, interrupt control unit does not produce interrupt signal, ongoing frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start the measurement carrying out next Frequency point;
If the detected signal amplitude of i radio-frequency channel is in outside radio-frequency channel amplitude range that interrupt control unit presets and the detected signal amplitude of intermediate-frequency channel is within the intermediate-frequency channel amplitude range that interrupt control unit presets, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier status of radio-frequency channel; If the detected signal amplitude of intermediate-frequency channel is in outside intermediate-frequency channel amplitude range that interrupt control unit presets and the detected signal amplitude of radio-frequency channel is within the radio-frequency channel amplitude range that interrupt control unit presets, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier status of intermediate-frequency channel; If the detected signal amplitude of radio-frequency channel, intermediate-frequency channel is in outside the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range respectively simultaneously, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier status of radio-frequency channel; When the next pulse signal of waiting timer arrives, passage output level controller carries out following operation and 1. carries out reset operation to interrupt control unit, 2. FPGA/DSP current radio frequency channel setting situation and intermediate-frequency channel facilities is notified, and this result of calculation is set for calculation flag again, 3. gated sweep controller starts scanning;
J, scanning monitor produce synchronizing signal, radio-frequency channel, intermediate-frequency channel, analog to digital converter and beginning linkage work; This calculation process result of FPGA/DSP covers calculation process result last time;
The signal of k, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, and interrupt control unit rejudges according to the amplitude of rectified signal;
If the detected signal amplitude of l radio-frequency channel, intermediate-frequency channel is within the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range respectively simultaneously, interrupt control unit does not produce interrupt signal, ongoing frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start the measurement carrying out next Frequency point;
If the detected signal amplitude value of m radio-frequency channel and/or intermediate-frequency channel is still in outside the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range, repeated execution of steps i is to step l, until within the detected signal amplitude of radio-frequency channel, the intermediate-frequency channel default radio-frequency channel amplitude range that is in interrupt control unit respectively and intermediate-frequency channel amplitude range simultaneously, present frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start the measurement carrying out next Frequency point;
N, when the count value of counter is equal with the pre-set count values of CPU, counter produce interrupt, show that current measurement point is last measurement point, repeated execution of steps e is to step m;
O, passage output level controller produce end interrupt and notify CPU, and present scan process terminates;
P, CPU carry out display operation to the result of FPGA/DSP process.
Certainly; more than illustrate and be only preferred embodiment of the present invention; the present invention is not limited to enumerate above-described embodiment; should be noted that; any those of ordinary skill in the art are under the instruction of this specification; made all equivalently to substitute, obvious variant, within the essential scope all dropping on this specification, protection of the present invention ought to be subject to.
Claims (3)
1. the automatic regulating system of superheterodyne reception analytical instrument passage output level, comprises radio-frequency channel, intermediate-frequency channel, analog to digital converter, FPGA/DSP, scanning monitor and CPU, characterized by further comprising:
Timer, the parameter for arranging according to CPU produces the pulse signal of constant duration;
Passage output level controller, for responding the control command that CPU sends, CPU is sent to for generation of end interrupt, control for the attenuator of radio frequency passage and intermediate-frequency channel and amplifier, for carrying out optimum configurations to scanning monitor and the scanning time started of pulse signal gated sweep controller produced according to timer, for current radio frequency passage and intermediate-frequency channel facilities are provided for FPGA/DSP and arrange this result be whether current/recalculate mark;
Counter, count pulse for producing passage output level controller counts, when count value is equal with the pre-set count values of CPU, counter produces interrupt signal and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response count device produces;
Coupler, for carrying out coupling output by the signal exported through radio-frequency channel and intermediate-frequency channel;
Power detecting unit, for being undertaken amplifying and detection by the signal through coupler coupling output;
Interrupt control unit, for detecting the signal after power detecting unit detection, if detection signal range value does not meet the predetermined amplitude scope of CPU, interrupt control unit produces interrupt signal, and this interrupt signal is sent to passage output level controller, the interruption that passage output level controller response interrupt control unit produces also carries out interrupt processing, and passage output level performs interruption reset condition operation to interrupt control unit;
Described radio-frequency channel, for decaying to input signal, amplifying, filtering and mixing operation, the attenuator in radio-frequency channel and amplifier are for regulating passage output level;
Intermediate-frequency channel, the signal exported for radio frequency passage carries out channel selecting, channel compensation, decay, amplification, filtering and mixing operation, and the attenuator of intermediate-frequency channel and amplifier can be used for regulating passage output level;
Analog to digital converter, for being converted to digital signal by the analog signal exported through intermediate-frequency channel;
FPGA/DSP, for receiving the digital signal that analog converter exports, and processes and analysis operation digital signal;
Scanning monitor, for generation of various synchronizing signal, makes the mixing local oscillator in radio-frequency channel, the compensating circuit in intermediate-frequency channel, analog to digital converter, FPGA/DSP synchronous operation;
CPU, for carrying out initial condition setting to passage output level controller, for carrying out reset operation to timer and carrying out optimum configurations according to scanning mode to timer, for carrying out reset operation to counter and carrying out optimum configurations according to scanning mode to counter;
Described passage output level controller comprises:
Data register, for storing the data that CPU produces, comprises scan-data and control data;
Interrupt register, for storing the interruption that interrupt control unit produces;
Channel status register, for storing the state/mark being sent to FPGA/DSP;
Interruption processing module, for producing scanning impulse, count pulse, reset signal, end interrupt signal and state/flag data according to commutator pulse, control data, interrupt signal and built-in interrupt processing rule;
Sweep parameter arranges module, according to scan-data and scanning pulse signal gated sweep counter;
Radio-frequency channel control module, controls according to the radio-frequency channel status data radio frequency passage in channel status register; Intermediate-frequency channel control module, controls intermediate-frequency channel according to the intermediate-frequency channel status data in channel status register.
2. the automatic regulating system of superheterodyne reception analytical instrument passage output level according to claim 1, is characterized in that, described timer, counter, interrupt control unit and passage output level controller are positioned at FPGA/DSP inside.
3. the Automatic adjustment method of superheterodyne reception classifying apparatus passage output level, is characterized in that comprising the steps:
A, CPU carry out initial condition setting to passage output level controller;
The parameter that b, passage output level controller are arranged according to CPU is arranged scanning monitor;
C, CPU carry out reset operation to counter and arrange counter;
D, CPU carry out reset operation to timer and carry out optimum configurations to timer, and timer starts according to parameters the pulse signal producing constant duration;
Following operation is performed: 1. reset operation is carried out to interrupt control unit after e, passage output level controller receive the pulse signal of timer generation, 2. the attenuator of radio frequency passage and intermediate-frequency channel, amplifier pre-set, whether 3. notify FPGA/DSP current radio frequency passage and intermediate-frequency channel facilities and arrange this result is current calculation flag, 4. produce count pulse to counter, 5. gated sweep controller starts scanning;
F, scanning monitor produce synchronizing signal, and radio-frequency channel, intermediate-frequency channel, analog to digital converter and FPGA/DSP start linkage work;
The signal of g, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, and interrupt control unit judges according to the amplitude of rectified signal;
If the detected signal amplitude of h radio-frequency channel, intermediate-frequency channel is within the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range respectively simultaneously, interrupt control unit does not produce interrupt signal, ongoing frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start the measurement carrying out next Frequency point;
If the detected signal amplitude of i radio-frequency channel is in outside radio-frequency channel amplitude range that interrupt control unit presets and the detected signal amplitude of intermediate-frequency channel is within the intermediate-frequency channel amplitude range that interrupt control unit presets, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier status of radio-frequency channel; If the detected signal amplitude of intermediate-frequency channel is in outside intermediate-frequency channel amplitude range that interrupt control unit presets and the detected signal amplitude of radio-frequency channel is within the radio-frequency channel amplitude range that interrupt control unit presets, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier status of intermediate-frequency channel; If the detected signal amplitude of radio-frequency channel, intermediate-frequency channel is in outside the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range respectively simultaneously, interrupt control unit produces interrupt signal, and passage output level controller resets attenuator, the amplifier status of radio-frequency channel; When the next pulse signal of waiting timer arrives, passage output level controller carries out following operation and 1. carries out reset operation to interrupt control unit, 2. FPGA/DSP current radio frequency channel setting situation and intermediate-frequency channel facilities is notified, and this result of calculation is set for calculation flag again, 3. gated sweep controller starts scanning;
J, scanning monitor produce synchronizing signal, radio-frequency channel, intermediate-frequency channel, analog to digital converter and beginning linkage work; This calculation process result of FPGA/DSP covers calculation process result last time;
The signal of k, radio-frequency channel and intermediate-frequency channel becomes rectified signal and sends into interrupt control unit after coupler and power detecting unit, and interrupt control unit rejudges according to the amplitude of rectified signal;
If the detected signal amplitude of l radio-frequency channel, intermediate-frequency channel is within the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range respectively simultaneously, interrupt control unit does not produce interrupt signal, ongoing frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start the measurement carrying out next Frequency point;
If the detected signal amplitude value of m radio-frequency channel and/or intermediate-frequency channel is still in outside the default radio-frequency channel amplitude range of interrupt control unit and intermediate-frequency channel amplitude range, repeated execution of steps i is to step l, until within the detected signal amplitude of radio-frequency channel, the intermediate-frequency channel default radio-frequency channel amplitude range that is in interrupt control unit respectively and intermediate-frequency channel amplitude range simultaneously, present frequency point measurement completes, when the next pulse signal of waiting timer arrives, forward step e to, start the measurement carrying out next Frequency point;
N, when the count value of counter is equal with the pre-set count values of CPU, counter produce interrupt, show that current measurement point is last measurement point, repeated execution of steps e is to step m;
O, passage output level controller produce end interrupt and notify CPU, and present scan process terminates;
P, CPU carry out display operation to the result of FPGA/DSP process.
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| CN115882801A (en) * | 2021-09-29 | 2023-03-31 | 深圳市中兴微电子技术有限公司 | Automatic gain control device and gain updating timing output method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1063594A2 (en) * | 1999-06-23 | 2000-12-27 | Denso Corporation | An interrupt controller and a microcomputer incorporating this controller |
| CN1690971A (en) * | 2004-04-27 | 2005-11-02 | 松下电器产业株式会社 | Interrupt control apparatus |
| CN201066913Y (en) * | 2007-06-25 | 2008-05-28 | 浙江华立通信集团有限公司 | 3G and 4G terminal dormant mode control device |
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| JP2004056212A (en) * | 2002-07-16 | 2004-02-19 | Nippon Hoso Kyokai <Nhk> | Receiving performance measurement instrument |
| CN201303330Y (en) * | 2008-09-17 | 2009-09-02 | 浙江三维无线科技有限公司 | Ultra high frequency (UHF) radio-frequency power detection device |
| CN102752062B (en) * | 2012-06-20 | 2015-04-29 | 京信通信技术(广州)有限公司 | Method and device for detecting frequency correction channel |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1063594A2 (en) * | 1999-06-23 | 2000-12-27 | Denso Corporation | An interrupt controller and a microcomputer incorporating this controller |
| CN1690971A (en) * | 2004-04-27 | 2005-11-02 | 松下电器产业株式会社 | Interrupt control apparatus |
| CN201066913Y (en) * | 2007-06-25 | 2008-05-28 | 浙江华立通信集团有限公司 | 3G and 4G terminal dormant mode control device |
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Effective date of registration: 20160826 Address after: 266555 No. 98 Xiangjiang Road, Qingdao economic and Technological Development Zone, Shandong Patentee after: China Electronics Technology Instrument and Meter Co., Ltd. Address before: 266555 Qingdao economic and Technological Development Zone, Shandong Xiangjiang Road, No. 98 Patentee before: The 41st Institute of CETC |
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Address after: 266555 No. 98 Xiangjiang Road, Qingdao economic and Technological Development Zone, Shandong Patentee after: CLP kesiyi Technology Co.,Ltd. Address before: 266555 No. 98 Xiangjiang Road, Qingdao economic and Technological Development Zone, Shandong Patentee before: CHINA ELECTRONIC TECHNOLOGY INSTRUMENTS Co.,Ltd. |