CN103413809A - Split gate type flash memory and forming method thereof - Google Patents
Split gate type flash memory and forming method thereof Download PDFInfo
- Publication number
- CN103413809A CN103413809A CN2013103745261A CN201310374526A CN103413809A CN 103413809 A CN103413809 A CN 103413809A CN 2013103745261 A CN2013103745261 A CN 2013103745261A CN 201310374526 A CN201310374526 A CN 201310374526A CN 103413809 A CN103413809 A CN 103413809A
- Authority
- CN
- China
- Prior art keywords
- material layer
- semiconductor substrate
- insulation material
- insulating barrier
- bit unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Provided are a split gate type flash memory and a forming method thereof. The split gate type flash memory comprises a semiconductor substrate and a storage bit unit located on the surface of the semiconductor substrate. The storage bit unit comprises a first isolating layer located on the surface of the semiconductor substrate, a floating gate located on the surface of the first isolating layer, a second isolating layer located on the surface of the floating gate, a control gate located on the surface of the second isolating layer and a side wall structure covering the floating gate and the control gate. The first isolating layer comprises a third isolating layer and a fourth isolating layer, wherein the third isolating layer and the fourth isolating layer are located on the surface of the semiconductor substrate, and the thickness of the third isolating layer is larger than that of the fourth isolating layer. When the storage bit unit is programmed, electrons in the semiconductor substrate are injected into the floating gate through the fourth isolating layer. According to the split gate type flash memory, the data retention performance of the flash memory and the coupling coefficient of the control gate are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of gate-division type flash memory and forming method thereof.
Background technology
Flash memory (Flash Memory) is as a kind of integrated circuit memory devices,, because but it has after high speed, high density micro, outage plurality of advantages such as still can keeping data, be widely used in as in the electronic products such as portable computer, mobile phone, digital music player.Flash memory is as a kind of nonvolatile memory, and its operation principles is by the critical voltage that changes memory cell, to control the switch of gate pole passage, and to reach the purpose of storage data, the data that make to be stored in memory cell can not disappear because of power interruptions.
Usually, according to the difference of the transistor grid structure that forms memory cell, flash memory can be divided into two kinds: stacking gate flash memory and gate-division type flash memory.Because there was the problem of wiping in folded gate flash memory, and gate-division type flash memory has effectively avoided crossing erasure effect, and circuit design is relatively simple.And, compare folded gate flash memory, gate-division type flash memory utilizes the source hot electron to inject and programmes, and has higher programming efficiency.
Publication number is that the Chinese patent literature of CN101465161A discloses a kind of gate-division type flash memory.Described gate-division type flash memory comprises source region, drain region, word line and two storage bit unit, each storage bit unit comprises the first silicon oxide layer that is positioned at semiconductor substrate surface, be positioned at the multi-crystal silicon floating bar on described the first silicon oxide layer surface, be positioned at second silicon oxide layer on described multi-crystal silicon floating bar surface, be positioned at the polysilicon control grid on described the second silicon oxide layer surface, and the monox lateral wall that covers described the first silicon oxide layer, multi-crystal silicon floating bar, the second silicon oxide layer and polysilicon control grid.
In order to guarantee the programming of described gate-division type flash memory, electronics can successfully enter described multi-crystal silicon floating bar, and described the first silicon oxide layer can not be done too thickly.Yet the first thinner silicon oxide layer is easy to cause electronics to run out of in multi-crystal silicon floating bar, a little less than causing the data of flash memory to keep (data retention) ability.
Summary of the invention
What the present invention solved is the poor problem of gate-division type flash memory data holding ability.
For addressing the above problem, the invention provides a kind of gate-division type flash memory, comprise Semiconductor substrate; Be positioned at the storage bit unit of described semiconductor substrate surface; Described storage bit unit comprises the first insulating barrier that is positioned at described semiconductor substrate surface, be positioned at the floating boom of described the first surface of insulating layer, be positioned at second insulating barrier on described floating boom surface, the sidewall structure that is positioned at the control gate of described the second surface of insulating layer and covers described floating boom, control gate; Wherein, described the first insulating barrier comprises the 3rd insulating barrier and the 4th insulating barrier that all is positioned at described semiconductor substrate surface, and the thickness of described the 3rd insulating barrier is greater than the thickness of described the 4th insulating barrier; During to described storage bit unit programming, the electronics in described Semiconductor substrate injects described floating boom via described the 4th insulating barrier.
Optionally, the thickness of described the 3rd insulating barrier is 150 dusts～250 dusts, and the thickness of described the 4th insulating barrier is 80 dusts～120 dusts.
Based on above-mentioned gate-division type flash memory, the present invention also provides a kind of formation method of gate-division type flash memory, and described formation method comprises: Semiconductor substrate is provided; On described Semiconductor substrate, form storage bit unit, wherein, described storage bit unit comprises the first insulating barrier that is positioned at described semiconductor substrate surface at least, be positioned at the floating boom of described the first surface of insulating layer, be positioned at second insulating barrier on described floating boom surface, the sidewall structure that is positioned at the control gate of described the second surface of insulating layer and covers described floating boom, control gate; Wherein, described the first insulating barrier comprises the 3rd insulating barrier and the 4th insulating barrier that all is positioned at described semiconductor substrate surface, and the thickness of described the 3rd insulating barrier is greater than the thickness of described the 4th insulating barrier; During to described storage bit unit programming, the electronics in described Semiconductor substrate injects described floating boom via described the 4th insulating barrier.
Compared with prior art, technical scheme of the present invention has the following advantages:
Gate-division type flash memory provided by the invention comprises the first insulating barrier between Semiconductor substrate and floating boom, and described the first insulating barrier comprises the 3rd insulating barrier and the 4th insulating barrier that all is positioned at described semiconductor substrate surface.The thickness of described the 3rd insulating barrier is greater than the thickness of described the 4th insulating barrier, and electronics reduces from the probability leaked described floating boom, has improved the data holding ability of gate-division type flash memory.And during to described gate-division type flash memory programming, the electronics in described Semiconductor substrate injects described floating boom via described the 4th insulating barrier, and does not need through described the 3rd insulating barrier, can guarantee the normal programming to described gate-division type flash memory.
Further, because the thickness of described the 3rd insulating barrier increases with respect to described the 4th insulating barrier, reduce the electric capacity between described floating boom and described Semiconductor substrate, therefore, improved the coupling coefficient of control gate in the gate-division type flash memory.
The accompanying drawing explanation
Fig. 1～Fig. 9 is the structural representation of forming process of the gate-division type flash memory of the embodiment of the present invention 1;
Figure 10～Figure 23 is the structural representation of forming process of the gate-division type flash memory of the embodiment of the present invention 2.
Embodiment
Just as described in the background art, existing gate-division type flash memory electronics in order to guarantee to programme can successfully enter floating boom, and the first silicon oxide layer be positioned between floating boom and Semiconductor substrate can not do too thickly.Yet the data holding ability of flash memory is relevant with the thickness of described the first silicon oxide layer: described the first silicon oxide layer is thinner, and the data holding ability of flash memory is poorer.
During to described gate-division type flash memory programming, inner transverse electric field and the longitudinal electric field of forming of described gate-division type flash memory.Under the effect of described transverse electric field and longitudinal electric field, the electronics in Semiconductor substrate only enters floating boom through an end of the close word line of described the first silicon oxide layer.Therefore, technical solution of the present invention is constant by the thickness of retaining part the first silicon oxide layer, and while guaranteeing programming, electronics successfully injects floating boom; By increasing the thickness of part the first silicon oxide layer, improve the data holding ability of gate-division type flash memory.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Technical solution of the present invention provides a kind of gate-division type flash memory, and described gate-division type flash memory comprises: Semiconductor substrate; Be positioned at the storage bit unit of described semiconductor substrate surface; Described storage bit unit comprises the first insulating barrier that is positioned at described semiconductor substrate surface, be positioned at the floating boom of described the first surface of insulating layer, be positioned at second insulating barrier on described floating boom surface, the sidewall structure that is positioned at the control gate of described the second surface of insulating layer and covers described floating boom, control gate; Wherein, described the first insulating barrier comprises the 3rd insulating barrier and the 4th insulating barrier that all is positioned at described semiconductor substrate surface, and the thickness of described the 3rd insulating barrier is greater than the thickness of described the 4th insulating barrier; During to described storage bit unit programming, the electronics in described Semiconductor substrate injects described floating boom via described the 4th insulating barrier.
Because described the first insulating barrier comprises the 3rd insulating barrier and the 4th insulating barrier, identical in the thickness of described the 4th insulating barrier and prior art, the thickness of described the 3rd insulating barrier is greater than the thickness of described the 4th insulating barrier, therefore, electronics reduces from the probability leaked described floating boom, can improve the data holding ability of gate-division type flash memory.And during to described gate-division type flash memory programming, the electronics in described Semiconductor substrate injects described floating boom via described the 4th insulating barrier, and does not need through described the 3rd insulating barrier, can guarantee the normal programming to described gate-division type flash memory.
Technical solution of the present invention also provides a kind of formation method of gate-division type flash memory, and the formation method of described gate-division type flash memory comprises: Semiconductor substrate is provided; On described Semiconductor substrate, form storage bit unit, wherein, described storage bit unit comprises the first insulating barrier that is positioned at described semiconductor substrate surface at least, be positioned at the floating boom of described the first surface of insulating layer, be positioned at second insulating barrier on described floating boom surface, the sidewall structure that is positioned at the control gate of described the second surface of insulating layer and covers described floating boom, control gate; Wherein, described the first insulating barrier comprises the 3rd insulating barrier and the 4th insulating barrier that all is positioned at described semiconductor substrate surface, and the thickness of described the 3rd insulating barrier is greater than the thickness of described the 4th insulating barrier; During to described storage bit unit programming, the electronics in described Semiconductor substrate injects described floating boom via described the 4th insulating barrier.
Those skilled in the art know, and flash memory generally includes the storage array that a plurality of flash cells form.In following examples of the present invention, be all that structure and the formation method with a flash cell describes.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Embodiment 1
At first the present embodiment provides a kind of formation method of gate-division type flash memory, and Fig. 1 to Fig. 9 is the structural representation of the gate-division type flash memory forming process of the present embodiment.
With reference to figure 1, Semiconductor substrate 100 is provided, on the surface of described Semiconductor substrate 100, form pentasyllabic quatrain edge material layer 110.
Wherein a kind of of the silicon substrate, germanium substrate, germanium silicon substrate, silicon-on-insulator substrate that described Semiconductor substrate 100 is selected from P type or N-type.The material of described pentasyllabic quatrain edge material layer 110 is that thickness is the silica of 150 dusts～250 dusts, and the technique that forms described pentasyllabic quatrain edge material layer 110 is thermal oxidation technology, atom layer deposition process or chemical vapor deposition method.
With reference to figure 2, remove the described pentasyllabic quatrain edge of part material layer 110, until expose described Semiconductor substrate 100, form opening 111 and the 3rd insulation material layer 112.
At the interior formation thickness of described opening 111, be less than the 4th insulation material layer 113 of described the 3rd insulation material layer 112 thickness, form first insulation material layer 120 of " recessed " font shown in Figure 3.
Identical in the material of described the 4th insulation material layer 113 and prior art, adopting thickness is the silica of 80 dusts～120 dusts, and the technique that forms described the 4th insulation material layer 113 is depositing technics.
With reference to figure 4, form floating boom material layer 130 on described the first insulation material layer 120 surfaces;
On described floating boom material layer 130 surfaces, form the second insulation material layer 140;
In the surperficial formation control gate material layer 150 of described the second insulation material layer 140, and form mask layer 160 on described control gate material layer 150 surfaces.
Described floating boom material layer 130 is used to form floating boom, and described control gate material layer 150 is used to form control gate.The material of described floating boom material layer 130, control gate material layer 150 is polysilicon or the metal doped with N-type or p type impurity ion, and the technique that forms described polysilicon is chemical vapor deposition method.
The material of described the second insulation material layer 140 is silica, and the technique that forms described the second insulation material layer 140 is chemical vapor deposition method.
The material of described mask layer 160 is wherein one or more such as photoresist, silica, silicon nitride, silicon oxynitride, amorphous carbon, and the technique that forms described mask layer is chemical vapor deposition method.In the present embodiment, the material of described mask layer 160 is silicon nitride.
With reference to figure 4 and Fig. 5, in described mask layer 160, be formed with the opening (not shown), along described opening substep, described control gate material layer 150, the second insulation material layer 140, floating boom material layer 130 and the 4th insulation material layer 113 are carried out to etching, until expose described Semiconductor substrate 100, form groove 170, the symmetrical configuration of described groove 170 both sides.
Particularly, adopt photoetching process to carry out etching to described the 4th insulation material layer 113, floating boom material layer 130, the second insulation material layer 140 and control gate material layer 150, remove described the 4th insulation material layer 113 of part, floating boom material layer 130, the second insulation material layer 140 and control gate material layer 150, until expose described Semiconductor substrate 100; Afterwards, adopt described the second insulation material layer 140 of photoetching process etching and control gate material layer 150, remove described the second insulation material layer 140 of part and control gate material layer 150, until expose described floating boom material layer 130, form described groove 170.
In other embodiments, also can be first described control gate material layer 150 and second insulation material layer 140 of the opening exposed region in described mask layer 160 be carried out to etching, until expose described floating boom material layer 130; Again the exposed region of described floating boom material layer 130 carried out to etching, until expose described Semiconductor substrate 100.The exposed region of described Semiconductor substrate 100 is less than the exposed region of described floating boom material layer 130.
With reference to figure 6, in described the 4th insulation material layer 113, floating boom material layer 130, the second insulation material layer 140, control gate material layer 150 and mask layer 160 sidewall surfaces, form the first side wall 180, described the first side wall 180 is monox lateral wall.
Groove (not shown) sidewall between described the first side wall 180 and lower surface form tunnel oxide 190, and the groove that utilizes polysilicon to fill between described the first side wall 180 forms word line 200.
The technique that forms described word line 200 comprises: on described Semiconductor substrate 100, mask layer 160, tunnel oxide 190 surfaces, utilize chemical vapour deposition (CVD) to form polysilicon, described polysilicon has filled up groove between described the first side wall 180, the mask layer 160 of take is etching barrier layer, described polysilicon is carried out to chemico-mechanical polishing, until expose described mask layer 160, in the groove between described the first side wall 180, form word line 200.
In the operation at the gate-division type flash memory data erase, utilize the electronics in the floating boom that described floating boom material layer 130 forms to be tunneling in described word line 200 by described tunnel oxide 190 and described the first side wall 180, the sidewall of described floating boom material layer 130 is less than the distance of the sidewall of described control gate material layer 150 and described tunnel oxide 190 with the distance of described tunnel oxide 190, described floating boom material layer 130 is more less than described control gate material layer 150 etchings, and the operating voltage difference of different flash memories, the thickness of described tunnel oxide 190 also can be different.By adjusting the thickness of described tunnel oxide 190, just can realize the effective control to the electronics in floating boom.
With reference to figure 6 and Fig. 7, remove described mask layer 160, take described the first side wall 180 and word line 200 is mask, the described control gate material layer 150 of etching, the second insulation material layer 140, floating boom material layer 130 and the 3rd insulation material layer 112, formation control grid 151, the second insulating barrier 141, floating boom 131 and the 3rd insulating barrier 122 respectively.Corresponding the 4th insulating barriers 123 that form of described the 4th insulation material layer 113, described the 4th insulating barrier 123 and described the 3rd insulating barrier 122 form the first insulating barriers 121, the length of described the 3rd insulating barrier 122 account for described the first insulating barrier 121 length 40% to 60%.Wherein, in the embodiment of the present invention, the length of indication is that semiconductor structure edge in accompanying drawing 1 is parallel to Semiconductor substrate 100 surface direction distance from left to right.
Please refer to Fig. 8, at sidewall formation second side wall 181 of described the first side wall 180, control gate 151, the second insulating barrier 141, floating boom 131 and the 3rd insulating barrier 122, described the first side wall 180 and the second side wall 181 form sidewall structures 182.Described sidewall structure 182, control gate 151, the second insulating barrier 141, floating boom 131 and the first insulating barrier 121 form storage bit unit 210, and described word line 200 both sides form two discrete storage bit unit.
With reference to figure 9, a storage bit unit, away from the interior formation source electrode 101 of the Semiconductor substrate 100 of described word line 200 1 sides, drains 102 in another storage bit unit away from the interior formation of the Semiconductor substrate 100 of word line 200 1 sides therein.The technique that forms described source electrode 101 and drain electrode 102 is ion implantation technology.
The present embodiment also provides a kind of gate-division type flash memory, please refer to Fig. 9, specifically comprises: Semiconductor substrate 100; Be positioned at described Semiconductor substrate 100 two discrete storage bit unit 210 in surface; Word line 200 between two storage bit unit 210; The tunnel oxide 190 of isolating described storage bit unit 210 and described word line 200 and isolating described word line 200 and described Semiconductor substrate 100; Be positioned at the source electrode 101 of one of them storage bit unit 210 away from the Semiconductor substrate 100 of described word line 200 1 sides; Be positioned at the drain electrode 102 of another storage bit unit 210 away from the Semiconductor substrate 100 of described word line 200 1 sides.
Described storage bit unit 210 comprises the first insulating barrier 121 that is positioned at described Semiconductor substrate 100 surfaces, be positioned at the floating boom 131 on described the first insulating barrier 121 surfaces, be positioned at second insulating barrier 141 on described floating boom 131 surfaces, the sidewall structure 182 that is positioned at the control gate 151 on described the second insulating barrier 141 surfaces and covers described floating boom 131, control gate 151.
Described sidewall structure 182 comprises the first side wall 180 and the second side wall 181.
Described the first insulating barrier 121 comprises the 3rd insulating barrier 122 and the 4th insulating barrier 123 that all is positioned at described Semiconductor substrate 100 surfaces, and the thickness of described the 3rd insulating barrier 122 is greater than the thickness of described the 4th insulating barrier 123; During to described storage bit unit 210 programming, the electronics in described Semiconductor substrate 100 injects described floating boom 131 via described the 4th insulating barrier 123.
When the storage bit unit 210 in the present embodiment is programmed, identical in the program voltage applied and prior art.For convenience of describing, suppose that the storage bit unit near described source electrode 101 is the first storage bit unit, the storage bit unit of close described drain electrode 102 is the second storage bit unit.Correspondingly, the control gate that is arranged in described the first storage bit unit is the first control gate, and the floating boom that is arranged in described the first storage bit unit is the first floating boom; The control gate that is arranged in described the second storage bit unit is the second control gate, and the floating boom that is arranged in described the second storage bit unit is the second floating boom.
So that described the first storage bit unit is programmed for to example, the voltage that described the first control gate is applied is 8V to 10V, the voltage that described the second control gate is applied is 5V, the voltage that described word line 200 is applied is Vt+0.5V, Vt means the threshold voltage of described gate-division type flash memory, the voltage that described source electrode 101 is applied is 5V to 6V, and the voltage that described drain electrode 102 is applied is 0V.
Under the effect of the program voltage applied, described source electrode 101 and drain between 102 and form conducting channel, and at the end formation electric field of described the first insulating barrier 121 near described word line 200, electronics in conducting channel enters the first floating boom through the 4th insulating barrier 123 in described the first storage bit unit, completes programming.
Described the second storage bit unit programming, with similar to described the first storage bit unit programming, is not repeated them here.
Due to identical in the thickness of described the 4th insulating barrier 123 and prior art, the thickness of described the 3rd insulating barrier 122 is greater than the thickness of described the 4th insulating barrier 123, therefore, in the situation that guarantee the normal programming of described storage bit unit 210, the a part of thickness of described the first insulating barrier 121 increases, reduce electronics from the probability that described floating boom 131 leaks, improved the data holding ability of gate-division type flash memory.
And, because the thickness of described the 3rd insulating barrier 122 increases, reduced the electric capacity between described floating boom 131 and described Semiconductor substrate 100, improved the coupling coefficient of control gate 151 in the gate-division type flash memory.
Embodiment 2
At first the present embodiment provides the formation method of another kind of gate-division type flash memory, and Figure 10 to Figure 23 is the structural representation of the gate-division type flash memory forming process of the present embodiment.
With reference to Figure 10, Semiconductor substrate 100 is provided, on described Semiconductor substrate 100 surfaces, form pentasyllabic quatrain edge material layer 110.
Wherein a kind of of the silicon substrate, germanium substrate, germanium silicon substrate, silicon-on-insulator substrate that described Semiconductor substrate 100 is selected from P type or N-type.The material of described pentasyllabic quatrain edge material layer 110 is that thickness is the silica of 150 dusts～250 dusts, and the technique that forms described pentasyllabic quatrain edge material layer 110 is thermal oxidation technology, atom layer deposition process or chemical vapor deposition method.
With reference to Figure 11, remove the described pentasyllabic quatrain edge of part material 110, until expose described Semiconductor substrate 100, form the 3rd insulation material layer 111.
Both sides at described the 3rd insulation material layer 111 form the 4th insulation material layer 112 that thickness is less than described the 3rd insulation material layer 111 thickness, form first insulation material layer 120 of " protruding " font as shown in figure 12.
Identical in the material of described the 4th insulation material layer 112 and prior art, adopting thickness is the silica of 80 dusts～120 dusts, and the technique that forms described the 4th insulation material layer 112 is depositing technics.
With reference to Figure 13, form floating boom material layer 130 on described the first insulation material layer 120 surfaces;
On described floating boom material layer 130 surfaces, form the second insulation material layer 140;
In the surperficial formation control gate material layer 150 of described the second insulation material layer 140, and form mask layer 160 on described control gate material layer 150 surfaces.
Described floating boom material layer 130 is used to form floating boom, and described control gate material layer 150 is used to form control gate.The material of described floating boom material layer 130, control gate material layer 150 is polysilicon or the metal doped with N-type or p type impurity ion, and the technique that forms described polysilicon is chemical vapor deposition method.
The material of described the second insulation material layer 140 is silica, and the technique that forms described the second insulation material layer 140 is chemical vapor deposition method.
The material of described mask layer 160 is wherein one or more such as photoresist, silica, silicon nitride, silicon oxynitride, amorphous carbon, and the technique that forms described mask layer is chemical vapor deposition method.In the present embodiment, the material of described mask layer 160 is silicon nitride.
With reference to Figure 14, described mask layer 160 is carried out to etching, until expose described control gate material layer 150, form the 3rd side wall 161 at described mask layer 160 sidewalls, between described the 3rd side wall 161, expose part control gate material layer 150 surfaces.
Concrete technology comprises: on described mask layer 160 surfaces, form patterned photoresist layer (not shown), the described patterned photoresist layer of take is mask, and described mask layer 160 is carried out to etching, until expose described control gate material layer 150; On described mask layer 160 and control gate material layer 150 surfaces that expose, form the 3rd spacer material layer (not shown), described the 3rd spacer material layer is returned to etching, form the 3rd side walls 161 at described mask layer 160 sidewalls.In the present embodiment, the material of described the 3rd side wall 161 is silica.By controlling the length of described the 3rd spacer material layer, can control the length of described the 3rd side wall 161 bottommosts, thereby control the final floating boom formed and the length of control gate.
With reference to Figure 14 and Figure 15, described the 3rd side wall 161 of take is mask, and described control gate material layer 150 and described the second insulation material layer 140 are carried out to etching, exposes part floating boom material layer 130, forms the first opening (not shown).At described the first opening sidewalls, form the 4th side wall 162, between described the 4th side wall 162, expose part floating boom material layer 130 surfaces.
The material of described the 4th side wall 162 is also silica, and the technique that forms described the 4th side wall 162 of layer is similar with the technique that forms described the 3rd side wall 161, does not repeat them here.
With reference to Figure 15 and Figure 16, described the 4th side wall 162 of take is mask, and described floating boom material layer 130 and the 3rd insulation material layer 111 are carried out to etching, until expose described Semiconductor substrate 100, forms the second opening (not shown).At described the second opening sidewalls, form the 5th side wall (not shown), expose the part semiconductor substrate between described the 5th side wall.The material of described the 5th side wall is also silica, and the technique that forms described the 5th side wall of layer is similar with the technique that forms described the 3rd side wall 161, does not repeat them here.
The common formation of described the 3rd side wall 161, the 4th side wall 162 and the 5th side wall the first side wall 163, expose part semiconductor substrate 100 between described the first side wall 163, and form groove 170, the symmetrical configuration of described groove 170 both sides.
With reference to Figure 17, the interior formation source electrode 101 of part semiconductor substrate 100 exposed between described the first side wall 163, the technique that forms described source electrode 101 is ion implantation technology.
At the surperficial formation of described the first side wall 163 source line 180, form the first medium material layer on described source line 180 surfaces.Described first medium material layer is silica material, is used to form the first medium layer 190 that makes described source line 180 and extraneous electricity isolate.
The technique that forms described source line 180 comprises: utilize chemical vapour deposition (CVD) to form polysilicon in described Semiconductor substrate 100 and the first side wall 163 surfaces, described polysilicon is filled described groove 170, the mask layer 160 of take is etching barrier layer, described polysilicon is carried out to chemico-mechanical polishing, until expose described mask layer 160, in described groove 170, form source line 180.
With reference to Figure 17 and Figure 18, remove described mask layer 160, take described the first side wall 163 and first medium layer 190 and be mask, the described control gate material layer 150 of etching and the second insulation material layer 140, formation control grid 151 and the second insulating barrier 141 respectively.Sidewall at described the first side wall 163, control gate 151 and the second insulating barrier 141 forms the 5th side wall 164, and described the first side wall 163 and the 5th side wall 164 form sidewall structure 165.
With reference to Figure 18 and Figure 19, take described sidewall structure 165 and described first medium layer 190 and be mask, the described floating boom material layer 130 of etching and the 4th insulation material layer 112, form respectively floating boom 131 and the 4th insulating barrier 123.Corresponding the 3rd insulating barriers 122 that form of described the 3rd insulation material layer 111, described the 3rd insulating barrier 122 and described the 4th insulating barrier 123 form the first insulating barriers 121, the length of described the 3rd insulating barrier 122 account for described the first insulating barrier 121 length 40% to 60%.
Described sidewall structure 165, control gate 151, the second insulating barrier 141, floating boom 131 and the first insulating barrier 121 form storage bit unit 210, and line 180 both sides in described source form two discrete storage bit unit.
Continuation, with reference to Figure 19, generates second medium material layer 200 at described storage bit unit 210, first medium layer 190 and Semiconductor substrate 100 surface uniforms.The material of described second medium material layer 200 is silicon nitride, adopts chemical vapor deposition method to form.
With reference to Figure 20, adopt chemical vapor deposition method, at described second medium material layer 200 Surface Creation wordline material layers 220, described wordline material 220 is polysilicon.
With reference to Figure 20 and Figure 21, adopt dry etch process, remove the described wordline material layer 220 of part and second medium material layer 200, expose described first medium material layer 190, the first side wall 163 and Semiconductor substrate 100, with at the side formation word line 211 of described storage bit unit 210 away from the source line, between described word line 211 and storage bit unit 210 and between word line 211 and Semiconductor substrate 100, forming second medium layer 201.
With reference to Figure 22, at side formation second side wall of described word line 211 away from storage bit unit 210, described the second side wall is separator 166.The material of described the second side wall is also silica, and the technique that forms described the second side wall is similar with the technique that forms described the 3rd side wall 161, does not repeat them here.
With reference to Figure 23, a storage bit unit, drain 102 away from the interior formation first of the Semiconductor substrate 100 of source line 180 1 sides, away from interior formation the second drain electrode 103 of the Semiconductor substrate 100 of source line 180 1 sides, the technique that forms described first drain electrode the 102 and second drain electrode 103 is ion implantation technology in another storage bit unit.
The present embodiment also provides a kind of gate-division type flash memory, please refer to Figure 23, specifically comprises: Semiconductor substrate 100; Be positioned at first drain electrode the 102, second drain electrode 103 and source electrode 101 of described Semiconductor substrate 100, described source electrode 101 is between described the first drain electrode 102 and described the second drain electrode 103; Be positioned at described Semiconductor substrate 100 two discrete storage bit unit 210 in surface; Source line 180 between described source electrode 101 surfaces, two storage bit unit; Be positioned at the first medium layer 190 on line 180 surfaces, described source; Be positioned at the word line 211 of described storage bit unit 210 away from described source line 180 1 sides; The second medium layer 201 of isolating described storage bit unit 210 and described word line 211 and isolating described word line 211 and described Semiconductor substrate 100; Be positioned at the separator 166 of described word line 211 away from described storage bit unit 210 1 sides.
Described storage bit unit 210 comprises the first insulating barrier 121 that is positioned at described Semiconductor substrate 100 surfaces, be positioned at the floating boom 131 on described the first insulating barrier 121 surfaces, be positioned at second insulating barrier 141 on described floating boom 131 surfaces, the sidewall structure 165 that is positioned at the control gate 151 on described the second insulating barrier 141 surfaces and covers described floating boom 131, control gate 151.
Described sidewall structure 165 comprises the first side wall 163 and the 5th side wall 164.
Described the first insulating barrier 121 comprises the 3rd insulating barrier 122 and the 4th insulating barrier 123 that all is positioned at described Semiconductor substrate 100 surfaces, and the thickness of described the 3rd insulating barrier 122 is greater than the thickness of described the 4th insulating barrier 123; During to described storage bit unit 210 programming, the electronics in described Semiconductor substrate 100 injects described floating boom 131 via described the 4th insulating barrier 123.
When the storage bit unit 210 in the present embodiment is programmed, identical in the program voltage applied and prior art.For convenience of describing, suppose that the storage bit unit near the first drain electrode 102 is the first storage bit unit, the storage bit unit of close the second drain electrode 103 is the second storage bit unit.Correspondingly, the control gate that is arranged in described the first storage bit unit is the first control gate, and the floating boom that is arranged in described the first storage bit unit is the first floating boom, and the word line of close described the first storage bit unit is the first word line; The control gate that is arranged in described the second storage bit unit is the second control gate, and the floating boom that is arranged in described the second storage bit unit is the second floating boom, and the word line of close described the second storage bit unit is the second word line.
So that described the first storage bit unit is programmed for to example, the voltage that described the first control gate is applied is 10V, the voltage that described source line 180 is applied is 5V to 6V, the voltage that described the first word line is applied is Vt+0.5V, Vt means the threshold voltage of described gate-division type flash memory, is 0V to described the first drain electrode 102 voltages that apply.
Under the effect of the program voltage applied, between described source electrode 101 and the first drain electrode 102, form conducting channel, and at the end formation electric field of described the first insulating barrier 121 near described the first word line, electronics in conducting channel enters the first floating boom through the 4th insulating barrier 123 in described the first storage bit unit, completes programming.
Described the second storage bit unit programming, with similar to described the first storage bit unit programming, is not repeated them here.
The gate-division type flash memory of the present embodiment has reduced electronics from the probability that floating boom leaks, and has improved the data holding ability of gate-division type flash memory and the coupling coefficient of control gate.
Although the present invention discloses as above, the present invention not is defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (10)
1. a gate-division type flash memory, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the storage bit unit of described semiconductor substrate surface;
Described storage bit unit comprises the first insulating barrier that is positioned at described semiconductor substrate surface, be positioned at the floating boom of described the first surface of insulating layer, be positioned at second insulating barrier on described floating boom surface, the sidewall structure that is positioned at the control gate of described the second surface of insulating layer and covers described floating boom, control gate;
Wherein, described the first insulating barrier comprises the 3rd insulating barrier and the 4th insulating barrier that all is positioned at described semiconductor substrate surface, and the thickness of described the 3rd insulating barrier is greater than the thickness of described the 4th insulating barrier; During to described storage bit unit programming, the electronics in described Semiconductor substrate injects described floating boom via described the 4th insulating barrier.
2. gate-division type flash memory according to claim 1, is characterized in that, the thickness of described the 3rd insulating barrier is 150 dusts～250 dusts, and the thickness of described the 4th insulating barrier is 80 dusts～120 dusts.
3. gate-division type flash memory according to claim 1, is characterized in that, the length of described the 3rd insulating barrier account for described the first insulating barrier length 40% to 60%.
4. gate-division type flash memory according to claim 1, is characterized in that, described gate-division type flash memory also comprises:
Word line between two storage bit unit;
The tunnel oxide of isolating described storage bit unit and described word line and isolating described word line and described Semiconductor substrate;
Be positioned at the source electrode of one of them storage bit unit away from the Semiconductor substrate of described word line one side;
Be positioned at the drain electrode of another storage bit unit away from the Semiconductor substrate of described word line one side.
5. gate-division type flash memory according to claim 1, is characterized in that, described gate-division type flash memory also comprises:
Be positioned at the first drain electrode, second drain electrode and the source electrode of described Semiconductor substrate, described source electrode is between described the first drain electrode and described the second drain electrode;
Source line between described source electrode surface, two storage bit unit;
Be positioned at the first medium layer on line surface, described source;
Be positioned at the word line of described storage bit unit away from described source line one side;
The second medium layer of isolating described storage bit unit and described word line and isolating described word line and described Semiconductor substrate;
Be positioned at the separator of described word line away from described storage bit unit one side.
6. the formation method of a gate-division type flash memory, is characterized in that, comprising:
Semiconductor substrate is provided;
On described Semiconductor substrate, form storage bit unit, wherein, described storage bit unit comprises the first insulating barrier that is positioned at described semiconductor substrate surface at least, be positioned at the floating boom of described the first surface of insulating layer, be positioned at second insulating barrier on described floating boom surface, the sidewall structure that is positioned at the control gate of described the second surface of insulating layer and covers described floating boom, control gate; Wherein, described the first insulating barrier comprises the 3rd insulating barrier and the 4th insulating barrier that all is positioned at described semiconductor substrate surface, and the thickness of described the 3rd insulating barrier is greater than the thickness of described the 4th insulating barrier; During to described storage bit unit programming, the electronics in described Semiconductor substrate injects described floating boom via described the 4th insulating barrier.
7. the formation method of gate-division type flash memory according to claim 6, is characterized in that, the described storage bit unit that forms on described Semiconductor substrate comprises:
At described semiconductor substrate surface, form the first insulation material layer, described the first insulation material layer comprises the 4th insulation material layer and is positioned at described the 4th insulation material layer both sides and thickness is greater than the 3rd insulation material layer of described the 4th insulation material layer;
Surface at described the first insulation material layer forms the floating boom material layer;
Surface at described floating boom material layer forms the second insulation material layer;
Surperficial formation control gate material layer at described the second insulation material layer;
Remove control gate material layer, the second insulation material layer, floating boom material layer and the 4th insulation material layer of part, with formation, expose the groove of described Semiconductor substrate, the symmetrical configuration of described groove both sides;
In described groove, form successively monox lateral wall, tunnel oxide and polysilicon word line.
8. the formation method of gate-division type flash memory according to claim 7, is characterized in that, describedly at described semiconductor substrate surface, forms the first insulation material layer and comprise:
At described semiconductor substrate surface, form pentasyllabic quatrain edge material layer;
Remove the described pentasyllabic quatrain edge of part material layer, until expose described Semiconductor substrate, to form opening and described the 3rd insulation material layer;
In described opening, form described the 4th insulation material layer, the thickness of described the 4th insulation material layer is less than the thickness of described the 3rd insulation material layer.
9. the formation method of gate-division type flash memory according to claim 6, is characterized in that, the described storage bit unit that forms on described Semiconductor substrate comprises:
At described semiconductor substrate surface, form the first insulation material layer, described the first insulation material layer comprises the 3rd insulation material layer and is positioned at described the 3rd insulation material layer both sides and thickness is less than the 4th insulation material layer of described the 3rd insulation material layer;
Surface at described the first insulation material layer forms the floating boom material layer;
Surface at described floating boom material layer forms the second insulation material layer;
Surperficial formation control gate material layer at described the second insulation material layer;
Remove described control gate material layer, the second insulation material layer, floating boom material layer and the 3rd insulation material layer of part;
Form the first side wall, between described the first side wall, form the groove that exposes the part semiconductor substrate, the symmetrical configuration of described groove both sides;
In the Semiconductor substrate exposed, form source electrode between described the first side wall;
On described the first side wall surface, form the source line of filling described groove;
On described source line surface, form the first medium material layer;
Take described the first side wall and first medium material layer is mask, and the described control gate material layer of etching, the second insulation material layer, floating boom material layer and the 4th insulation material layer, to form two discrete storage bit unit in line both sides, described source;
The formation method of described gate-division type flash memory also comprises:
At described storage bit unit, first medium material layer and semiconductor substrate surface, form the second medium material layer;
In described second medium material surface, form the wordline material layer;
Remove the described wordline material layer of part and second medium material layer, until expose described first medium material layer, the first side wall and Semiconductor substrate, in described storage bit unit, to form the word line away from a side of source line;
At side formation second side wall of described word line away from storage bit unit;
In described storage bit unit, form respectively drain electrode in away from the Semiconductor substrate of source line one side.
10. the formation method of gate-division type flash memory according to claim 9, is characterized in that, describedly at described semiconductor substrate surface, forms the first insulation material layer and comprise:
At described semiconductor substrate surface, form pentasyllabic quatrain edge material layer;
Remove the described pentasyllabic quatrain edge of part material layer, until expose described Semiconductor substrate, to form described the 3rd insulation material layer;
In the both sides of described the 3rd insulation material layer, form described the 4th insulation material layer, the thickness of described the 4th insulation material layer is less than the thickness of described the 3rd insulation material layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310374526.1A CN103413809B (en) | 2013-08-23 | 2013-08-23 | Gate-division type flash memory and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310374526.1A CN103413809B (en) | 2013-08-23 | 2013-08-23 | Gate-division type flash memory and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103413809A true CN103413809A (en) | 2013-11-27 |
| CN103413809B CN103413809B (en) | 2016-04-06 |
Family
ID=49606807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310374526.1A Active CN103413809B (en) | 2013-08-23 | 2013-08-23 | Gate-division type flash memory and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103413809B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060006452A1 (en) * | 2004-07-06 | 2006-01-12 | Samsung Electronics Co., Ltd. | EEPROM device and manufacturing method thereof |
| US20070298571A1 (en) * | 2003-06-20 | 2007-12-27 | Weon-Ho Park | Single chip data processing device with embedded nonvolatile memory and method thereof |
| CN102290376A (en) * | 2011-08-26 | 2011-12-21 | 上海宏力半导体制造有限公司 | Formation method for integrated semiconductor device |
| CN102315252A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Flash memory unit for shared source line and forming method thereof |
-
2013
- 2013-08-23 CN CN201310374526.1A patent/CN103413809B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070298571A1 (en) * | 2003-06-20 | 2007-12-27 | Weon-Ho Park | Single chip data processing device with embedded nonvolatile memory and method thereof |
| US20060006452A1 (en) * | 2004-07-06 | 2006-01-12 | Samsung Electronics Co., Ltd. | EEPROM device and manufacturing method thereof |
| CN102290376A (en) * | 2011-08-26 | 2011-12-21 | 上海宏力半导体制造有限公司 | Formation method for integrated semiconductor device |
| CN102315252A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Flash memory unit for shared source line and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103413809B (en) | 2016-04-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103165615B (en) | Split-gate flash memory and forming method thereof | |
| CN104282761A (en) | Vertical channel memory and manufacturing method thereof and operating method using the same | |
| CN102347281B (en) | Split-gate flash memory unit and forming method thereof | |
| CN101162736A (en) | Vertical channel transistor structure and manufacturing method thereof | |
| CN102938406A (en) | Split gate type flash memory and forming method thereof | |
| CN102368479B (en) | Flash memory and manufacturing method thereof | |
| CN102117814B (en) | Grid-sharing flash memory unit and preparation method thereof | |
| TW202008510A (en) | Split-gate type non-volatile memory and manufacturing method thereof | |
| CN104821318A (en) | Separate gate memory device and forming method thereof | |
| CN105336622A (en) | Semi-floating gate device and formation method therefor | |
| CN104752360A (en) | Memory device and forming method thereof | |
| US7618864B2 (en) | Nonvolatile memory device and methods of forming the same | |
| CN101777562B (en) | Non-volatile semiconductor memory with floating gate and manufacturing method thereof | |
| CN104900650A (en) | Split gate flash memory and manufacturing method thereof | |
| CN102593061B (en) | Flash memory of discrete gate and manufacture method thereof | |
| CN102097383B (en) | Method for manufacturing double-bit flash memory | |
| CN102290444A (en) | SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory | |
| US20110169069A1 (en) | Hto offset and bl trench process for memory device to improve device performance | |
| CN102163576B (en) | Split-gate flash memory unit and manufacturing method thereof | |
| CN101714560A (en) | Eeprom and method for manufacturing the eeprom | |
| CN104934430A (en) | NOR flash memory and manufacturing method thereof | |
| KR100814376B1 (en) | Non-volatile memory device and method of manufacturing the same | |
| CN103413809B (en) | Gate-division type flash memory and forming method thereof | |
| CN102280378A (en) | SONOS structure and SONOS memory formation method | |
| CN110277399B (en) | SONOS memory and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140408 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140408 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |