CN103413803B - 一种混合集成电路及其制造方法 - Google Patents
一种混合集成电路及其制造方法 Download PDFInfo
- Publication number
- CN103413803B CN103413803B CN201310290021.7A CN201310290021A CN103413803B CN 103413803 B CN103413803 B CN 103413803B CN 201310290021 A CN201310290021 A CN 201310290021A CN 103413803 B CN103413803 B CN 103413803B
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- CN
- China
- Prior art keywords
- circuit substrate
- circuit
- mmic chip
- polytetrafluoroethylene
- blind slot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310290021.7A CN103413803B (zh) | 2013-07-10 | 2013-07-10 | 一种混合集成电路及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310290021.7A CN103413803B (zh) | 2013-07-10 | 2013-07-10 | 一种混合集成电路及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103413803A CN103413803A (zh) | 2013-11-27 |
CN103413803B true CN103413803B (zh) | 2016-01-20 |
Family
ID=49606801
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310290021.7A Active CN103413803B (zh) | 2013-07-10 | 2013-07-10 | 一种混合集成电路及其制造方法 |
Country Status (1)
Country | Link |
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CN (1) | CN103413803B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104332692B (zh) * | 2014-10-10 | 2017-05-17 | 中国电子科技集团公司第四十一研究所 | 采用金属压块拼接技术粘贴软介质微波电路的方法 |
WO2019153122A1 (zh) * | 2018-02-06 | 2019-08-15 | 深圳市傲科光电子有限公司 | 混合印刷电路板 |
CN112216675A (zh) * | 2020-09-11 | 2021-01-12 | 中国电子科技集团公司第十三研究所 | 微组装基板结构及芯片微组装方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1477702A (zh) * | 2002-07-09 | 2004-02-25 | 恩益禧电子股份有限公司 | 用于制造电子封装的半导体安装衬底和生产这种半导体安装衬底的生产过程 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100836663B1 (ko) * | 2006-02-16 | 2008-06-10 | 삼성전기주식회사 | 캐비티가 형성된 패키지 온 패키지 및 그 제조 방법 |
FR2945379B1 (fr) * | 2009-05-05 | 2011-07-22 | United Monolithic Semiconductors Sa | Composant miniature hyperfrequences pour montage en surface |
-
2013
- 2013-07-10 CN CN201310290021.7A patent/CN103413803B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1477702A (zh) * | 2002-07-09 | 2004-02-25 | 恩益禧电子股份有限公司 | 用于制造电子封装的半导体安装衬底和生产这种半导体安装衬底的生产过程 |
Also Published As
Publication number | Publication date |
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CN103413803A (zh) | 2013-11-27 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20190227 Address after: 266555 Xiangjiang 98, Huangdao District, Qingdao City, Shandong Province Patentee after: China Electronics Technology Instrument and Meter Co., Ltd. Address before: 266555 No. 98 Xiangjiang Road, Qingdao economic and Technological Development Zone, Shandong Patentee before: The 41st Institute of CETC |
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TR01 | Transfer of patent right | ||
CP01 | Change in the name or title of a patent holder |
Address after: 266555 Xiangjiang 98, Huangdao District, Qingdao City, Shandong Province Patentee after: CLP kesiyi Technology Co.,Ltd. Address before: 266555 Xiangjiang 98, Huangdao District, Qingdao City, Shandong Province Patentee before: CHINA ELECTRONIC TECHNOLOGY INSTRUMENTS Co.,Ltd. |
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CP01 | Change in the name or title of a patent holder |