CN103413797A - Power semiconductor module assembled through three-dimensional structural units - Google Patents
Power semiconductor module assembled through three-dimensional structural units Download PDFInfo
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- CN103413797A CN103413797A CN2013103230975A CN201310323097A CN103413797A CN 103413797 A CN103413797 A CN 103413797A CN 2013103230975 A CN2013103230975 A CN 2013103230975A CN 201310323097 A CN201310323097 A CN 201310323097A CN 103413797 A CN103413797 A CN 103413797A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Abstract
The invention provides a power semiconductor module assembled through three-dimensional structural units. The power semiconductor module is assembled mechanically through the multiple three-dimensional structural units (6). An emitting electrode of one three-dimensional structural unit is connected with a collector electrode of another three-dimensional structural unit in series through a connector to form a half-bridge unit, and the multiple half-bridge units are in parallel connection. Each three-dimensional structural unit (6) of the power semiconductor module is composed of an all-control type power semiconductor chip (10a), a non-control type power semiconductor chip (10b), a first substrate (1) and a second substrate (5), wherein the all-control type power semiconductor chip (10a) and the non-control type power semiconductor chip (10b) are located between the first substrate (1) and the second substrate (5) and arranged side by side, and a grid electrode (10a2) of the all-control type power semiconductor chip (10a) is located at one corner of the non-control type power semiconductor chip (10b). The power semiconductor module is filled with insulation cooling liquid to be cooled.
Description
Technical field
The present invention relates to a kind of power semiconductor modular of three-dimension packaging.
Background technology
In recent years, along with the development of new energy technology, powerful current transformer is widely used.The heat-sinking capability of inverter becomes a common key problem of paying close attention to.The power semiconductor modular junction temperature of chip at work may reach 175 ℃ even higher, and too high junction temperature of chip has reduced the cycle-index of power semiconductor modular and then the useful life that can reduce module greatly.
In the current power semiconductor module, adopt the method for metallic bond zygonema for the connection between IGBT and diode, the method because thermal fatigue easily causes peeling off of bonding line, greatly reduces the reliability of module under hot conditions.This traditional encapsulating structure chips front has adopted bonding wire to carry out electric interconnection, therefore can only be by welding overleaf DBC and the copper soleplate structure is dispelled the heat as the chip of thermal source, and the radiating efficiency of traditional single face radiator structure is very limited.
In addition, the high heat-flux power device makes thermal source chip surface temperature distributing disproportionation phenomenon more outstanding due to self inhomogeneous cooling channel structure.Current module generally adopts the mode that is welded direct to copper soleplate to encapsulate, and this makes certain element failure cause whole module to be scrapped, and other intact cell mesh can not further utilize, and makes use cost increase.
The power semiconductor modular that U.S. Pat 0138452A1 and US7005743B2 propose has adopted two-sided cooling method, improved the cooling effect of module, what but the grid of the described power semiconductor chip of this patent adopted is that bonding wire is drawn, whole encapsulation process is not still broken away from the dependence of para-linkage line, has increased the process complexity of encapsulation.
Summary of the invention
The objective of the invention is to overcome the shortcoming of prior art, propose the power semiconductor modular that a kind of three-dimensional structure without lead key closing process unit assembles.One aspect of the present invention can reduce chip crust thermal resistance, reduce the junction temperature of chip, can reduce the stray parameter of module simultaneously, and then improves the power density of power semiconductor modular.
Power semiconductor modular of the present invention is comprised of a plurality of three-dimensional structures unit, the mode that each three-dimensional structure unit is fixed by machinery is arranged on above insulating base, each three-dimensional structure unit can load and unload flexibly, avoid the problem that causes module whole to lose efficacy because of certain cell failure wherein, power semiconductor modular can effectively improve the heat dispersion of module simultaneously.
In power semiconductor modular of the present invention, the emitter of a three-dimensional structure unit is connected as a half-bridge unit with the collector electrode of another one three-dimensional structure unit by splicing ear, then according to different circuit requirements, selects the half-bridge unit of different numbers to carry out parallel connection.In power semiconductor modular, the number of three-dimensional structure unit is determined by voltage, the current class of chip and the circuit structure that will realize.
Each three-dimensional structure unit by the full-control type power semiconductor chip, do not control type power semiconductor chip, the first substrate, the second substrate, the first metallic gasket, the second metallic gasket and the 3rd metallic gasket and form, the first welded metal pad is to the grid of full-control type power semiconductor chip, the second welded metal pad is to the grid of full-control type power semiconductor chip, and the 3rd welded metal pad is to the positive pole of not controlling the type power semiconductor chip.The first substrate forms by three layers: be positioned at top the first metal layer, be positioned at the first middle electric insulation layer and be positioned at the second following metal level.Described the first metal layer forms mutually discrete two parts by etching technics: the first metal layer gate electrode side and the first metal layer emitter side.Described the second metal level forms two parts by etching technics: the second metal level gate electrode side and the second metal level emitter side.The first metal layer gate electrode side is corresponding up and down with the position of the second metal level gate electrode side, and the first metal layer emitter side is corresponding up and down with the second metal level emitter side.The first electric insulation layer in the middle of being positioned at has a plated-through hole, and the first metal layer gate electrode side is connected by described plated-through hole with the second metal level gate electrode side.Electric insulation between the first metal layer emitter side and the second metal level emitter side.
The second substrate forms by three layers: be positioned at the 3rd top metal level, be positioned at the second middle electric insulation layer and be positioned at the 4th following metal level.The 3rd metal level forms unconnected two parts by etching technics: the 3rd metal level collector electrode side and the 3rd metal level emitter side, the 3rd metal level collector electrode side is not connected with the 3rd metal level emitter side.
The first metal layer, the second metal level and the 3rd metal level all have circuit structure.
The electric insulation layer of two substrates adopts the highly heat-conductive materials such as aluminium oxide, aluminium nitride or silicon nitride to make, and the material of the metal level of two substrates is the alloy of copper ﹑ aluminium or copper etc.Full-control type power semiconductor chip and the circuit structure of not controlling the metal level of type power semiconductor chip by two substrates are realized interconnection.
The first substrate is positioned at the top of whole three-dimensional structure unit, the second substrate is positioned at the bottom of whole three-dimensional structure unit, full-control type power semiconductor chip and do not control the type power semiconductor chip and be welded on side by side between first substrate the second metal level and the second substrate the 3rd metal level, the grid of full-control type power semiconductor chip is corresponding with the second metal level gate electrode side, and the emitter of full-control type power semiconductor chip, the positive pole of not controlling the type power semiconductor chip are corresponding with the second metal level collector electrode side.
The full-control type power semiconductor chip is IGBT etc., and not controlling the type power semiconductor chip is silicon-based diode or silicon carbide-based diode etc.
The grid of described full-control type power semiconductor chip is by the second metal level gate electrode side welding of the first metallic gasket and the first substrate, and first substrate the second metal level gate electrode side is connected with the first substrate the first metal layer gate electrode side by the electric insulation layer plated-through hole; The emitter of full-control type power semiconductor chip and the positive pole of not controlling the type power semiconductor chip weld by the second metal level emitter side of the second metallic gasket and the 3rd metallic gasket and the first substrate respectively.The collector electrode of full-control type power semiconductor chip and the negative pole of not controlling the type power semiconductor chip respectively with the collector electrode side welding of the 3rd metal level; The second metal level emitter side is by the 4th metallic gasket and the welding of the 3rd metal level emitter side.
Power semiconductor modular is undertaken cooling by the direct invasion cooling circulating fluid that insulate.
The present invention has strengthened the heat-sinking capability of power semiconductor modular, improved modular power density, simultaneously realized again the flexible loading and unloading of three-dimensional structure unit on the power semiconductor modular insulating base, so the present invention is specially adapted to the high heat-flux occasions such as large-scale wind energy, solar power plant.Interconnected between power semiconductor chip of the present invention welds to realize by metallic layer circuit, broken away from the dependence of para-linkage technique, improved the reliability of power semiconductor modular.
The accompanying drawing explanation
Fig. 1 a is the sectional view of three-dimensional structure unit;
Fig. 1 b is the left view of three-dimensional structure unit;
Fig. 2 is the vertical view of the first substrate of three-dimensional structure unit;
Fig. 3 is the upward view of three-dimensional structure unit the first substrate;
Fig. 4 is the vertical view of three-dimensional structure unit the second substrate;
Fig. 5 is three-dimensional structure unit installation diagram;
Fig. 6 a is the mounted inside figure of the embodiment of the present invention;
Fig. 6 b is the shell figure of the embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention.
Power semiconductor modular of the present invention is comprised of a plurality of three-dimensional structures unit, and each three-dimensional structure unit is fixedly mounted on above insulating base.The emitter of a three-dimensional structure unit is connected as a half-bridge unit with the collector electrode of another one three-dimensional structure unit by splicing ear, the unit parallel connection of a plurality of half-bridges.
As shown in Figure 1a, three-dimensional structure unit 6 comprises full-control type power semiconductor chip 10a, does not control type power semiconductor chip 10b, the first substrate 1, the second substrate 5, the first metallic gasket 8a, the second metallic gasket 9a, and the 3rd metallic gasket 9b.Described full-control type power semiconductor chip 10a and do not control type power semiconductor chip 10b between the first substrate 1 and the second substrate 5, be arranged in juxtaposition.
As shown in Figure 3, in three-dimensional structure unit 6, do not control type power semiconductor chip 10b and be positioned at the side away from full-control type power semiconductor chip 10a grid 10a2, full-control type power semiconductor chip 10a, do not control type power semiconductor chip 10b and align with the left side edge of the second substrate.The grid 10a2 of described full-control type power semiconductor chip 10a is positioned at full-control type power semiconductor chip edge.
The first substrate 1 and the second substrate 5 form by three-decker: middle one deck is electric insulation layer, electric insulation layer top and following be metal level.
The first substrate 1 is comprised of the first metal layer 1a, the first electric insulation layer 1b and the second metal level 1c; The first metal layer 1a be positioned at above the first electric insulation layer 1b is divided into the first metal layer emitter side 1a1 and the first metal layer gate electrode side 1a2 two parts, not conducting between described the first metal layer emitter side 1a1 and the first metal layer gate electrode side 1a2; The the second metal level 1c be positioned at below the first electric insulation layer 1b is divided into the second metal level emitter side 1c1 and the first metal layer gate electrode side 1c2 two parts, not conducting between described the second metal level emitter side 1c1 and the second metal level gate electrode side 1c2; The first metal layer gate electrode side 1a2 is connected by a plated-through hole 7c who is positioned at the first insulating barrier 1b with the second metal level gate electrode side 1c2.
The grid 10a2 of described full-control type power semiconductor chip 10a is corresponding with the second metal level gate electrode side 1c2, and the emitter 10a1 of full-control type power semiconductor chip 10a, the anodal 10b1 of not controlling the type power semiconductor chip are corresponding with the collector electrode side 1c1 of the second metal level.The second substrate 5 is comprised of the 3rd metal level 5a, the second electric insulation layer 5b and the 4th metal level 5c; The 3rd metal level 5a and the 4th metal level 5c lay respectively at the top of the second electric insulation layer 5b and below; The 3rd metal level 5a forms the 3rd metal level collector electrode side 5a1 and the 3rd metal level emitter side 5a2 two parts, not conducting between the 3rd metal level collector electrode side 5a1 and the 3rd metal level emitter side 5a2 by etching technics.
As shown in Figure 2, Figure 3, Figure 4, the first metal layer 1a, the second metal level 1c and the 3rd metal level 5a all have circuit structure.
As shown in Figure 1a, the collector electrode 10a1 of full-control type power semiconductor chip 10a, the negative pole 10b2 of not controlling the type power semiconductor chip are welded on the 3rd metal level emitter side 5a1; The emitter 10a1 of full-control type power semiconductor chip 10a, grid 10a2 and anodal 10b1 respectively with the first metallic gasket 8a, the second metallic gasket 9a and the 3rd metallic gasket 9b welding of not controlling the type power semiconductor chip; The second metal level gate electrode side 1c2 welding of the first metallic gasket 8a and the first substrate 1, and be connected with the first metal layer gate electrode side 1a2 of the first substrate 1 by metallization via hole 7c; The second metal level emitter side 1c1 welding of the second metallic gasket 9a and the 3rd metallic gasket 9b and the first substrate 1.
As shown in Figure 1 b, the second metal level emitter side 1c1 of the first substrate 1 is connected with the 3rd metal level emitter side 5a2 of the second substrate 5 by the 4th metallic gasket 11.
As shown in Figure 6 a, the emitter e 2 of the first three-dimensional structure unit is connected and is formed a half-bridge unit by splicing ear 22 with the collector electrode e3 of the second three-dimensional structure unit; The emitter f2 of the 3rd three-dimensional structure unit connects and forms a half-bridge unit by splicing ear 22 with the collector electrode f3 of the 4th three-dimensional structure unit, and the emitter g2 of the 5th three-dimensional structure unit connects as a half-bridge unit by splicing ear 22 with the collector electrode g3 of the 6th three-dimensional structure unit; The first, the 3rd, the 5th three-dimensional structure unit collector electrode e1, f1, g1 in three half-bridge unit are fixed on the positive terminal 20a of insulating base 17, the second, the 4th, that the emitter e 4 of the 6th three-dimensional structure unit, f4, g4 are fixed in the negative terminal 20b of insulating base 17 is upper, three groups of half-bridge unit are realized in parallel by positive terminal 20a and negative terminal 20b.
There is the electrode of metallization pattern on described insulating base 17 surfaces: positive terminal 20a, negative terminal 20b connect with the circuit of realizing a plurality of three-dimensional structures unit.
Below in conjunction with accompanying drawing, describe the structure of embodiments of the invention, the full-control type power semiconductor chip of this embodiment is IGBT, and not controlling the type power semiconductor chip is silicon-based diode or silicon carbide-based diode.
As shown in Figure 1a, described igbt chip collector electrode 10a3 and diode chip for backlight unit negative pole 10b2 are welded on the 3rd metal level collector electrode side 5a1 of the second substrate 5 by unleaded or leaded slicken solder;
As shown in Figure 1 b, the bottom surface of the 4th metallic gasket 11 and the 3rd metal level emitter side 5a2 welding.
As shown in Figure 1a, the grid 10a2 of igbt chip and the first metallic gasket 8a welding; The anodal 10b1 of igbt chip emitter 10a1, diode chip for backlight unit welds with the second metallic gasket 9a, the 3rd metallic gasket 9b respectively; The face bonding of the first metallic gasket 8a is connected to the second metal level gate electrode side 1c of the first substrate 1, and the end face of the second metallic gasket 9a, the 3rd metallic gasket 9b, the 4th metallic gasket 11 is welded in the second metal level emitter side 1c1 of the first substrate; The metal layer material of the first substrate 1 and the second substrate 5 is the alloy of copper ﹑ aluminium or copper, and electric insulation layer is aluminium oxide, and the highly heat-conductive materials such as aluminium nitride or silicon nitride are made, and between electric insulation layer and metal level, adopts sintering to connect.
As shown in Figure 4, the 3rd metal level 5a is split into two parts: the 3rd metal level collector electrode side 5a1 and the 3rd metal level emitter side 5a2.The collector electrode 10a3 welding of the 3rd metal level collector electrode side 5a1 and igbt chip, weld layer is 14a1; The 3rd metal level emitter side 5a2 is connected with the emitter 10a1 of igbt chip by the 4th metallic gasket 11; The 4th metallic gasket 11 and the 3rd metal level emitter side 5a2 pass through solder interconnections;
As shown in Figure 1a, the first metallic gasket 8a, the second metallic gasket 9a and the 3rd metallic gasket 9b weld with grid 10a2, the emitter 10a1 of igbt chip and the anodal 10b1 of diode chip for backlight unit respectively;
As shown in Figure 5, the grid 10a2 welding of described the first metallic gasket 8a and igbt chip, the second metal level gate electrode side 1c2 welding of the first metallic gasket 8a and the first substrate 1, the second metal level gate electrode side 1c2 of the first substrate 1 is connected by electric insulation layer plated-through hole 7c and the first metal layer gate electrode side 1a2's.The second metal level emitter side 1c1 welding of the second metallic gasket 9a, the 3rd metallic gasket, the 4th metallic gasket 11 and the first substrate 1, so realize the encapsulation of three-dimensional structure unit.
As shown in Figure 6 a, the three-dimensional structure unit of the present embodiment assembling power semiconductor modular is a kind of full bridge structure, is fixed on insulating base 17 by splicing ear 22 and nut 24 by six three-dimensional structure unit.Ac output end 19a, the 19b of three-dimensional structure unit assembling power semiconductor modular, 19c draw by the top exit 24 that outside terminal passes through the shell 16 of three-dimensional structure unit assembling power semiconductor modular, top exit 24 and ac output end 19a, the 19b of three-dimensional structure unit assembling power semiconductor modular, the hole encapsulation process between 19c.
As shown in Figure 6 b, the shell 16 of three-dimensional structure unit assembling power semiconductor modular is mounted with by the through hole 18 that rivet passes on insulating base 17 with insulating base 17, and shell 16 is processed by the sealing gap that contacts in assembling with insulating base 17.
It is cooling that the present invention passes into the insulating and cooling liquid body, can by the entrance 21a with this power semiconductor modular and outlet 21b, is connected and carry out the infiltration type heat radiation by external refrigerant compression equipment.
Claims (5)
1. the power semiconductor modular of a three-dimensional structure unit assembling, is characterized in that, described power semiconductor modular is comprised of a plurality of three-dimensional structures unit, and each three-dimensional structure unit is fixedly mounted on insulating base (17); The emitter of a three-dimensional structure unit is connected as a half-bridge unit with the collector electrode of another one three-dimensional structure unit by splicing ear, the unit parallel connection of a plurality of half-bridges;
Each three-dimensional structure unit is by full-control type power semiconductor chip (10a), do not control type power semiconductor chip (10b), the first substrate (1), the second substrate (5), the first metallic gasket (8a), the second metallic gasket (9a), and the 3rd metallic gasket (9b) form, the first metallic gasket (8a) is welded on the grid (10a2) of full-control type power semiconductor chip, the second metallic gasket (9a) is welded on the emitter (10a1) of full-control type power semiconductor chip, the 3rd metallic gasket (9b) is welded on the positive pole (10b1) of not controlling type power semiconductor chip (10b), described full-control type power semiconductor chip (10a) and do not control type power semiconductor chip (10b) and be positioned between the first substrate (1) and the second substrate (5), be arranged in juxtaposition,
Described the first substrate (1) is comprised of three-decker: be positioned at top the first metal layer (1a), be positioned at middle the first electric insulation layer (1b) and be positioned at following the second metal level (1c); Described the first metal layer (1a) forms two parts by etching technics: the first metal layer gate electrode side (1a2) and the first metal layer emitter side (1a1), not conducting between described the first metal layer emitter side (1a1) and the first metal layer gate electrode side (1a2); Described the second metal level (1c) forms two parts by etching technics: the second metal level gate electrode side (1c2) and the second metal level emitter side (1c1); The first metal layer gate electrode side (1a2) is corresponding up and down with the position of the second metal level gate electrode side (1c2), and the first metal layer emitter side (1a1) is upper and lower corresponding with the second metal level emitter side (1c1); The first electric insulation layer in the middle of being positioned at has a plated-through hole (7c), and the first metal layer gate electrode side (1a2) is connected by described plated-through hole (7c) with the second metal level gate electrode side (1c2); Electric insulation between the first metal layer emitter side (1a1) and the second metal level emitter side (1c1);
The grid (10a2) of full-control type power semiconductor chip (10a) is corresponding with the second metal level gate electrode side (1c2), and the emitter (10a1) of full-control type power semiconductor chip (10a), the positive pole (10b1) of not controlling the type power semiconductor chip are corresponding with the collector electrode side (1c1) of the second metal level;
The second substrate (5) forms by three layers: be positioned at the 3rd top metal level (5a), be positioned at middle the second electric insulation layer (5b) and be positioned at the 4th following metal level (5c); The 3rd metal level (5a) forms unconnected two parts by etching technics: the 3rd metal level collector electrode side (5a1) and the 3rd metal level emitter side (5a2), the 3rd metal level collector electrode side (5a1) and the 3rd not conducting of metal level emitter side (5a2).
2. power semiconductor modular according to claim 1 (6), is characterized in that, described the first metal layer (1a), the second metal level (1c) and the 3rd metal level (5a) all have circuit structure.
3. power semiconductor modular according to claim 1, it is characterized in that, the collector electrode (10a1) of described full-control type power semiconductor chip (10a), the negative pole (10b2) of not controlling the type power semiconductor chip are welded on the 3rd metal level emitter side (5a1); The emitter (10a1) of full-control type power semiconductor chip (10a), grid (10a2) and do not control positive pole (10b1) respectively with the first metallic gasket (8a), second metallic gasket (9a) of type power semiconductor chip, and the welding of the 3rd metallic gasket (9b); The first metallic gasket (8a) and the second metal level gate electrode side (1c2) welding, and be connected with the first metal layer gate electrode side (1a2) by metallization via hole (7c); The second metallic gasket (9a) and the 3rd metallic gasket (9b) and the second metal level emitter side (1c1) welding; The second metal level emitter side (1c1) is connected with the 3rd metal level emitter side (5a2) by the 4th metallic gasket (11).
4. power semiconductor modular according to claim 1, is characterized in that, the described type power semiconductor chip (10b) of not controlling is positioned at the side away from the grid (10a2) of full-control type power semiconductor chip (10a); Full-control type power semiconductor chip (10a), do not control type power semiconductor chip (10b) and align with the left side edge of the second substrate, the grid (10a2) of described full-control type power semiconductor chip (10a) is positioned at full-control type power semiconductor chip edge.
5. power semiconductor modular according to claim 1, it is characterized in that, it is cooling that described power semiconductor modular passes into the insulating and cooling liquid body, and external refrigerant compression equipment is by being connected and carrying out the infiltration type heat radiation with this power semiconductor modular entrance (21a) and outlet (21b).
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| CN201310323097.5A CN103413797B (en) | 2013-07-29 | 2013-07-29 | A kind of power semiconductor modular of three-dimensional structure unit assembling |
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| CN201310323097.5A CN103413797B (en) | 2013-07-29 | 2013-07-29 | A kind of power semiconductor modular of three-dimensional structure unit assembling |
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| CN109269667A (en) * | 2018-09-15 | 2019-01-25 | 国网福建省电力有限公司 | A kind of Novel IGBT device and preparation method thereof with real-time temperature test sytem |
| CN110911395A (en) * | 2018-09-17 | 2020-03-24 | 株洲中车时代电气股份有限公司 | Double-sided heat dissipation IGBT module |
| CN116230666A (en) * | 2023-05-05 | 2023-06-06 | 烟台台芯电子科技有限公司 | DBC double-sided micro-channel refrigeration IGBT module and manufacturing method thereof |
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| CN110911395A (en) * | 2018-09-17 | 2020-03-24 | 株洲中车时代电气股份有限公司 | Double-sided heat dissipation IGBT module |
| CN116230666A (en) * | 2023-05-05 | 2023-06-06 | 烟台台芯电子科技有限公司 | DBC double-sided micro-channel refrigeration IGBT module and manufacturing method thereof |
| CN116230666B (en) * | 2023-05-05 | 2023-08-08 | 烟台台芯电子科技有限公司 | DBC double-sided micro-channel refrigeration IGBT module and manufacturing method thereof |
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