CN103378820A - Programmable digital filtering implementation method, apparatus, baseband chip and terminal thereof - Google Patents
Programmable digital filtering implementation method, apparatus, baseband chip and terminal thereof Download PDFInfo
- Publication number
- CN103378820A CN103378820A CN2012101162343A CN201210116234A CN103378820A CN 103378820 A CN103378820 A CN 103378820A CN 2012101162343 A CN2012101162343 A CN 2012101162343A CN 201210116234 A CN201210116234 A CN 201210116234A CN 103378820 A CN103378820 A CN 103378820A
- Authority
- CN
- China
- Prior art keywords
- data
- configuration
- programmable digital
- multiply accumulating
- general purpose
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Complex Calculations (AREA)
Abstract
The invention discloses a programmable digital filtering implementation method, an apparatus, a baseband chip and a terminal thereof. The method comprises the steps of acquiring and storing a multiply-accumulate operation instruction; reading corresponding configuration data and a configuration coefficient that are stored in a general-purpose register block to user configuration according to the multiply-accumulate operation instruction; and carrying out a multiply-accumulate operation based on the configuration data and the configuration coefficient. The digital filtering device with microprocessor architecture can be used for achieving any multiply-accumulate operation. Especially in the multi-mode mobile terminal baseband processing, a set of filter resources is used for replacing different filter resources in multiple modes, so that the area of the device is greatly reduced. Different types of filter can be programmed flexibly, and through the processing of software radio, system resources can be saved and energy consumption can be reduced to some extent.
Description
Technical field
The present invention relates to digital signal processing technique field, in particular to a kind of programmable digital filter achieving method, device, baseband chip and terminal thereof.
Background technology
In communication system, commonly used to FIR (Finite Impulse Response, finite impulse response) filter and IIR (Infinite Impulse Response, digital filter) digital filter, wherein, the FIR filter is commonly used to do sampling and interpolation, and its mathematical formulae is as follows:
In addition, the time domain formula of iir filter is as follows:
4 can find out from formula 1 to formula, and iir filter and FIR filter all are take the multiply accumulating computing as main implementation, and wherein, the iir filter implementation is similar to the cascade filtering of FIR filter especially.This shows, no matter for low-pass filtering, high-pass filtering or bandpass filtering, present comb filter finally all is to carry out the multiply accumulating operation, therefore, for the hardware filtering device, the difference that realizes different filter functions is mainly reflected in different exponent numbers and coefficient is set, and can also realize by cascade system is set simultaneously.
Yet the coefficient of the hardware filtering device in the general baseband chip all solidifies, and can't reuse.And the implementation of these hardware filtering devices is all for realizing that by the multiply accumulating method it is larger to take resource in the operating process.Especially in the mobile communication multimode system, its filter type or function under different mode may be different, and its corresponding filter need take a resource separately, Given this, but how a kind of its coefficient, exponent number flexible configuration are provided, and the reusable universal filter of filter just becomes the technical problem of needing at present solution badly.
Summary of the invention
The object of the present invention is to provide a kind of programmable digital filter achieving method, device, baseband chip and terminal thereof, this programmable digital filter is based on little processing framework, but can realize coefficient, exponent number flexible configuration, and according to data and the corresponding transfer function realization multiply accumulating computings such as coefficient of described flexible configuration, and then realize that filter is reusable.In the present invention, each corresponding function of processing that the transfer function that multimode terminal adopts under corresponding pattern adopts prior art to provide gets final product, and the present invention does not do any type of restriction to this.
In order to realize purpose of the present invention, the present invention realizes by the following technical solutions:
A kind of programmable digital filter achieving method comprises:
Obtain and store the multiply accumulating operational order;
Read user configured corresponding configuration data and the configuration coefficients of storing in the general purpose register set according to this multiply accumulating operational order;
Carry out the multiply accumulating computing according to described configuration data and configuration coefficients.
Preferably, before obtaining and store the multiply accumulating operational order, described programmable digital filter achieving method also comprises:
Obtain and store the data load instructions;
Reconfigurations data and Reconfigurations coefficient according to input are loaded on memory location corresponding in the general purpose register set with it.
Preferably, when the Reconfigurations data of input when be plural, with corresponding being stored to respectively among two different registers in the general purpose register set of real part and the imaginary data of these Reconfigurations data.
Preferably, carrying out in the multiply accumulating calculating process according to described configuration data and configuration coefficients, can multiplier is repeatedly multiplexing.
A kind of programmable digital filtering implement device comprises:
The location of instruction is used for obtaining and storing the multiply accumulating operational order;
Processing unit is used for reading corresponding configuration data and the configuration coefficients that general purpose register set is stored according to this multiply accumulating operational order;
General purpose register set is used for storing user configured configuration data and configuration coefficients;
Arithmetic element is used for carrying out the multiply accumulating computing according to described configuration data and configuration coefficients.
Preferably, the described location of instruction also is used for obtaining and store the data load instructions, so that Reconfigurations data and the Reconfigurations coefficient of the input of described processing unit User are loaded on memory location corresponding in the general purpose register set with it.
Preferably, when the Reconfigurations data of user input when be plural, described processing unit is with corresponding being stored to respectively among two different registers in the general purpose register set of the real part of these Reconfigurations data and imaginary data.
Preferably, described arithmetic element is being carried out in the multiply accumulating calculating process according to described configuration data and configuration coefficients, can multiplier is repeatedly multiplexing.
A kind of baseband chip, it comprises CPU module and described programmable digital filtering implement device, wherein,
The CPU module is used for configuration multiply accumulating operational order;
Programmable digital filtering implement device, be used for after obtaining and store this multiply accumulating operational order, read corresponding configuration data and the configuration coefficients of storing in the general purpose register set according to this multiply accumulating operational order and also carry out the multiply accumulating computing according to described configuration data and configuration coefficients.
A kind of terminal, it comprises described baseband chip, wherein said baseband chip comprises CPU module and described programmable digital filtering implement device, wherein,
The CPU module is used for configuration multiply accumulating operational order;
Programmable digital filtering implement device, be used for after obtaining and store this multiply accumulating operational order, read corresponding configuration data and the configuration coefficients of storing in the general purpose register set according to this multiply accumulating operational order and also carry out the multiply accumulating computing according to described configuration data and configuration coefficients.
The present invention has broken through the concept of traditional hardware accelerator, a large amount of data operation Unit Designs is become microprocessor architecture, the data operation unit separates with control unit, adopt the digital filter apparatus of microprocessor architecture provided by the invention, can realize arbitrarily multiply accumulating computing, especially in the multi-module mobile terminal Base-Band Processing, use a cover filter resource to replace different filter resource under the various modes, so that area reduces greatly, but dissimilar filter flexible programming, and by the processing mode of this software radio, can save to a certain extent system resource and reduce energy consumption.
In addition, programmable digital filter achieving method provided by the invention can also be supported complex filter, the occupation mode external interface of real number and plural number only is embodied in the instruction, on hardware, do not bring extra register and the increase of calculation resources, can realize flexibly real filter and complex filter by programming.
Description of drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, consists of a part of the present invention, and illustrative examples of the present invention and explanation thereof are used for explaining the present invention, do not consist of improper restriction of the present invention.In the accompanying drawings:
Fig. 1 is the programmable digital filter achieving method schematic flow sheet that the embodiment of the invention provides;
Fig. 2 is the programmable digital filtering implement device structural representation that the embodiment of the invention provides;
Fig. 3 is the programmable digital filtering implement device resource placement schematic diagram that the embodiment of the invention provides;
Fig. 4 is the programmable digital filtering implement device work schedule schematic diagram that the embodiment of the invention provides;
Fig. 5 is the programmable digital filtering implement device vector registor schematic diagram that the embodiment of the invention provides;
Fig. 6 is real number and the location mode schematic diagram of complex filter in register that the embodiment of the invention provides;
Fig. 7 is real number and the compatible implementation schematic diagram of complex filter that the embodiment of the invention provides.
Embodiment
In order to make technical problem to be solved by this invention, technical scheme and beneficial effect clearer, clear, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
A kind of programmable digital filter achieving method that the embodiment of the invention provides as shown in Figure 1, comprises following concrete steps:
S103, obtain the multiply accumulating operational order;
S104, read user configured corresponding configuration data and the configuration coefficients of storing in the general purpose register set according to this multiply accumulating operational order;
S105, the described configuration data of foundation and configuration coefficients are carried out the multiply accumulating computing.
The programmable digital filter achieving method that adopts the invention described above embodiment to provide, its corresponding programmable digital filtering implement device adopts microprocessor architecture, filter is divided into control stream and data flow, control stream produces control signal by instruction set decoding, and reading out data flows to arithmetic element and finishes the multiply accumulating operation from the register group.
Wherein, the core of control stream is instruction set, and instruction set is the external avatar of this little processing framework.Major function has data load instructions, operational order (comprising real number and plural number), and instruction data storage.Use these instructions to realize arbitrarily digital filter, for example complex filter, cascading filter by flexible programming, and other forms of multiply accumulating data operation.
In embodiments of the present invention, can realize the compatible design of complex filter and real filter by this programmable digital filtering implement device, on the basis that does not increase register expense and arithmetic element, the combined command collection is by revising register data and coefficient, and add a selected cell 14 at the front end of arithmetic element, almost under the situation that does not increase extra any resource overhead, just can realize the compatible design of real number and complex filter.
Under the preferred implementation, continue with reference to Fig. 1, before obtaining the multiply accumulating operational order, described programmable digital filter achieving method also comprises:
S101, obtain and store the data load instructions;
Reconfigurations data and the Reconfigurations coefficient of S102, foundation input are loaded on memory location corresponding in the general purpose register set with it.
By above-mentioned steps S101 and S102, can carry out the configuration of data in the general purpose register set, thereby be the corresponding data of the filter configuration of multimode terminal under various patterns.In embodiments of the present invention, each corresponding function of processing that the transfer function that multimode terminal adopts under corresponding pattern adopts prior art to provide gets final product, and the present invention does not do any type of restriction to this.
Under the preferred implementation, when the Reconfigurations data of user input when be plural, with corresponding being stored to respectively among two different registers in the general purpose register set of real part and the imaginary data of these Reconfigurations data.As shown in Figure 5 and Figure 6, described general purpose register set is used for depositing data and the coefficient of multiply accumulating, coefficient is fixed later at loaded, and data are serial shifts, shift motion is to be produced after decoding by the instruction that gets access to, for simplified design, in filter when programming that takies a plurality of beats, should the inverted order programming, and the benefit of doing like this is that shifting function does not need to consider losing of end data.
Slightly change on the interface that is arranged in described general purpose register set of plural number, continuation is with reference to Fig. 6, under plural pattern, squeezing into of data flow is to squeeze into 2 data at every turn, is respectively real and imaginary part, external this difference only is embodied on the instruction set, higher bit is put real part, and low bit is put imaginary part, and real part is stored in first register, imaginary part is stored in second, and the rest may be inferred.Direct serial is squeezed under the real mode, not tabbing.
More preferably, carrying out in the multiply accumulating calculating process according to described configuration data and configuration coefficients, can multiplier is repeatedly multiplexing.
In actual mechanical process, arithmetic element is not distinguished complex multiplication or the multiplication of real number, and it is responsible for finishing multiplication and cumulative operation.As shown in Figure 7, for example: suppose under the complex filter pattern that data are A=Ar+jAi, the sampling coefficient is B=Br+jBi, so A*B=(ArBr-AiBi)+j (ArBi+AiBr).So, a complex multiplication needs 4 real multipliers to finish.In order to save multiplication resources, taked for two steps finished, at first calculate real part (ArBr-AiBi), then calculate imaginary part (ArBi+AiBr), like this by finishing the once multiply operation of plural number to twice of two multipliers is multiplexing.Corresponding instruction is as follows:
The real part result of VADD VD0VC0R // calculating VD0 and VC0 complex multiplication;
The imaginary part result of VADD VD0VC0I // calculating VD0 and VC0 complex multiplication.
As shown in Figure 2, the embodiment of the invention also provides a kind of programmable digital filtering implement device 1, comprising:
The location of instruction 10 is used for obtaining and storing the multiply accumulating operational order;
Processing unit 11 is used for reading corresponding configuration data and the configuration coefficients that general purpose register set is stored according to this multiply accumulating operational order;
General purpose register set 12 is used for storing user configured configuration data and configuration coefficients;
In order to improve clock frequency, the programmable digital filtering implement device 1 that the embodiment of the invention provides adopts the pipeline design, altogether 8 beats of flowing water, address generation, fetching, decoding, VAU1, VAU2, VNU1, VNU2, peek.Control stream and synchronization of data streams flowing water, 8 grades of flow beats can improve maximum clock frequency and the throughput of system greatly.
Wherein, the location of instruction 10 (can doublely make command memory) is deposited microcommand, the outer CPU module directly writes instruction and enable this programmable digital filtering implement device 1 (universal filter) by bus, and the location of instruction 10 sends this instruction and deciphers processing to processing unit 11.
Processing unit 11 produces control signal reading out data from general purpose register set 12 according to decode results, and the multiply accumulating computing of data and coefficient vector is responsible for finishing in control algorithm unit 13.
The normalized vector adder is responsible for the cumulative output of all multiplication results in the bat, and the cumulative delay of a plurality of numbers is longer, has adopted fast compression set here, so that frequency improves greatly.
As shown in Figure 3, programmable digital filtering implement device 1 resource placement's schematic diagram that it provides for the embodiment of the invention, horizontal and vertical product is exactly that a sampled point needs data volume to be processed, transverse width has determined a multiply accumulating data volume that beat arithmetic element 13 will be finished, vertical extension has determined multiplexing number, if the fastest sample rate is determined in the middle of a plurality of filter.The data volume that will finish within the unit interval has so just determined that the data volume of the narrower unit of so horizontal width beat computing is just less, so vertically will be longer, and multiplexing number will be larger, and the work clock of system requires just higher.One of them filter might take a plurality of beats, and this exponent number with this filter is relevant, and for example different colours represents a resource that filter is shared among the figure, can arbitrary disposition.
To sum up, programmable digital filtering implement device 1 its versatility of providing of the embodiment of the invention is embodied in following two aspects:
(1) in case the universal filter flow is ASIC (Application Specific Integrated Circuit), structure is solidified, and versatility can be by the configurable realization of instruction set and coefficient.
(2) IP kernel is customizable, no matter what application scenarios, can be according to demand and the actual scene size that decides the universal filter that will produce of oneself, and the scale of arithmetic element 13 and multiplexing number, be these those long relations that disappear between the two, obtain compromise according to actual conditions.
As shown in Figure 4, the programmable digital filtering implement device 1 work schedule schematic diagram that it provides for the embodiment of the invention, the calculating of each sampling point can take n (multiplexing number) system beat, and the sampling point of all filters calculates and finishes in this n beat.Support opening of filter to close, and reload new filter.
Preferably, the described location of instruction 10 also is used for obtaining and store the data load instructions, so that Reconfigurations data and the Reconfigurations coefficient of the input of described processing unit 11 Users are loaded on memory location corresponding in the general purpose register set 12 with it.As shown in Figure 5 and Figure 6, described general purpose register set 12 is used for depositing data and the coefficient of multiply accumulating, coefficient is fixed later at loaded, and data are serial shifts, shift motion is to be produced after decoding by the instruction that gets access to, for simplified design, in filter when programming that takies a plurality of beats, should the inverted order programming, and the benefit of doing like this is that shifting function does not need to consider losing of end data.
Slightly change on the interface that is arranged in described general purpose register set 12 of plural number, continuation is with reference to Fig. 6, under plural pattern, squeezing into of data flow is to squeeze into 2 data at every turn, is respectively real and imaginary part, external this difference only is embodied on the instruction set, higher bit is put real part, and low bit is put imaginary part, and real part is stored in first register, imaginary part is stored in second, and the rest may be inferred.Direct serial is squeezed under the real mode, not tabbing.
Preferably, when the Reconfigurations data of user input when be plural, described processing unit 11 is with corresponding being stored to respectively among two different registers in the general purpose register set 12 of the real part of these Reconfigurations data and imaginary data.
Preferably, described arithmetic element 13 is being carried out in the multiply accumulating calculating process according to described configuration data and configuration coefficients, can multiplier is repeatedly multiplexing.In actual mechanical process, arithmetic element 13 is not distinguished complex multiplication or the multiplication of real number, and it is responsible for finishing multiplication and cumulative operation.As shown in Figure 7, for example: suppose under the complex filter pattern that data are A=Ar+jAi, the sampling coefficient is B=Br+jBi, so A*B=(ArBr-AiBi)+j (ArBi+AiBr).So, a complex multiplication needs 4 real multipliers to finish.In order to save multiplication resources, taked for two steps finished, at first calculate real part (ArBr-AiBi), then calculate imaginary part (ArBi+AiBr), like this by finishing the once multiply operation of plural number to twice of two multipliers is multiplexing.
Correspondingly, the embodiment of the invention also provides a kind of baseband chip, and with reference to shown in Figure 2, it comprises CPU module and described programmable digital filtering implement device 1, wherein,
Programmable digital filtering implement device 1, be used for after obtaining and store this multiply accumulating operational order, read corresponding configuration data and the configuration coefficients of storage in the general purpose register set 12 according to this multiply accumulating operational order and also carry out the multiply accumulating computing according to described configuration data and configuration coefficients.
In the practical application, CPU module 2 is not constantly sending instruction in real time, CPU module 2 be disposable with instruction load after the location of instruction 10 of programmable digital filtering implement device 1, this programmable digital filtering implement device 1 will constantly be carried out from the location of instruction 10 instruction fetch circulation, until pattern when changing CPU module 2 reconfigure the location of instruction 10.
1 detailed design of described programmable digital filtering implement device please refer to technical scheme mentioned above, herein repeated description no longer.
Correspondingly, the embodiment of the invention also provides a kind of terminal, and it comprises described baseband chip, and wherein said baseband chip comprises CPU module 2 and described programmable digital filtering implement device 1, wherein,
Programmable digital filtering implement device 1, be used for after obtaining and store this multiply accumulating operational order, read corresponding configuration data and the configuration coefficients of storage in the general purpose register set 12 according to this multiply accumulating operational order and also carry out the multiply accumulating computing according to described configuration data and configuration coefficients.
In the practical application, CPU module 2 is not constantly sending instruction in real time, CPU module 2 be disposable with instruction load after the location of instruction 10 of programmable digital filtering implement device 1, this programmable digital filtering implement device 1 will constantly be carried out from the location of instruction 10 instruction fetch circulation, until pattern when changing CPU module 2 reconfigure the location of instruction 10.
Similarly, 1 detailed design of described programmable digital filtering implement device please refer to technical scheme mentioned above, herein repeated description no longer.
Above-mentioned explanation illustrates and has described a preferred embodiment of the present invention, but as previously mentioned, be to be understood that the present invention is not limited to the disclosed form of this paper, should not regard the eliminating to other embodiment as, and can be used for various other combinations, modification and environment, and can in invention contemplated scope described herein, change by technology or the knowledge of above-mentioned instruction or association area.And the change that those skilled in the art carry out and variation do not break away from the spirit and scope of the present invention, then all should be in the protection range of claims of the present invention.
Claims (10)
1. a programmable digital filter achieving method is characterized in that, comprising:
Obtain and store the multiply accumulating operational order;
Read user configured corresponding configuration data and the configuration coefficients of storing in the general purpose register set according to this multiply accumulating operational order;
Carry out the multiply accumulating computing according to described configuration data and configuration coefficients.
2. programmable digital filter achieving method as claimed in claim 1 is characterized in that, before obtaining and store the multiply accumulating operational order, also comprises:
Obtain and store the data load instructions;
Reconfigurations data and Reconfigurations coefficient according to input are loaded on memory location corresponding in the general purpose register set with it.
3. programmable digital filter achieving method as claimed in claim 2, it is characterized in that, when the Reconfigurations data of input when be plural, with corresponding being stored to respectively among two different registers in the general purpose register set of real part and the imaginary data of these Reconfigurations data.
4. programmable digital filter achieving method as claimed in claim 1 is characterized in that, is carrying out in the multiply accumulating calculating process according to described configuration data and configuration coefficients, can multiplier is repeatedly multiplexing.
5. a programmable digital filtering implement device is characterized in that, comprising:
The location of instruction is used for obtaining and storing the multiply accumulating operational order;
Processing unit is used for reading corresponding configuration data and the configuration coefficients that general purpose register set is stored according to this multiply accumulating operational order;
General purpose register set is used for storing user configured configuration data and configuration coefficients;
Arithmetic element is used for carrying out the multiply accumulating computing according to described configuration data and configuration coefficients.
6. programmable digital filtering implement device as claimed in claim 5, it is characterized in that, the described location of instruction also is used for obtaining and storing the data load instructions, so that Reconfigurations data and the Reconfigurations coefficient of described processing unit User input are loaded on memory location corresponding in the general purpose register set with it.
7. programmable digital filtering implement device as claimed in claim 6, it is characterized in that, when the Reconfigurations data of user input when be plural, described processing unit is with corresponding being stored to respectively among two different registers in the general purpose register set of the real part of these Reconfigurations data and imaginary data.
8. programmable digital filtering implement device as claimed in claim 5 is characterized in that, described arithmetic element is being carried out in the multiply accumulating calculating process according to described configuration data and configuration coefficients, can multiplier is repeatedly multiplexing.
9. a baseband chip is characterized in that, comprises the CPU module and such as the described programmable digital filtering of the arbitrary claim of claim 5-8 implement device, wherein,
The CPU module is used for configuration multiply accumulating operational order;
Programmable digital filtering implement device, be used for after obtaining and store this multiply accumulating operational order, read corresponding configuration data and the configuration coefficients of storing in the general purpose register set according to this multiply accumulating operational order and also carry out the multiply accumulating computing according to described configuration data and configuration coefficients.
10. a terminal is characterized in that, comprises baseband chip as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101162343A CN103378820A (en) | 2012-04-19 | 2012-04-19 | Programmable digital filtering implementation method, apparatus, baseband chip and terminal thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101162343A CN103378820A (en) | 2012-04-19 | 2012-04-19 | Programmable digital filtering implementation method, apparatus, baseband chip and terminal thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103378820A true CN103378820A (en) | 2013-10-30 |
Family
ID=49463457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101162343A Pending CN103378820A (en) | 2012-04-19 | 2012-04-19 | Programmable digital filtering implementation method, apparatus, baseband chip and terminal thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103378820A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104866461A (en) * | 2014-02-21 | 2015-08-26 | 北京国睿中数科技股份有限公司 | Floating point complex number i-multiplying addition-subtraction device and floating point complex number i-multiplying addition-subtraction method |
| CN105099395A (en) * | 2014-05-19 | 2015-11-25 | 深圳市欧克蓝科技有限公司 | Configurable digital filter device |
| CN106656103A (en) * | 2015-11-03 | 2017-05-10 | 深圳市中兴微电子技术有限公司 | FIR filter bank and filtering method |
| CN109035980A (en) * | 2018-08-29 | 2018-12-18 | 白舜 | A kind of general register operation sheet formula programing system and operation method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992517A (en) * | 2005-12-26 | 2007-07-04 | 中兴通讯股份有限公司 | Programmable interpolated filter device and realizing method therefor |
| CN101330283A (en) * | 2008-07-29 | 2008-12-24 | 中兴通讯股份有限公司 | Method and system for implementing digital filter based on programmable logic structure |
| US20080315940A1 (en) * | 2007-06-19 | 2008-12-25 | Nec Electronics Corporation | Mixing device for plural digital data having different sampling rates |
| CN101661407A (en) * | 2009-09-30 | 2010-03-03 | 中兴通讯股份有限公司 | Finite impulse response filter with parallel structure and processing method thereof |
-
2012
- 2012-04-19 CN CN2012101162343A patent/CN103378820A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992517A (en) * | 2005-12-26 | 2007-07-04 | 中兴通讯股份有限公司 | Programmable interpolated filter device and realizing method therefor |
| US20080315940A1 (en) * | 2007-06-19 | 2008-12-25 | Nec Electronics Corporation | Mixing device for plural digital data having different sampling rates |
| CN101330283A (en) * | 2008-07-29 | 2008-12-24 | 中兴通讯股份有限公司 | Method and system for implementing digital filter based on programmable logic structure |
| CN101661407A (en) * | 2009-09-30 | 2010-03-03 | 中兴通讯股份有限公司 | Finite impulse response filter with parallel structure and processing method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104866461A (en) * | 2014-02-21 | 2015-08-26 | 北京国睿中数科技股份有限公司 | Floating point complex number i-multiplying addition-subtraction device and floating point complex number i-multiplying addition-subtraction method |
| CN104866461B (en) * | 2014-02-21 | 2018-03-02 | 北京国睿中数科技股份有限公司 | Multiply the apparatus and method of i plus-minuss for floating-point complex |
| CN105099395A (en) * | 2014-05-19 | 2015-11-25 | 深圳市欧克蓝科技有限公司 | Configurable digital filter device |
| CN106656103A (en) * | 2015-11-03 | 2017-05-10 | 深圳市中兴微电子技术有限公司 | FIR filter bank and filtering method |
| WO2017075868A1 (en) * | 2015-11-03 | 2017-05-11 | 深圳市中兴微电子技术有限公司 | Fir filter bank and filtering method |
| CN106656103B (en) * | 2015-11-03 | 2019-07-19 | 深圳市中兴微电子技术有限公司 | A kind of FIR filter group and filtering method |
| CN109035980A (en) * | 2018-08-29 | 2018-12-18 | 白舜 | A kind of general register operation sheet formula programing system and operation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7353516B2 (en) | Data flow control for adaptive integrated circuitry | |
| CN104899182B (en) | A kind of Matrix Multiplication accelerated method for supporting variable partitioned blocks | |
| US9792118B2 (en) | Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods | |
| US8296764B2 (en) | Internal synchronization control for adaptive integrated circuitry | |
| CN109711533B (en) | Convolutional neural network acceleration system based on FPGA | |
| JP2007166535A5 (en) | ||
| CN110262773A (en) | A kind of And Methods of Computer Date Processing and device | |
| Ferreira et al. | An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture | |
| CN103378820A (en) | Programmable digital filtering implementation method, apparatus, baseband chip and terminal thereof | |
| JP2009507423A (en) | Programmable digital filter configuration of shared memory and shared multiplier | |
| CN103956991B (en) | A kind of FIR filtering Parallel Realization methods based on CPU/GPU heterogeneous platforms | |
| CN115880132B (en) | Graphics processor, matrix multiplication task processing method, device and storage medium | |
| CN102739195A (en) | Processing method, device and system of FIR (finite impulse response) filter | |
| CN113556101B (en) | IIR filter and data processing method thereof | |
| CN101072019B (en) | Wave filter and its filtering method | |
| KR20220107287A (en) | Data processing apparatus, method, base station and storage medium | |
| CN105720944B (en) | General FIR filter and its configuration method | |
| CN204316468U (en) | A kind of multi-path digital filter | |
| CN108595149A (en) | Restructural multiply-add operation device | |
| CN103345379A (en) | Complex number multiplying unit and realizing method thereof | |
| CN103235717B (en) | There is the processor of polymorphic instruction set architecture | |
| WO2002069492A2 (en) | System and method for a highly-programmable fir filter | |
| CN102457251B (en) | Method and device for realizing universal digital filter | |
| CN102231624B (en) | Vector processor-oriented floating point complex number block finite impulse response (FIR) vectorization realization method | |
| KR20210131417A (en) | data processing unit and artificial intelligence chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20151026 Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518085 Building No. 1 Applicant after: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Applicant before: ZTE Corporation |
|
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20131030 |
|
| RJ01 | Rejection of invention patent application after publication |