CN104866461B - Multiply the apparatus and method of i plus-minuss for floating-point complex - Google Patents
Multiply the apparatus and method of i plus-minuss for floating-point complex Download PDFInfo
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- CN104866461B CN104866461B CN201410060269.9A CN201410060269A CN104866461B CN 104866461 B CN104866461 B CN 104866461B CN 201410060269 A CN201410060269 A CN 201410060269A CN 104866461 B CN104866461 B CN 104866461B
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Abstract
The invention discloses a kind of apparatus and method for multiplying i plus-minuss for floating-point complex, the wherein device includes：Data memory module, data selecting module, computing module and control module, wherein, data memory module, data memory module includes multiple vector registors, each vector registor is used to preserve multiple floating-point complex, wherein, each floating-point complex includes one as the floating number of real part and a floating number as imaginary part.The device of the present invention can utilize existing vector operation part, realize and the complex data commonly used in communication system applications is carried out to multiply the tired plus and minus calculations of i, overcome the shortcomings of that traditional vector mode to vectorial complex data disposal ability, improves the concurrency of computing mode, saves hardware resource.
Description
Technical field
The present invention relates to micro-processor architecture technical field, more particularly to a kind of floating-point complex that is used for multiply i plus-minuss
Apparatus and method.
Background technology
With the fast development of digital communication technology, the requirement to digital signal processing capability also transport by more and more higher, vector
The concurrency using hardware is calculated, the processing procedure of data signal can be greatly accelerated, applies to digital communication neck more and more
In domain.
At present, widely used signal processing technology is orthogonal frequency division multiplexi in communication, can be by breaking a channel into
Some orthogonal subchannels, reduce interfering for interchannel, and it is possible to allow each subcarrier to have part in frequency range
It is overlapping, so as to improve bandwidth availability ratio.Because plural number can include mutually incoherent real part and imaginary part, just it is adapted to represent orthogonal
I roads and Q roads data, therefore in the application of OFDM, many data can use plural form to record.
The characteristics of vector operation is can to carry out same arithmetic operation to multiple data simultaneously, and improve computing performs effect
Rate.At present in digital signal processing, Fast Fourier Transform (FFT)（Fast Fourier Transformation, FFT）Have non-
Normal consequence, while in many ambits such as " matheematical equation ", " Linear System Analysis ", " signal transacting, emulation " all
Extensive application.And multiply the important calculating process that i plus-minus operations are FFT computings.But if using it is traditional to
Measure computing mode, it is impossible to give full play to the superiority of vector operation, even result in reduction operation efficiency.
The content of the invention
It is contemplated that at least solves one of above-mentioned technical problem.
Therefore, first purpose of the present invention is to propose a kind of device for multiplying i plus-minuss for floating-point complex.The device can
With.
Second object of the present invention is to propose a kind of method for multiplying i plus-minuss for floating-point complex.
To achieve these goals, the device for being used for floating-point complex and multiplying i plus-minuss of the embodiment of the present invention, including：Data are deposited
Module, data selecting module, computing module and control module are stored up, wherein, the data memory module, the data memory module
Including multiple vector registors, each vector registor is used to preserve multiple floating-point complex, wherein, each floating-point is answered
Number is comprising one as the floating number of real part and a floating number as imaginary part；The data selecting module, for respectively from
The real part floating number and imaginary part floating number of floating-point complex described in two groups are read in two vector registors respectively, as input
Data are sent to the computing module；The computing module, for the input data sent to the data selecting module
Carry out corresponding computing；The control module, for receiving operation information, control signal is generated according to the operation information, and
The data selecting module and the computing module is controlled to carry out corresponding data selection operation and fortune according to the control signal
Calculate operation；And the data memory module is additionally operable to preserve the operation result of the computing module.
The device for being used for floating-point complex and multiplying i plus-minuss according to embodiments of the present invention, is computing mould by data selecting module
Block provides different data so as to realize that the i that multiplies of floating-point complex tires out plus and minus calculation, can be directed to what is commonly used in communication system applications
Complex data carries out multiplying the tired plus and minus calculations of i, overcomes deficiency of traditional vector mode to vectorial complex data disposal ability,
The concurrency of computing mode is improved, existing vector operation part is made full use of, saves hardware resource.
To achieve these goals, the method for being used for floating-point complex and multiplying i plus-minuss of the embodiment of the present invention, including：Preserve more
Individual floating-point complex, wherein, each floating-point complex includes one as the floating number of real part and a floating-point as imaginary part
Number；Operation information is received, and control signal is generated according to the operation information；Two different floating-point complex are read respectively
Real part floating number and imaginary part floating number as input data；And phase is carried out to the input data according to the control signal
The arithmetic operation answered, preserve operation result.
The method for being used for floating-point complex and multiplying i plus-minuss according to embodiments of the present invention is different by being provided for computing module
Data can be directed to the complex data commonly used in communication system applications and carry out so as to realize that the i that multiplies of floating-point complex tires out plus and minus calculation
Multiply i and tire out plus and minus calculation, overcome deficiency of traditional vector mode to vectorial complex data disposal ability, improve computing side
The concurrency of formula, existing vector operation part is made full use of, saves hardware resource.
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
Of the invention above-mentioned and/or additional aspect and advantage will become from the following description of the accompanying drawings of embodiments
Substantially and it is readily appreciated that, wherein,
Fig. 1 is the structured flowchart of the device according to an embodiment of the invention for multiplying i plus-minuss for floating-point complex；
Fig. 2 is the operation principle schematic diagram of the device according to an embodiment of the invention for multiplying i plus-minuss for floating-point complex；
Fig. 3 is the computing schematic diagram of single-precision floating point CM i additions according to an embodiment of the invention；
Fig. 4 is the computing schematic diagram of double-precision floating point CM i additions according to an embodiment of the invention；And
Fig. 5 is the flow chart of the method according to an embodiment of the invention for multiplying i plus-minuss for floating-point complex.
Embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, is only used for explaining the present invention, and is not considered as limiting the invention.On the contrary, this
All changes that the embodiment of invention includes falling into the range of the spirit and intension of attached claims, modification and equivalent
Thing.
In the description of the invention, it is to be understood that term " first ", " second " etc. are only used for describing purpose, without
It is understood that to indicate or implying relative importance.In the description of the invention, it is necessary to which explanation, is provided unless otherwise clear and definite
And restriction, term " connected ", " connection " should be interpreted broadly, for example, it may be fixedly connected or be detachably connected,
Or it is integrally connected；Can be mechanical connection or electrical connection；Can be joined directly together, intermediary can also be passed through
It is indirectly connected.For the ordinary skill in the art, the tool of above-mentioned term in the present invention can be understood with concrete condition
Body implication.In addition, in the description of the invention, unless otherwise indicated, " multiple " are meant that two or more.
Any process or method described otherwise above description in flow chart or herein is construed as, and represents to include
Module, fragment or the portion of the code of the executable instruction of one or more the step of being used to realize specific logical function or process
Point, and the scope of the preferred embodiment of the present invention includes other realization, wherein can not press shown or discuss suitable
Sequence, including according to involved function by it is basic simultaneously in the way of or in the opposite order, carry out perform function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
Below with reference to the accompanying drawings the description apparatus and method for being used for floating-point complex and multiplying i plus-minuss according to embodiments of the present invention.
Fig. 1 is the structured flowchart of the device according to an embodiment of the invention for multiplying i plus-minuss for floating-point complex.
As shown in figure 1, this be used for floating-point complex multiply i plus-minus device can include data memory module 100, data select
Module 200, computing module 300 and control module 400.
Specifically, data memory module 100 may include multiple vector registors 110, and each vector registor 110 can be used for
Multiple floating-point complex are preserved, wherein, each floating-point complex can include one as the floating number of real part and one as imaginary part
Floating number.
In an embodiment of the present invention, the data type of each floating number can be divided into single precision type and type double precision,
Each single precision floating datum is 32, and each double-precision floating pointses are 64.
Further, in an embodiment of the present invention, the real part floating number of each floating-point complex and imaginary part floating number can protect
Exist in same vector registor 110, and the floating-point complex in different vector registors 110 can be read simultaneously, and may be used also
Sequentially successively to be read.
Further, in an embodiment of the present invention, a floating number is that the real part of floating-point complex or imaginary part can be by them
Position in vector data determine that and the floating number does not include the mark of imaginary part or real part in itself.Wherein, each floating-point is answered
Several real part floating numbers and the save location of imaginary part floating number are fixed, represent that real part or imaginary part are protected without special flag bit
Which position of vector registor 110 be present.
Data selecting module 200 can be used for the real part floating-point for reading floating-point complex from two vector registors 110 respectively
Number and imaginary part floating number, and sent as input data to computing module 300.Wherein, in an embodiment of the present invention, data are selected
Selecting module 200 may include multiple data selectors 210（Not shown in figure）, the structure all same of each data selector 210.Fortune
Module 300 is calculated to can be used for carrying out corresponding computing to the input data that data selecting module 200 is sent.Wherein, the present invention's
In embodiment, computing module 300 may include multiple arithmetic units 310, and each arithmetic unit can be divided into multiple computing submodules 311, often
Individual computing submodule 311 can be 64.The number of data selector 210 can be 2 times of 310 numbers of arithmetic unit, arithmetic unit 310
Number can be identical with the number of floating number in each vector registor 110.
More specifically, data selecting module 200 can first read two groups of operations that require calculation from vector registor 110
Data, this two groups of data from different vector registors, can from this two groups of data by the real part of each floating-point complex and
Imaginary component be you can well imagine and be taken out, and the data extracted are combined into one group of be sent to arithmetic unit 310 two two-by-two according to default
Data input pin.Arithmetic unit 310 can carry out two single precision floating datums or one to the input data that data selecting module 200 is sent
The signed magnitude arithmetic(al) of individual double-precision floating pointses.Wherein, the structure of each arithmetic unit 310 is identical.
It should be appreciated that data selecting module 200 can select different data to make according to the arithmetic type of required progress
Posted for the input data of arithmetic unit 310, such as the even bit data read in first vector registor with second vector
Odd bits data in storage are sent in same computing submodule 310 as input data, you can are realized floating to first
Imaginary part of counting and the arithmetic operation of the second floating number real part.
Control module 400 can be used for receiving operation information, and generate control signal according to operation information, and according to control
Signal distinguishes control data selecting module 200 and computing module 300 carries out corresponding data selection operation and arithmetic operation.Its
In, in an embodiment of the present invention, control signal may include that single precision floating datum multiplies i add operations, single precision floating datum multiplies i and subtracted
Method operation, double-precision floating pointses multiply i add operations and double-precision floating pointses multiply any one in i subtractions operation etc..
More specifically, control module 400 can generate control signal according to the operation information that receives, for example, being to do to multiply i and add
Method operation still multiplies the operation of i subtractions, is the relevant control signal such as single precision arithmetic or double-precision arithmetic.
Further, in an embodiment of the present invention, control module 400 can be specifically used for determining data according to control signal
The data selector channel of selecting module 200 and the mode of operation of computing module 300.Wherein, mode of operation may include two 32
Any one in single precision floating datum operation pattern and 64 double-precision floating pointses operation pattern etc..
In an embodiment of the present invention, data memory module 100 can be additionally used in the operation result for preserving computing module 300.
It is illustrated in figure 2 the operation principle signal for being used for floating-point complex and multiplying the device of i plus-minuss of one embodiment of the invention
Figure.
Further, in an embodiment of the present invention, when control signal is that single precision floating datum multiplies the operation of i plus/minus, control
Molding block 400 can control data selecting module 200 read respectively from two vector registors the first single precision real part floating number,
First single precision imaginary part floating number and the second single precision real part floating number, the second single precision imaginary part floating number, and control operator
Module 310 carries out the operation of single-precision floating point plus/minus method to the first single precision imaginary part floating number and the second single precision real part floating number,
And single-precision floating point is carried out to the first single precision real part floating number and the second single precision imaginary part floating number and subtracts/add operation.More
Specifically, in one particular embodiment of the present invention, one group of floating-point complex is stored in two vector registors 110 respectively, and
Acquiescence is alternately arranged each unit of deposit according to real part imaginary part, for example, as shown in figure 3, one required calculation to
The single-precision floating point plural number measured in register 110 is respectively (x6+x7i)、(x4+x5i)、(x2+x3i)、(x0+x1I), another
Single-precision floating point plural number in vector registor 110 is respectively (y6+y7i)、(y4+y5i)、(y2+y3i)、(y0+y1i).It is assumed that work as
Before need complete single-precision floating point vector multiply i add operations, data selecting module 200 can be read in first vector registor
Front two x7、x6With the front two y in second vector registor7、y6, and combined crosswise is sent into two different computing submodules
Block 310, to y7、x6Add operation is carried out, to y6、x7Carry out subtraction operation, by that analogy, to the real parts of two groups of floating-point complex and
Imaginary part alternate combinations are mutually added and subtracted, and by obtained operation result according to original storage order deposit data memory module 100
In vector registor 110, its operating result is（y6-x7）+(y7+x6)i、（y4-x5）+(y5+x4)i、（y2-x3）+(y3+x2)i、
（y0-x1）+(y1+x0)i。
When control signal be double-precision floating pointses multiply i plus/minus operation when, control module control data selecting module respectively from
The first double precision imaginary part floating number and the second double precision real part floating number are read in two vector registors, and controls computing submodule
Block carries out double-precision floating point plus/minus method to the first double precision imaginary part floating number and the second double precision real part floating number and operated, and
The first double precision real part floating number and the second double precision imaginary part floating number are read, and controls computing submodule 310 to first pair of essence
Degree real part floating number carries out double-precision floating point with the second double precision imaginary part floating number and subtracts/add operation.More specifically, in the present invention
A specific embodiment in, store one group of floating-point complex in two vector registors 110 respectively, and give tacit consent to according to real part imaginary part
The each unit of deposit is alternately arranged, for example, as shown in figure 4, double essences in the vector registor to require calculation
It is respectively (x to spend floating-point complex2+x3i)、(x0+x1I), the double-precision floating point plural number in another vector registor is respectively (y2
+y3i)、(y0+y1i).It is assumed that being currently needed for completion double-precision floating point vector multiplies i add operations, data selecting module 200 can be read
Second x in first vector registor2With first y in second vector registor3, and combine and be sent into computing submodule
Block 310 carries out add operation, then reads the second y in second vector registor2In second vector registor
First x3Combination is sent into computing submodule 310 and carries out subtraction operation, by that analogy, to the real and imaginary parts of two groups of floating-point complex
Alternately plus-minus is carried out, then obtained operation result is stored in the vector for preserving operation result according to original storage order
In register 110, its operating result is（y2-x3）+(y3+x2)i、（y0-x1）+(y1+x0)i。
The device for being used for floating-point complex and multiplying i plus-minuss of the embodiment of the present invention, is carried by data selecting module for computing module
For different data so as to realize that the i that multiplies of floating-point complex tires out plus and minus calculation, the plural number commonly used in communication system applications can be directed to
Data carry out multiplying the tired plus and minus calculations of i, overcome deficiency of traditional vector mode to vectorial complex data disposal ability, improve
The concurrency of computing mode, makes full use of existing vector operation part, saves hardware resource.
In order to realize above-described embodiment, the present invention also proposes a kind of method for multiplying i plus-minuss for floating-point complex.
Fig. 5 is the flow chart of the method according to an embodiment of the invention for multiplying i plus-minuss for floating-point complex.Need to illustrate
, in an embodiment of the present invention, vector registor, data selector and computing submodule can be multiple, and operator
The number of module is equal with the number of the floating number in each vector registor.
As shown in figure 5, the method for multiplying i plus-minuss for floating-point complex may comprise steps of：
S501, multiple floating-point complex are preserved, wherein, each floating-point complex includes one as the floating number of real part and one
Floating number as imaginary part.
Specifically, data memory module can preserve multiple floating-point complex, wherein, data memory module is posted including multiple vectors
Storage, each floating-point complex include one as the floating number of real part and a floating number as imaginary part.The one of the present invention
In individual embodiment, the data type of each floating number can be divided into single precision type and type double precision, each single precision floating datum
For 32, each double-precision floating pointses are 64.
In an embodiment of the present invention, the real part floating number of each floating-point complex and imaginary part floating number can be stored in same
In vector registor, and the floating-point complex in different vector registors can be read simultaneously, can also be sequentially by elder generation
After read.
In an embodiment of the present invention, a floating number is that the real part of floating-point complex or imaginary part can be by them in vectorial number
Position in determines, and the floating number does not include the mark of imaginary part or real part in itself.Wherein, the real part of each floating-point complex floats
The save location of points and imaginary part floating number is fixed, represents that real part or imaginary part are stored in vector and posted without special flag bit
Which position of storage.
S502, operation information is received, and control signal is generated according to operation information.
Wherein, in an embodiment of the present invention, control signal may include that single precision floating datum multiplies i add operations, single precision
Floating number multiplies the operation of i subtractions, double-precision floating pointses multiply i add operations and double-precision floating pointses multiply it is any in i subtractions operation etc.
It is a kind of.
Specifically, control module can generate control signal according to the operation information received, for example, being to do to multiply i additions behaviour
Still multiply the operation of i subtractions, be the relevant control signal such as single precision arithmetic or double-precision arithmetic.
S503, the real part floating number of two different floating-point complex of reading and imaginary part floating number are as input data respectively.
Specifically, data selecting module can first read the data of two groups of operations that require calculation from vector registor,
This two groups of data can distinguish the real and imaginary parts of each floating-point complex from this two groups of data from different vector registors
Extract, and the data extracted are combined into one group of two data input pin for being sent to arithmetic unit two-by-two according to default.
Arithmetic unit can carry out two single precision floating datums or double-precision floating points to the input data that data selecting module is sent
Signed magnitude arithmetic(al).Wherein, the structure of each arithmetic unit is identical.
It should be appreciated that data selecting module can select different data as fortune according to the arithmetic type of required progress
The input data of device is calculated, such as is read in the even bit data and second vector registor in first vector registor
Odd bits data are sent in same computing submodule as input data, you can are realized to the first floating number imaginary part and the
The arithmetic operation of two floating number real parts.The input data that computing module is sent to data selecting module carries out corresponding computing.
S504, corresponding arithmetic operation is carried out to input data according to control signal, and preserve operation result.
Specifically, control module receives operation information, and generates control signal according to operation information, is then believed according to control
Number difference control data selecting module and computing module carry out corresponding data selection operation and arithmetic operation, and by computing module
The operation result of output is stored in the vector registor for preserving operation result according to original storage order.
Further, in one embodiment of the invention, corresponding computing is carried out to input data according to control signal
Operation specifically includes：
When control signal is that single precision floating datum multiplies the operation of i plus/minus, control module can control data selecting module difference
It is real that the first single precision real part floating number, the first single precision imaginary part floating number and the second single precision are read from two vector registors
Portion's floating number, the second single precision imaginary part floating number, and control computing submodule single to the first single precision imaginary part floating number and second
Precision real part floating number carries out the operation of single-precision floating point plus/minus method, and to the first single precision real part floating number and second single essence
Degree imaginary part floating number carries out single-precision floating point and subtracts/add operation.More specifically, in one particular embodiment of the present invention, two
One group of floating-point complex is stored in individual vector registor respectively, and gives tacit consent to and is alternately arranged each unit of deposit according to real part imaginary part, is lifted
For example, as shown in figure 3, the single-precision floating point plural number in the vector registor to require calculation is respectively (x6+x7i)、
(x4+x5i)、(x2+x3i)、(x0+x1I), the single-precision floating point plural number in another vector registor is respectively (y6+y7i)、
(y4+y5i)、(y2+y3i)、(y0+y1i).It is assumed that being currently needed for completion single-precision floating point vector multiplies i add operations, data selection mould
The front two x in first vector registor can be read in block 2007、x6With the front two y in second vector registor7、y6, and
Combined crosswise is sent into two different computing submodules 310, to y7、x6Add operation is carried out, to y6、x7Subtraction operation is carried out, with
This analogizes, and the real and imaginary parts alternate combinations of two groups of floating-point complex are mutually added and subtracted, and by obtained operation result according to original
In the vector registor 110 of storage order deposit data memory module 100, its operating result is（y6-x7）+(y7+x6)i、（y4-
x5）+(y5+x4)i、（y2-x3）+(y3+x2)i、（y0-x1）+(y1+x0)i。
When control signal be double-precision floating pointses multiply i plus/minus operation when, control module control data selecting module respectively from
The first double precision imaginary part floating number and the second double precision real part floating number are read in two vector registors, and controls computing submodule
Block carries out double-precision floating point plus/minus method to the first double precision imaginary part floating number and the second double precision real part floating number and operated, and
The first double precision real part floating number and the second double precision imaginary part floating number are read, and controls computing submodule real to the first double precision
Portion's floating number carries out double-precision floating point with the second double precision imaginary part floating number and subtracts/add operation.More specifically, the one of the present invention
In individual specific embodiment, one group of floating-point complex is stored in two vector registors respectively, and gives tacit consent to and is alternately arranged according to real part imaginary part
Row are stored in each unit.For example, as shown in figure 4, double-precision floating point in the vector registor to require calculation
Plural number is respectively (x2+x3i)、(x0+x1I), the double-precision floating point plural number in another vector registor is respectively (y2+y3i)、
(y0+y1i).It is assumed that be currently needed for completing double-precision floating point vector multiplying i add operations, data selecting module can be read first to
Measure the second x in register2With first y in second vector registor3, and combine feeding computing submodule and added
Method operates, and then reads the second y in second vector registor2With first x in second vector registor3Combination
It is sent into computing submodule and carries out subtraction operation, by that analogy, alternately plus-minus is carried out to the real and imaginary parts of two groups of floating-point complex, so
Obtained operation result is stored in the vector registor for preserving operation result according to original storage order afterwards, it is operated
As a result it is（y2-x3）+(y3+x2)i、（y0-x1）+(y1+x0)i。
The method for being used for floating-point complex and multiplying i plus-minuss according to embodiments of the present invention, can utilize existing vector operation portion
Part, realize and the complex data commonly used in communication system applications is carried out to multiply the tired plus and minus calculations of i, overcome traditional vector mode pair
The deficiency of vectorial complex data disposal ability, the concurrency of computing mode is improved, save hardware resource.
It should be appreciated that each several part of the present invention can be realized with hardware, software, firmware or combinations thereof.Above-mentioned
In embodiment, software that multiple steps or method can be performed in memory and by suitable instruction execution system with storage
Or firmware is realized.If, and in another embodiment, can be with well known in the art for example, realized with hardware
Any one of row technology or their combination are realized：With the logic gates for realizing logic function to data-signal
Discrete logic, have suitable combinational logic gate circuit application specific integrated circuit, programmable gate array（PGA）, scene
Programmable gate array（FPGA）Deng.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description
Point is contained at least one embodiment or example of the present invention.In this manual, to the schematic representation of above-mentioned term not
Necessarily refer to identical embodiment or example.Moreover, specific features, structure, material or the feature of description can be any
One or more embodiments or example in combine in an appropriate manner.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Not
In the case of departing from the principle and objective of the present invention a variety of change, modification, replacement and modification can be carried out to these embodiments, this
The scope of invention is limited by claim and its equivalent.
Claims (6)
- A kind of 1. device for multiplying i plus-minuss for floating-point complex, it is characterised in that including：Data memory module, data selection mould Block, computing module and control module, wherein,The data memory module, the data memory module include multiple vector registors, and each vector registor is used In the multiple floating-point complex of preservation, wherein, each floating-point complex includes one as the floating number of real part and one as empty The floating number in portion；The data selecting module, for reading floating-point complex described in two groups respectively from two vector registors respectively Real part floating number and imaginary part floating number, sent as input data to the computing module；The computing module, the input data for being sent to the data selecting module carries out corresponding computing, described Computing module includes multiple computing submodules, and control signal multiplies i add operations instruction, single-precision floating point including single precision floating datum Number multiplies i subtractions operational order, double-precision floating pointses multiply i add operations instruction and double-precision floating pointses multiply in i subtraction operational orders Any one；When the control signal is that the single precision floating datum multiplies the operation of i plus/minus, the control module controls institute State data selecting module and the first single precision imaginary part floating number, the second single precision are read from two different vector registors Real part floating number, the first single precision real part floating number, the second single precision imaginary part floating number, and the computing submodule is controlled to institute State the first single precision imaginary part floating number and the second single precision real part floating number carries out the operation of single-precision floating point plus/minus method, and it is right The first single precision real part floating number and the second single precision imaginary part floating number carry out single-precision floating point and subtract/add operation；Work as institute When stating control signal and multiplying the operation of i plus/minus for the double-precision floating pointses, the control module controls the data selecting module point The first double precision imaginary part floating number and the second double precision real part floating number are not read from two vector registors, and is controlled The computing submodule carries out double-precision floating point to the first double precision imaginary part floating number and the second double precision real part floating number Plus/minus method operates, and reads the first double precision real part floating number and the second double precision imaginary part floating number, and controls the computing Submodule carries out double-precision floating point to the first double precision real part floating number and the second double precision imaginary part floating number and subtracts/addition behaviour Make；The control module, for receiving operation information, control signal is generated according to the operation information, and according to the control Signal controls the data selecting module and the computing module to carry out corresponding data selection operation and arithmetic operation；AndThe data memory module is additionally operable to preserve the operation result of the computing module.
- 2. device according to claim 1, it is characterised in that the control module is specifically used for according to the control signal The data selector channel of the data selecting module and the mode of operation of the computing module are determined, wherein, the mode of operation Including appointing in two 32 single precision floating datum operation patterns and 64 double-precision floating pointses operation patterns Meaning is a kind of.
- 3. device according to claim 1, it is characterised in that each computing submodule is 64.
- A kind of 4. method for multiplying i plus-minuss for floating-point complex, it is characterised in that including：Multiple floating-point complex are preserved, wherein, each floating-point complex includes one as the floating number of real part and a conduct The floating number of imaginary part；Operation information is received, and control signal is generated according to the operation information；The real part floating number of two different floating-point complex of reading and imaginary part floating number are as input data respectively；AndCorresponding arithmetic operation is carried out to the input data according to the control signal, control signal includes single precision floating datum Multiply i add operations, single precision floating datum multiplies the operation of i subtractions, double-precision floating pointses multiply i add operations and double-precision floating pointses multiply i Subtraction operation in any one；When the control signal is that the single precision floating datum multiplies the operation of i plus/minus, respectively from two The first single precision real part floating number, the first single precision imaginary part floating number and the second single precision real part is read in individual vector registor to float Points, the second single precision imaginary part floating number, and to the first single precision imaginary part floating number and the second single precision real part floating number The operation of single-precision floating point plus/minus method is carried out, and to the first single precision real part floating number and the second single precision imaginary part floating-point Number carries out single-precision floating point and subtracts/add operation；When the control signal is that the double-precision floating pointses multiply the operation of i plus/minus, point The first double precision imaginary part floating number and the second double precision real part floating number are not read from two vector registors, and to institute State the first double precision imaginary part floating number and carry out the operation of double-precision floating point plus/minus method with the second double precision real part floating number, and read Take the first double precision real part floating number and the second double precision imaginary part floating number, and to the first double precision real part floating number and the Two double precision imaginary part floating numbers carry out double-precision floating point and subtract/add operation；And preserve operation result.
- 5. according to the method for claim 4, it is characterised in that also include：Mode of operation is determined according to the control signal, wherein, the mode of operation includes two 32 single precision floating datums and transported Calculate any one in mode of operation and 64 double-precision floating pointses operation patterns.
- 6. according to the method for claim 4, it is characterised in that the multiple floating-point complex is stored in multiple vector registors In, each the vector registor is used to preserve multiple floating-point complex, described to multiply i operations and add and subtract operation as 64.
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| CN105975436B (en) * | 2016-06-16 | 2023-08-01 | 中国兵器工业集团第二一四研究所苏州研发中心 | IP circuit of general configurable acceleration unit in SoC system |
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| CN103378820A (en) * | 2012-04-19 | 2013-10-30 | 中兴通讯股份有限公司 | Programmable digital filtering implementation method, apparatus, baseband chip and terminal thereof |
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