CN103367322B - Micro-heater and formation method - Google Patents
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- CN103367322B CN103367322B CN201210088186.1A CN201210088186A CN103367322B CN 103367322 B CN103367322 B CN 103367322B CN 201210088186 A CN201210088186 A CN 201210088186A CN 103367322 B CN103367322 B CN 103367322B
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Abstract
A kind of micro-heater and formation method, by plain conductor, the pseudo-grid adjacent with MOS device grid to be measured are connected, and plain conductor is connected with testing power supply, to provide voltage to pseudo-grid, by the joule heating effect of pseudo-grid, MOS device to be measured is heated, and by the heat that the pseudo-grid of voltage control controlled in pseudo-grid produce, and then control the temperature of MOS device to be measured, make the temperature of MOS device reach the probe temperature it being carried out to performance test.Be micro-heater and the heating means of MOS device to be measured intensification in the present invention, micro-heater independently can be utilized to heat, MOS device to be detected is heated evenly, and temperature-controllable.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of is micro-heater of device to be detected intensification and forming method thereof.
Background technology
Along with the integrated level of integrated circuit improves constantly, the device density in integrated circuit and current rate become more and more higher, and integrated circuit can produce more and more higher energy.Therefore, in integrated circuit, the high temperature reliability of device becomes more and more important, more and more needs to carry out at relatively high temperatures to the test of integrated circuit.Such as, the electromigration of metal interconnecting wires is detected, to gate dielectric layer and the dielectric of time correlation test, the high temperature service life of device tested and back bias voltage stability test (NBTI) etc., all need to carry out at relatively high temperatures, the electric property of integrated circuit at relatively high temperatures can be obtained.
The integrated circuit of pending electric performance test, when carrying out electric performance test to integrated circuit, need be placed in heater by prior art, is increased to probe temperature to make the temperature of integrated circuit.As shown in Figure 1, for the vertical view of the existing heater making Integrated Circuit Temperature raise, comprise: insulating barrier 102, the current load node 106 being positioned at the plain conductor 104 on insulating barrier 102 and being connected with plain conductor, also comprises heated tray (not shown) and is positioned at the integrated circuit 108 of the pending electric performance test on heated tray below described insulating barrier 102.In Fig. 1, heater along the cutaway view on AA direction as shown in Figure 2, comprising: heated tray 110, loads on the integrated circuit 108 on heated tray 110, is positioned at the insulating barrier 102 on integrated circuit, is positioned at the plain conductor 104 on insulating barrier 102.
By when in Fig. 1 ~ Fig. 2, heater heats integrated circuit, first the integrated circuit of pending electric performance test is loaded on heated tray 110, electric current is provided to plain conductor 104 by the current load node 106 be connected with plain conductor 104, produce Joule heat by electric current in plain conductor 104 and pass through integrated circuit 108 transferring heat of mode below insulating barrier 102, on heated tray 110 of heat trnasfer, and then making integrated circuit 108 be warming up to probe temperature.Because the integrated circuit 108 be positioned on heated tray 110 exists temperature difference in vertical direction, cause the electric performance test result of integrated circuit inaccurate.
Be can also find more information relevant to technique scheme in the Chinese patent application of 101771023A in application publication number.
Therefore, provide a kind of and can become one of problem demanding prompt solution to the technique that pending electric performance test integrated circuit heats.
Summary of the invention
The problem that the present invention solves is to provide a kind of micro-heater for MOS device intensification to be measured, the MOS device of micro-heater to pending electric performance test independently can be utilized to heat, MOS device to be measured is heated evenly, and temperature-controllable.
For solving the problem, the invention provides a kind of micro-heater, comprising:
MOS device to be measured, described MOS device to be measured comprises the grid be positioned in Semiconductor substrate, and is positioned at the pseudo-grid that Semiconductor substrate is disposed adjacent with MOS device grid to be measured; Be positioned at the first medium layer described Semiconductor substrate covering described pseudo-grid and MOS device grid to be measured; Be positioned at the second dielectric layer on described first medium layer, run through described second dielectric layer and the first connector be connected with grid, run through described second dielectric layer and the second connector be connected with pseudo-grid, and run through described first medium layer with second dielectric layer and with MOS device source electrode to be measured and the 3rd connector be connected that drains, the position of described 3rd connector does not overlap with the position of pseudo-grid; Be positioned at the sense node be connected in described second dielectric layer and with the first connector, and be positioned at the plain conductor be connected in described second dielectric layer and with the second connector, plain conductor is connected with pseudo-grid by the second connector; Wherein, plain conductor is connected with testing power supply, utilizes described pseudo-grid to heat MOS device to be measured.
Optionally, the material of described grid or pseudo-grid is polysilicon.
Optionally, in described micro-heater, pseudo-grid number is the integral multiple of 2.
Optionally, described pseudo-grid are symmetricly set in the both sides of grid.
Optionally, the bearing of trend of described pseudo-grid is parallel with MOS device grid bearing of trend to be measured.
Optionally, the material of described first medium layer or second dielectric layer is silica or low-K material.
Optionally, the material of described plain conductor is aluminium or copper.
Optionally, the material of described first connector, the second connector or the 3rd connector is tungsten or copper.
Optionally, described micro-heater also comprises loading node, is connected with described plain conductor, and described plain conductor is connected with testing power supply by loading node.
Optionally, the material of described loading node is aluminium or copper.
Accordingly, present invention also offers a kind of formation method of above-mentioned micro-heater, comprising:
There is provided Semiconductor substrate, the grid forming MOS device to be measured on the semiconductor substrate and the pseudo-grid be disposed adjacent with grid; With described grid for mask forms source electrode and the drain region of MOS device to be measured in the Semiconductor substrate of grid both sides, and form the first medium layer covering described grid and pseudo-grid and the second dielectric layer covering described first medium layer; Formed and run through described second dielectric layer and the first connector be connected with grid and run through described second dielectric layer and the second connector be connected with pseudo-grid, form the 3rd connector running through described first medium layer and be connected with second dielectric layer and with source electrode and the drain region of MOS device to be measured, the position of described 3rd connector does not overlap with the position of pseudo-grid; Described second dielectric layer is formed the sense node be connected with the first connector and the plain conductor be connected with the second connector, and described plain conductor is connected with pseudo-grid by the second connector.
Optionally, the material of described grid or pseudo-grid is polysilicon.
Optionally, in described micro-heater, pseudo-grid number is the integral multiple of 2.
Optionally, described pseudo-grid are symmetricly set in the both sides of grid.
Optionally, the bearing of trend of described pseudo-grid is parallel with MOS device grid bearing of trend to be measured.
Optionally, the material of described first medium layer or second dielectric layer is silica or low-K material.
Optionally, the material of described plain conductor is aluminium or copper.
Optionally, the material of described first connector, the second connector or the 3rd connector is tungsten or copper.
Optionally, after the formation method of described micro-heater forms the sense node be connected with the first connector and the plain conductor be connected with the second connector in described second dielectric layer, also comprise the loading node being formed and be connected with described plain conductor, described plain conductor is connected with testing power supply by loading node.
Optionally, the material of described loading node is aluminium or copper.
Compared with prior art, the present invention has the following advantages:
In the present invention, micro-heater makes the pseudo-grid being arranged in MOS device to be measured connect by plain conductor, and plain conductor is connected with testing power supply, to apply voltage to pseudo-grid, by the joule heating effect of pseudo-grid, MOS device to be measured is heated, and by controlling the heat of the pseudo-grid generation of Current Control in pseudo-grid, and then control the temperature of MOS device to be measured, make the temperature of MOS device reach the probe temperature it being carried out to performance test.Because described pseudo-grid are formed near MOS device grid to be measured, micro-heater independently can be utilized to heat MOS device to be measured, make it be heated evenly.
In addition, present invention also offers a kind of formation method of micro-heater, the formation method of the micro-heater of the present invention utilizes plain conductor connected by the pseudo-grid formed in existing technique and apply voltage to pseudo-grid, it is made to produce Joule heat, and then the MOS device to be measured be positioned near pseudo-grid is heated up, to reach the probe temperature of MOS device to be measured, simplify the processing procedure forming micro-heater, improve the efficiency of heating surface of formed micro-heater simultaneously.
Accompanying drawing explanation
Fig. 1 is the vertical view of the existing heater that Integrated Circuit Temperature is raised;
Fig. 2 be in Fig. 1 heater along the cutaway view in AA direction;
Fig. 3 is the vertical view of the present invention's micro-heater one embodiment;
Fig. 4 be in Fig. 3 micro-heater along the cutaway view in BB direction;
Fig. 5 be in Fig. 3 micro-heater along the cutaway view in CC direction;
Fig. 6 is the schematic flow sheet of formation method one embodiment of the micro-heater of the present invention;
Fig. 7 to Figure 10 is the cross-sectional view of the forming process of micro-heater of the embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Just as described in the background section, in the manufacture process of semiconductor device, usually need to carry out electric performance test to integrated circuit in manufactured semiconductor device, to assess the electric property of manufactured semiconductor device.Such as, integrated circuit is carried out in the process of electric performance test, as carried out electromigration detection to metal interconnecting wires, carry out testing with the dielectric of time correlation to gate dielectric layer, to the test of the high temperature service life of device and back bias voltage stability test (NBTI) etc., the temperature of pending semiconductor test is all needed to be increased to higher temperature, and prior art do not have a kind of can effectively to the heater that pending electric performance test integrated circuit heats up, make at integrated circuit in electric performance test process, detection means can be treated heat separately, avoid the impact being subject to other factors, device to be detected is heated evenly, and temperature-controllable.
In existing technique; in the process forming MOS device grid; usual meeting is in the monosymmetric formation of grid and gate parallel and the pseudo-grid of structural similarity; avoid by light shield the photoresist exposure be deposited in gate material layers; during to form the photoetching agent pattern corresponding with gate shapes; make because mask pattern A/F corresponding with grid on light shield is too little laser through during mask pattern occur diffraction; the opening of formed photoetching agent pattern is caused to become large; impact institute forms the shape of grid, and then the performance of MOS device manufactured by affecting.
For the formation process of the problems referred to above and existing MOS device, inventor provide a kind of micro-heater, comprise: MOS device to be measured, described MOS device to be measured comprises the grid be positioned in Semiconductor substrate, and is positioned at the pseudo-grid that Semiconductor substrate is disposed adjacent with MOS device grid to be measured; Be positioned at the first medium layer described Semiconductor substrate covering described pseudo-grid and MOS device grid to be measured; Be positioned at the second dielectric layer on described first medium layer, run through described second dielectric layer and the first connector be connected with grid, run through described second dielectric layer and the second connector be connected with pseudo-grid, and run through described first medium layer with second dielectric layer and with MOS device source electrode to be measured and the 3rd connector be connected that drains, the position of described 3rd connector does not overlap with the position of pseudo-grid; Be positioned at the sense node be connected in described second dielectric layer and with the first connector, and be positioned at the plain conductor be connected in described second dielectric layer and with the second connector, plain conductor is connected with pseudo-grid by the second connector; Wherein, plain conductor is connected with testing power supply, utilizes described pseudo-grid to heat MOS device to be measured.
In the present invention micro-heater by plain conductor, existing technique is formed, the pseudo-grid adjacent with grid are connected, and plain conductor is connected with testing power supply, by the joule heating effect of grid, MOS device is heated, make its temperature rise to the probe temperature carrying out electric performance test.Because described pseudo-grid are positioned near the grid of MOS device, MOS device is heated evenly, and by changing the voltage loading on testing power supply on plain conductor, the heat that pseudo-grid produce can be controlled, thus control the temperature of MOS device to be measured.
With reference to figure 3 to Fig. 5, be a kind of embodiment of the micro-heater of the present invention, wherein Fig. 3 is the vertical view of the micro-heater of the present invention, Fig. 4 and Fig. 5 to be respectively in Fig. 3 micro-heater along the cutaway view on BB direction and CC direction.Described micro-heater comprises: Semiconductor substrate 200, is positioned at the isolation structure 201 of described Semiconductor substrate 200, and between isolation structure 201, the active area 202 of MOS device to be measured; Be positioned at the grid 204 of MOS device to be measured on described active area 202; Be symmetricly set in grid 204 both sides, and the pseudo-grid 206 of structural similarity parallel with grid 204; Be positioned in described Semiconductor substrate 200, cover the first medium layer 300 of described grid 204 and pseudo-grid 206, cover the second dielectric layer 400 of described first medium layer 300; Run through described second dielectric layer 400 and the first connector 208 be connected with grid 204, run through described second dielectric layer 400 and the second connector 210 be connected with pseudo-grid 206, run through described first medium layer 300 with second dielectric layer 400 and with the 3rd connector 203 being formed at MOS device source electrode to be measured and drain region in active area 202 and being connected; Be positioned at the sense node 212 be connected in described second dielectric layer 400 and with the first connector 208, and be positioned at the plain conductor 214 be connected in described second dielectric layer 400 and with the second connector 210, plain conductor 214 is connected with pseudo-grid 206 by the second connector 210.Wherein, the position of described 3rd connector 203 does not overlap with the position of pseudo-grid 206; Described plain conductor 214 is connected with external testing power supply, utilizes described pseudo-grid 206 to heat MOS device to be measured.
In the present embodiment, described Semiconductor substrate 200 is silicon substrate, germanium substrate, silicon-Germanium substrate, silicon carbide substrates, gallium nitride substrate one wherein.The material of described grid 204 or pseudo-grid 206 can be polysilicon.Described pseudo-grid 206 can be positioned on the active area 202 of MOS device to be measured, also can be positioned at outside the active area 202 of MOS device to be measured, but the 3rd connector 203 that described pseudo-grid 206 position is not connected with MOS device source electrode to be measured and drain region overlaps.
Preferably, the number of described pseudo-grid 206 is the integral multiple of 2, and is symmetricly set in the both sides of grid 204, and to make subsequently through applying voltage to pseudo-grid 206 to make in MOS device temperature-rise period to be measured, MOS device to be measured is heated evenly.In the present embodiment, described micro-heater comprises four pseudo-grid 206, and described pseudo-grid 206 are symmetricly set in grid 204 both sides; The bearing of trend EE of described pseudo-grid 206 can be identical with the bearing of trend DD of grid 204.
The material of described first connector 108, second connector 110, the 3rd connector 203 can be tungsten or copper, and the material of described plain conductor 214 can be aluminium or copper.The material of described first medium layer 300 and second dielectric layer 400 can be silica or low k dielectric materials.
In other embodiments, described micro-heater also comprises loading node 216, is connected with described plain conductor 214, and described plain conductor 214 is connected with external testing power supply by loading node 216.The material of described loading node 216 is aluminium or copper.
In the present embodiment, because described pseudo-grid 206 are formed near the grid 204 of MOS device to be measured, described MOS device to be measured is heated evenly, and by changing the voltage loading on testing power supply on plain conductor 214, control the heat that pseudo-grid 206 produce, thus reach the object of the temperature controlling MOS device to be measured.
Accordingly, present invention also offers a kind of formation method of micro-heater, with reference to figure 6, be the schematic flow sheet of formation method one embodiment of the micro-heater of the present invention, comprise:
Step S1, provides Semiconductor substrate, the grid forming MOS device to be measured on the semiconductor substrate and the pseudo-grid be disposed adjacent with grid;
Step S2, with described grid for mask forms source electrode and the drain region of MOS device to be measured in the Semiconductor substrate of grid both sides, and forms the first medium layer covering described grid and pseudo-grid and the second dielectric layer covering described first medium layer;
Step S3, formed and run through described second dielectric layer and the first connector be connected with grid and run through described second dielectric layer and the second connector be connected with pseudo-grid, form the 3rd connector running through described first medium layer and be connected with second dielectric layer and with source electrode and the drain region of MOS device to be measured, the position of described 3rd connector does not overlap with the position of pseudo-grid;
Step S4, described second dielectric layer is formed the sense node be connected with the first connector and the plain conductor be connected with the second connector, and described plain conductor is connected with pseudo-grid by the second connector.
Fig. 7 to Figure 10 is the cross-sectional view of the forming process of micro-heater of the embodiment of the present invention, and composition graphs 6, Fig. 7 to Figure 10 are described in detail to the forming process for micro-heater.
In conjunction with reference to figure 6 and Fig. 7, perform step S1, provide Semiconductor substrate 200, the grid 204 that described Semiconductor substrate 200 is formed MOS device to be measured and the pseudo-grid 206 be disposed adjacent with grid 204.
In a particular embodiment, in described Semiconductor substrate 200, be also formed with isolation structure 201, to define the active area 202 of MOS device to be measured.The material of described Semiconductor substrate 200 is silicon substrate, germanium substrate, silicon-Germanium substrate, silicon carbide substrates, gallium nitride substrate one wherein.The material of described grid 204 or pseudo-grid 206 can be polysilicon.Described pseudo-grid 206 can be positioned on the active area 202 of MOS device to be measured, also can be positioned at outside the active area 202 of MOS device to be measured.
In conjunction with reference to figure 6 and Fig. 8, perform step S2, be source electrode and the drain region that mask forms MOS device to be measured in the Semiconductor substrate of grid 204 both sides with described grid 204, and form the first medium layer 300 covering described grid 204 and pseudo-grid 206 and the second dielectric layer 400 covering described first medium layer 300.
Wherein, the material of described first medium layer 300 and second dielectric layer 400 can be silica or low k dielectric materials.
In conjunction with reference to figure 6 and Fig. 9, perform step S3, formed and run through described second dielectric layer 400 and the first connector (not shown) be connected with grid 204 and run through described second dielectric layer 400 and the second connector 210 be connected with pseudo-grid 206, form the 3rd connector (not shown) running through described first medium layer 300 and be connected with second dielectric layer 400 and with source electrode and the drain region of MOS device to be measured, the position of described 3rd connector does not overlap with the position of pseudo-grid 206.
Concrete, the material of described first connector, the second connector 210 and the 3rd connector is tungsten or copper.
Finally, in conjunction with reference to figure 6 and Figure 10, perform step S4, described second dielectric layer 400 is formed the sense node (not shown) be connected with the first connector and the plain conductor 214 be connected with the second connector 210, and described plain conductor 214 is connected with pseudo-grid 206 by the second connector 210.
Concrete, the material of described plain conductor is aluminium or copper.
In other embodiments, after step S4, also comprise the loading node 216 being formed and be connected with described plain conductor 214, the material of described loading node 216 is aluminium or copper, and described plain conductor 214 is connected with testing power supply by loading node 216.
The vertical view of the micro-heater formed by step S1 to S4 as shown in Figure 3.
In the present embodiment, the formation method of micro-heater utilizes plain conductor connected by the pseudo-grid formed in existing technique and apply voltage to pseudo-grid, it is made to produce Joule heat, and then the MOS device to be measured be positioned near pseudo-grid is heated up, to reach the probe temperature of MOS device to be measured, simplify the processing procedure forming micro-heater, improve the efficiency of heating surface of formed micro-heater simultaneously.
To sum up, in the present invention be MOS device to be measured heat up micro-heater and heating means by plain conductor, the pseudo-grid adjacent with MOS device grid to be measured are connected, and plain conductor is connected with testing power supply, to provide voltage to pseudo-grid, the joule heating effect of pseudo-grid is utilized to heat MOS device to be measured, and by the heat that the pseudo-grid of voltage control controlled in pseudo-grid produce, and then control the temperature of MOS device to be measured, make the temperature of MOS device reach the probe temperature it being carried out to performance test.Micro-heater independently can be utilized to heat, MOS device to be detected is heated evenly, and temperature-controllable.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (20)
1. a micro-heater, is characterized in that, comprises
MOS device to be measured, described MOS device to be measured comprises the grid be positioned in Semiconductor substrate, and is positioned at the pseudo-grid that Semiconductor substrate is disposed adjacent with MOS device grid to be measured;
Be positioned at the first medium layer described Semiconductor substrate covering described pseudo-grid and MOS device grid to be measured;
Be positioned at the second dielectric layer on described first medium layer, run through described second dielectric layer and the first connector be connected with grid, run through described second dielectric layer and the second connector be connected with pseudo-grid, and run through described first medium layer with second dielectric layer and with MOS device source electrode to be measured and the 3rd connector be connected that drains, the position of described 3rd connector does not overlap with the position of pseudo-grid;
Be positioned at the sense node be connected in described second dielectric layer and with the first connector, and be positioned at the plain conductor be connected in described second dielectric layer and with the second connector, plain conductor is connected with pseudo-grid by the second connector;
Wherein, plain conductor is connected with testing power supply, utilizes described pseudo-grid to heat MOS device to be measured.
2. micro-heater as claimed in claim 1, is characterized in that, the material of described grid or pseudo-grid is polysilicon.
3. micro-heater as claimed in claim 1, is characterized in that, in described micro-heater, pseudo-grid number is the integral multiple of 2.
4. micro-heater as claimed in claim 3, is characterized in that, described pseudo-grid are symmetricly set in the both sides of grid.
5. micro-heater as claimed in claim 1, is characterized in that, the bearing of trend of described pseudo-grid is parallel with MOS device grid bearing of trend to be measured.
6. micro-heater as claimed in claim 1, is characterized in that, the material of described first medium layer or second dielectric layer is silica or low-K material.
7. micro-heater as claimed in claim 1, is characterized in that, the material of described plain conductor is aluminium or copper.
8. micro-heater as claimed in claim 1, is characterized in that, the material of described first connector, the second connector or the 3rd connector is tungsten or copper.
9. micro-heater as claimed in claim 1, is characterized in that, also comprises loading node, is connected with described plain conductor, and described plain conductor is connected with testing power supply by loading node.
10. micro-heater as claimed in claim 9, is characterized in that, the material of described loading node is aluminium or copper.
The formation method of 11. 1 kinds of micro-heaters, is characterized in that, comprising:
There is provided Semiconductor substrate, the grid forming MOS device to be measured on the semiconductor substrate and the pseudo-grid be disposed adjacent with grid;
With described grid for mask forms source electrode and the drain region of MOS device to be measured in the Semiconductor substrate of grid both sides, and form the first medium layer covering described grid and pseudo-grid and the second dielectric layer covering described first medium layer;
Formed and run through described second dielectric layer and the first connector be connected with grid and run through described second dielectric layer and the second connector be connected with pseudo-grid, form the 3rd connector running through described first medium layer and be connected with second dielectric layer and with source electrode and the drain region of MOS device to be measured, the position of described 3rd connector does not overlap with the position of pseudo-grid;
Described second dielectric layer is formed the sense node be connected with the first connector and the plain conductor be connected with the second connector, and described plain conductor is connected with pseudo-grid by the second connector.
The formation method of 12. micro-heaters as claimed in claim 11, is characterized in that, the material of described grid and pseudo-grid is polysilicon.
The formation method of 13. micro-heaters as claimed in claim 11, is characterized in that, the number of described pseudo-grid is the integral multiple of 2.
The formation method of 14. micro-heaters as claimed in claim 13, it is characterized in that, described pseudo-grid are symmetricly set in the both sides of grid.
The formation method of 15. micro-heaters as claimed in claim 11, is characterized in that, the bearing of trend of described pseudo-grid is parallel with the grid bearing of trend of MOS device to be measured.
The formation method of 16. micro-heaters as claimed in claim 11, is characterized in that, the material of described first medium layer or second dielectric layer is silica or low-K material.
The formation method of 17. micro-heaters as claimed in claim 11, is characterized in that, the material of described plain conductor is aluminium or copper.
The formation method of 18. micro-heaters as claimed in claim 11, is characterized in that, the material of described first connector, the second connector or the 3rd connector is tungsten or copper.
The formation method of 19. micro-heaters as claimed in claim 11, it is characterized in that, after described second dielectric layer is formed the sense node that is connected with the first connector and the plain conductor be connected with the second connector, also comprise the loading node being formed and be connected with described plain conductor, described plain conductor is connected with testing power supply by loading node.
The formation method of 20. micro-heaters as claimed in claim 19, is characterized in that, the material of described loading node is aluminium or copper.
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| US5598009A (en) * | 1994-11-15 | 1997-01-28 | Advanced Micro Devices, Inc. | Hot carrier injection test structure and testing technique for statistical evaluation |
| CN100362642C (en) * | 2004-06-28 | 2008-01-16 | 中芯国际集成电路制造(上海)有限公司 | Detecting structure for simultaneously detecting hot carriers of multiple metal-oxide-semiconductor device |
| CN101771023B (en) * | 2008-12-31 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Wafer-level test structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5598009A (en) * | 1994-11-15 | 1997-01-28 | Advanced Micro Devices, Inc. | Hot carrier injection test structure and testing technique for statistical evaluation |
| CN100362642C (en) * | 2004-06-28 | 2008-01-16 | 中芯国际集成电路制造(上海)有限公司 | Detecting structure for simultaneously detecting hot carriers of multiple metal-oxide-semiconductor device |
| CN101771023B (en) * | 2008-12-31 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Wafer-level test structure |
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