CN103367322A - Micro heating device and forming method - Google Patents
Micro heating device and forming method Download PDFInfo
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- CN103367322A CN103367322A CN2012100881861A CN201210088186A CN103367322A CN 103367322 A CN103367322 A CN 103367322A CN 2012100881861 A CN2012100881861 A CN 2012100881861A CN 201210088186 A CN201210088186 A CN 201210088186A CN 103367322 A CN103367322 A CN 103367322A
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Abstract
The invention provides a micro heating device and a forming method. A gate of an MOS device to be tested is connected with an adjacent dummy gate through a metal wire, and the metal wire is connected with a test power supply to provide voltage for the dummy gate. The MOS device to be tested is heated through the Joule heating effect of the dummy gate, the heat generated by the dummy gate is controlled through controlling the voltage in the dummy voltage, thus the temperature of the MOS device to be tested is controlled, and the temperature of the MOS device reaches a test temperature of testing the performance of the MOS device. According to the micro heating device for raising the temperature of the MOS device to be tested and the heating method, the micro heating device can be used independently to carry out heating, thus the heating of the MOS device to be tested is uniform, and the temperature is controllable.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of is little heater of heating up of device to be detected and forming method thereof.
Background technology
Along with the integrated level of integrated circuit improves constantly, the device density in the integrated circuit and current rate become more and more higher, and integrated circuit can produce more and more higher energy.Therefore, the high temperature reliability of device becomes more and more important in the integrated circuit, more and more need to carry out under higher temperature the test of integrated circuit.For example, to the electromigration of metal interconnecting wires detect, to dielectric test gate dielectric layer and time correlation, to the high temperature service life test of device and back bias voltage stability test (NBTI) etc., all need under higher temperature, carry out, in order to can obtain the electric property of integrated circuit under higher temperature.
Prior art needs the integrated circuit of pending electric performance test is placed heater, so that the temperature of integrated circuit is increased to probe temperature when integrated circuit is carried out electric performance test.As shown in Figure 1, be the existing vertical view that makes the heater of integrated circuit temperature rising, comprise: insulating barrier 102, the current load node 106 that is positioned at the plain conductor 104 on the insulating barrier 102 and is connected with plain conductor, the integrated circuit 108 that described insulating barrier 102 belows also comprise the heated tray (not shown) and are positioned at the pending electric performance test on the heated tray.Heater comprises along the cutaway view on the AA direction as shown in Figure 2 among Fig. 1: heated tray 110, load on the integrated circuit 108 on the heated tray 110, and be positioned at the insulating barrier 102 on the integrated circuit, be positioned at the plain conductor 104 on the insulating barrier 102.
When by heater among Fig. 1～Fig. 2 integrated circuit being heated, integrated circuit with pending electric performance test loads on the heated tray 110 first, provide electric current by the current load node 106 that is connected with plain conductor 104 to plain conductor 104, produce Joule heat and the mode transmitted by heat integrated circuit 108 transferring heats on insulating barrier 102 belows, the heated tray 110 by electric current in the plain conductor 104, and then make integrated circuit 108 be warming up to probe temperature.Because there is temperature difference in vertical direction in the integrated circuit 108 that is positioned on the heated tray 110, causes the electric performance test result of integrated circuit inaccurate.
In being the Chinese patent application of 101771023A, application publication number can also find more information relevant with technique scheme.
Therefore, provide a kind of and can become one of problem demanding prompt solution to the technique that pending electric performance test integrated circuit heats.
Summary of the invention
The problem that the present invention solves provides a kind of little heater that heats up for MOS device to be measured, can independently utilize little heater that the MOS device of pending electric performance test is heated, so that MOS device to be measured is heated evenly, and temperature is controlled.
For addressing the above problem, the invention provides a kind of little heater, comprising:
MOS device to be measured, described MOS device to be measured comprises the grid that is positioned on the Semiconductor substrate, and is positioned on the Semiconductor substrate the pseudo-grid with the adjacent setting of MOS device grids to be measured; Be positioned at the first medium layer that covers described pseudo-grid and MOS device grids to be measured on the described Semiconductor substrate; Be positioned at the second medium layer on the described first medium layer, the first connector that runs through described second medium layer and be connected with grid, the second connector that runs through described second medium layer and be connected with pseudo-grid, and run through described first medium layer and be connected with the second medium layer and MOS device source electrode to be measured and the 3rd connector that is connected of drain electrode, the position of described the 3rd connector does not overlap with the position of pseudo-grid; Be positioned on the described second medium layer and the sense node that is connected with the first connector, and be positioned on the described second medium layer and the plain conductor that is connected with the second connector, plain conductor is connected with pseudo-grid by the second connector; Wherein, plain conductor is connected with testing power supply, utilizes described pseudo-grid to MOS device heats to be measured.
Optionally, the material of described grid or pseudo-grid is polysilicon.
Optionally, pseudo-grid number is 2 integral multiple in described little heater.
Optionally, described pseudo-grid are symmetricly set in the both sides of grid.
Optionally, the bearing of trend of described pseudo-grid is parallel with MOS device grids bearing of trend to be measured.
Optionally, the material of described first medium layer or second medium layer is silica or low-K material.
Optionally, the material of described plain conductor is aluminium or copper.
Optionally, the material of described the first connector, the second connector or the 3rd connector is tungsten or copper.
Optionally, described little heater also comprises the loading node, is connected with described plain conductor, and described plain conductor is connected with testing power supply by loading node.
Optionally, the material of described loading node is aluminium or copper.
Accordingly, the present invention also provides a kind of formation method of above-mentioned little heater, comprising:
Semiconductor substrate is provided, described Semiconductor substrate form MOS device to be measured grid and with the pseudo-grid of the adjacent setting of grid; In the Semiconductor substrate of grid both sides, form source electrode and the drain region of MOS device to be measured take described grid as mask, and form the described grid of covering and the first medium layer of pseudo-grid and the second medium layer that covers described first medium layer; The second connector that formation runs through described second medium layer and the first connector that is connected with grid and runs through described second medium layer and be connected with pseudo-grid, formation runs through described first medium layer is connected the 3rd connector that is connected with source electrode and the drain region of MOS device to be measured with the second medium layer, the position of described the 3rd connector does not overlap with the position of pseudo-grid; Form the sense node that is connected with the first connector and the plain conductor that is connected with the second connector at described second medium layer, described plain conductor is connected with pseudo-grid by the second connector.
Optionally, the material of described grid or pseudo-grid is polysilicon.
Optionally, pseudo-grid number is 2 integral multiple in described little heater.
Optionally, described pseudo-grid are symmetricly set in the both sides of grid.
Optionally, the bearing of trend of described pseudo-grid is parallel with MOS device grids bearing of trend to be measured.
Optionally, the material of described first medium layer or second medium layer is silica or low-K material.
Optionally, the material of described plain conductor is aluminium or copper.
Optionally, the material of described the first connector, the second connector or the 3rd connector is tungsten or copper.
Optionally, the formation method of described little heater described second medium layer form the sense node that is connected with the first connector and with plain conductor that the second connector is connected after, comprise also forming the loading node that is connected with described plain conductor that described plain conductor is connected with testing power supply by loading node.
Optionally, the material of described loading node is aluminium or copper.
Compared with prior art, the present invention has the following advantages:
Little heater connects the pseudo-grid that are arranged in MOS device to be measured by plain conductor among the present invention, and plain conductor is connected with testing power supply, so that pseudo-grid are applied voltage, joule heating effect by pseudo-grid is to MOS device heats to be measured, and by controlling the heat of the pseudo-grid generation of Current Control in the pseudo-grid, and then control the temperature of MOS device to be measured, make the temperature of MOS device reach the probe temperature that it is carried out performance test.Because described pseudo-grid are formed near the MOS device grids to be measured, can independently utilize little heater that MOS device to be measured is heated, and it is heated evenly.
In addition, the present invention also provides a kind of formation method of little heater, the pseudo-grid that the formation method of the little heater of the present invention is utilized plain conductor to have now to form in the technique connect and pseudo-grid are applied voltage, make it produce Joule heat, and then near the MOS device to be measured that is positioned at the pseudo-grid is heated up, to reach the probe temperature of MOS device to be measured, simplified the processing procedure that forms little heater, improved simultaneously the efficiency of heating surface of little heater that forms.
Description of drawings
Fig. 1 is the existing vertical view that makes the heater of integrated circuit temperature rising;
Fig. 2 be among Fig. 1 heater along the cutaway view of AA direction;
Fig. 3 is the vertical view of little heater one embodiment of the present invention;
Fig. 4 be among Fig. 3 little heater along the cutaway view of BB direction;
Fig. 5 be among Fig. 3 little heater along the cutaway view of CC direction;
Fig. 6 is the schematic flow sheet of formation method one embodiment of the little heater of the present invention;
Fig. 7 to Figure 10 is the cross-sectional view of forming process of little heater of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, in the manufacture process of semiconductor device, usually need to carry out electric performance test to integrated circuit in the semiconductor device of manufacturing, with the electric property of assessment manufacturing semiconductor device.For example, integrated circuit is carried out in the process of electric performance test, detect as metal interconnecting wires being carried out electromigration, gate dielectric layer is carried out testing with the dielectric of time correlation, to the test of the high temperature service life of device and back bias voltage stability test (NBTI) etc., all need the temperature of pending semiconductor test is increased to higher temperature, and prior art does not have a kind of heater that can effectively heat up to pending electric performance test integrated circuit, so that at integrated circuit in the electric performance test process, can treat detection means heats separately, avoid being subject to the impact of other factors, so that device to be detected is heated evenly, and temperature is controlled.
In the existing technique; in the process that forms the MOS device grids; usually understand the pseudo-grid of and structural similarity parallel with grid in the monosymmetric formation of grid; avoid by light shield being deposited on the photoresist exposure on the gate material layers; when forming the photoetching agent pattern corresponding with gate shapes; make laser that diffraction occurs when seeing through mask pattern because mask pattern A/F corresponding with grid on the light shield is too little; cause the opening of the photoetching agent pattern that forms to become large; the shape of the impact grid that forms, and then affect manufacturing MOS performance of devices.
Formation technique for the problems referred to above and existing MOS device, the inventor provides a kind of little heater, comprise: MOS device to be measured, described MOS device to be measured comprises the grid that is positioned on the Semiconductor substrate, and is positioned on the Semiconductor substrate the pseudo-grid with the adjacent setting of MOS device grids to be measured; Be positioned at the first medium layer that covers described pseudo-grid and MOS device grids to be measured on the described Semiconductor substrate; Be positioned at the second medium layer on the described first medium layer, the first connector that runs through described second medium layer and be connected with grid, the second connector that runs through described second medium layer and be connected with pseudo-grid, and run through described first medium layer and be connected with the second medium layer and MOS device source electrode to be measured and the 3rd connector that is connected of drain electrode, the position of described the 3rd connector does not overlap with the position of pseudo-grid; Be positioned on the described second medium layer and the sense node that is connected with the first connector, and be positioned on the described second medium layer and the plain conductor that is connected with the second connector, plain conductor is connected with pseudo-grid by the second connector; Wherein, plain conductor is connected with testing power supply, utilizes described pseudo-grid to MOS device heats to be measured.
Little heater will have that technique forms, pseudo-grid adjacent with grid now by plain conductor and be connected among the present invention, and plain conductor is connected with testing power supply, joule heating effect by grid makes its temperature rise to the probe temperature that carries out electric performance test to the MOS device heats.Because described pseudo-grid are positioned near the grid of MOS device, the MOS device is heated evenly, and can loads on by change the voltage of testing power supply on the plain conductor, control the heat that pseudo-grid produce, thereby control the temperature of MOS device to be measured.
To Fig. 5, be a kind of embodiment of the little heater of the present invention with reference to figure 3, wherein Fig. 3 is the vertical view of the little heater of the present invention, and Fig. 4 and Fig. 5 are respectively among Fig. 3 little heater along the cutaway view on BB direction and the CC direction.Described little heater comprises: Semiconductor substrate 200, be positioned at the isolation structure 201 of described Semiconductor substrate 200, and between isolation structure 201, the active area 202 of MOS device to be measured; Be positioned at the grid 204 of MOS device to be measured on the described active area 202; Be symmetricly set in the pseudo-grid 206 of grid 204 both sides, and structural similarity parallel with grid 204; Be positioned on the described Semiconductor substrate 200, cover the first medium layer 300 of described grid 204 and pseudo-grid 206, cover the second medium layer 400 of described first medium layer 300; The first connector 208 that runs through described second medium layer 400 and be connected with grid 204, the second connector 210 that runs through described second medium layer 400 and be connected with pseudo-grid 206, run through that described first medium layer 300 is connected with the second medium layer and be formed at active area 202 in the 3rd connector 203 that is connected of MOS device source electrode to be measured and drain region; Be positioned on the described second medium layer 400 and the sense node 212 that is connected with the first connector 208, and be positioned on the described second medium layer 400 and the plain conductor 214 that is connected with the second connector 210, plain conductor 214 is connected with pseudo-grid 206 by the second connector 210.Wherein, the position of described the 3rd connector 203 does not overlap with the position of pseudo-grid 206; Described plain conductor 214 is connected with the external testing power supply, utilizes 206 pairs of MOS device heats to be measured of described pseudo-grid.
In the present embodiment, described Semiconductor substrate 200 is wherein a kind of of silicon substrate, germanium substrate, silicon-Germanium substrate, silicon carbide substrates, gallium nitride substrate.The material of described grid 204 or pseudo-grid 206 can be polysilicon.Described pseudo-grid 206 can be positioned on the active area 202 of MOS device to be measured, also can be positioned at outside the active area 202 of MOS device to be measured, but the 3rd connector 203 that described pseudo-grid 206 positions are not connected with MOS device source electrode to be measured and drain region overlap.
Better, the number of described pseudo-grid 206 is 2 integral multiple, and is symmetricly set in the both sides of grid 204, so that follow-up by pseudo-grid 206 being applied voltage so that in the MOS device temperature-rise period to be measured, MOS device to be measured is heated evenly.In the present embodiment, described little heater comprises four pseudo-grid 206, and described pseudo-grid 206 are symmetricly set in grid 204 both sides; The bearing of trend EE of described pseudo-grid 206 can be identical with the bearing of trend DD of grid 204.
The material of described the first connector 108, the second connector 110, the 3rd connector 203 can be tungsten or copper, and the material of described plain conductor 214 can be aluminium or copper.The material of described first medium layer 300 and second medium layer 400 can be silica or low k dielectric materials.
In other embodiments, described little heater also comprises loading node 216, is connected with described plain conductor 214, and described plain conductor 214 is connected with the external testing power supply by loading node 216.The material of described loading node 216 is aluminium or copper.
In the present embodiment, because described pseudo-grid 206 are formed near the grid 204 of MOS device to be measured, described MOS device to be measured is heated evenly, and load on the voltage of testing power supply on the plain conductor 214 by change, control the heat that pseudo-grid 206 produce, thereby reach the purpose of the temperature of control MOS device to be measured.
Accordingly, the present invention also provides a kind of formation method of little heater, and with reference to figure 6, the schematic flow sheet for formation method one embodiment of the little heater of the present invention comprises:
Step S1 provides Semiconductor substrate, described Semiconductor substrate form MOS device to be measured grid and with the pseudo-grid of the adjacent setting of grid;
Step S2 forms source electrode and the drain region of MOS device to be measured in the Semiconductor substrate of grid both sides take described grid as mask, and form the described grid of covering and the first medium layer of pseudo-grid and the second medium layer that covers described first medium layer;
Step S3, the second connector that formation runs through described second medium layer and the first connector that is connected with grid and runs through described second medium layer and be connected with pseudo-grid, formation runs through described first medium layer is connected the 3rd connector that is connected with source electrode and the drain region of MOS device to be measured with the second medium layer, the position of described the 3rd connector does not overlap with the position of pseudo-grid;
Step S4 forms the sense node that is connected with the first connector and the plain conductor that is connected with the second connector at described second medium layer, and described plain conductor is connected with pseudo-grid by the second connector.
Fig. 7 to Figure 10 is the cross-sectional view of forming process of little heater of the embodiment of the invention, in conjunction with Fig. 6, Fig. 7 to Figure 10 to being elaborated for the forming process of little heater.
In conjunction with reference to figure 6 and Fig. 7, execution in step S1 provides Semiconductor substrate 200, described Semiconductor substrate 200 form MOS device to be measured grid 204 and with the pseudo-grid 206 of grid 204 adjacent settings.
In specific embodiment, also be formed with isolation structure 201 in the described Semiconductor substrate 200, with the active area 202 that defines MOS device to be measured.The material of described Semiconductor substrate 200 is wherein a kind of of silicon substrate, germanium substrate, silicon-Germanium substrate, silicon carbide substrates, gallium nitride substrate.The material of described grid 204 or pseudo-grid 206 can be polysilicon.Described pseudo-grid 206 can be positioned on the active area 202 of MOS device to be measured, also can be positioned at outside the active area 202 of MOS device to be measured.
In conjunction with reference to figure 6 and Fig. 8, execution in step S2, in the Semiconductor substrate of grid 204 both sides, form source electrode and the drain region of MOS device to be measured take described grid 204 as mask, and form the described grid 204 of covering and the first medium layer 300 of pseudo-grid 206 and the second medium layer 400 that covers described first medium layer 300.
Wherein, the material of described first medium layer 300 and second medium layer 400 can be silica or low k dielectric materials.
In conjunction with reference to figure 6 and Fig. 9, execution in step S3, the second connector 210 that formation runs through described second medium layer 400 and the first connector (not shown) that is connected with grid 204 and runs through described second medium layer 400 and be connected with pseudo-grid 206, formation runs through the 3rd connector (not shown) that described first medium layer 300 is connected with the second medium layer and be connected with source electrode and the drain region of MOS device to be measured, and the position of described the 3rd connector does not overlap with the position of pseudo-grid 206.
Concrete, the material of described the first connector, the second connector 210 and the 3rd connector is tungsten or copper.
At last, in conjunction with reference to figure 6 and Figure 10, execution in step S4 forms the sense node (not shown) that is connected with the first connector and the plain conductor 214 that is connected with the second connector 210 at described second medium layer 400, and described plain conductor 214 is connected with pseudo-grid 206 by the second connector 210.
Concrete, the material of described plain conductor is aluminium or copper.
In other embodiments, behind step S4, comprise also forming the loading node 216 that is connected with described plain conductor 214 that the material of described loading node 216 is aluminium or copper, described plain conductor 214 is connected with testing power supply by loading node 216.
The vertical view of the little heater that forms by step S1 to S4 as shown in Figure 3.
The pseudo-grid that the formation method of little heater is utilized plain conductor to have now to form in the technique in the present embodiment connect and pseudo-grid are applied voltage, make it produce Joule heat, and then near the MOS device to be measured that is positioned at the pseudo-grid is heated up, to reach the probe temperature of MOS device to be measured, simplify the processing procedure that forms little heater, improved simultaneously the efficiency of heating surface of little heater that forms.
To sum up, be that little heater and the heating means that MOS device to be measured heats up are connected the pseudo-grid adjacent with MOS device grids to be measured by plain conductor among the present invention, and plain conductor is connected with testing power supply, to provide voltage to pseudo-grid, utilize the joule heating effect of pseudo-grid to MOS device heats to be measured, and pass through the heat that the pseudo-grid of voltage control in the pseudo-grid of control produce, and then control the temperature of MOS device to be measured, make the temperature of MOS device reach the probe temperature that it is carried out performance test.Can independently utilize little heater to heat, so that MOS device to be detected is heated evenly, and temperature is controlled.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (20)
1. a little heater is characterized in that, comprises
MOS device to be measured, described MOS device to be measured comprises the grid that is positioned on the Semiconductor substrate, and is positioned on the Semiconductor substrate the pseudo-grid with the adjacent setting of MOS device grids to be measured;
Be positioned at the first medium layer that covers described pseudo-grid and MOS device grids to be measured on the described Semiconductor substrate;
Be positioned at the second medium layer on the described first medium layer, the first connector that runs through described second medium layer and be connected with grid, the second connector that runs through described second medium layer and be connected with pseudo-grid, and run through described first medium layer and be connected with the second medium layer and MOS device source electrode to be measured and the 3rd connector that is connected of drain electrode, the position of described the 3rd connector does not overlap with the position of pseudo-grid;
Be positioned on the described second medium layer and the sense node that is connected with the first connector, and be positioned on the described second medium layer and the plain conductor that is connected with the second connector, plain conductor is connected with pseudo-grid by the second connector;
Wherein, plain conductor is connected with testing power supply, utilizes described pseudo-grid to MOS device heats to be measured.
2. little heater as claimed in claim 1 is characterized in that, the material of described grid or pseudo-grid is polysilicon.
3. little heater as claimed in claim 1 is characterized in that, pseudo-grid number is 2 integral multiple in described little heater.
4. little heater as claimed in claim 3 is characterized in that, described pseudo-grid are symmetricly set in the both sides of grid.
5. little heater as claimed in claim 1 is characterized in that, the bearing of trend of described pseudo-grid is parallel with MOS device grids bearing of trend to be measured.
6. little heater as claimed in claim 1 is characterized in that, the material of described first medium layer or second medium layer is silica or low-K material.
7. little heater as claimed in claim 1 is characterized in that, the material of described plain conductor is aluminium or copper.
8. little heater as claimed in claim 1 is characterized in that, the material of described the first connector, the second connector or the 3rd connector is tungsten or copper.
9. little heater as claimed in claim 1 is characterized in that, also comprises the loading node, is connected with described plain conductor, and described plain conductor is connected with testing power supply by loading node.
10. little heater as claimed in claim 9 is characterized in that, the material of described loading node is aluminium or copper.
11. the formation method of a little heater is characterized in that, comprising:
Semiconductor substrate is provided, described Semiconductor substrate form MOS device to be measured grid and with the pseudo-grid of the adjacent setting of grid;
In the Semiconductor substrate of grid both sides, form source electrode and the drain region of MOS device to be measured take described grid as mask, and form the described grid of covering and the first medium layer of pseudo-grid and the second medium layer that covers described first medium layer;
The second connector that formation runs through described second medium layer and the first connector that is connected with grid and runs through described second medium layer and be connected with pseudo-grid, formation runs through described first medium layer is connected the 3rd connector that is connected with source electrode and the drain region of MOS device to be measured with the second medium layer, the position of described the 3rd connector does not overlap with the position of pseudo-grid;
Form the sense node that is connected with the first connector and the plain conductor that is connected with the second connector at described second medium layer, described plain conductor is connected with pseudo-grid by the second connector.
12. the formation method of little heater as claimed in claim 11 is characterized in that, the material of described grid and pseudo-grid is polysilicon.
13. the formation method of little heater as claimed in claim 11 is characterized in that, the number of described pseudo-grid is 2 integral multiple.
14. the formation method of little heater as claimed in claim 13 is characterized in that described pseudo-grid are symmetricly set in the both sides of grid.
15. the formation method of little heater as claimed in claim 11 is characterized in that, the bearing of trend of described pseudo-grid is parallel with the grid bearing of trend of MOS device to be measured.
16. the formation method of little heater as claimed in claim 11 is characterized in that, the material of described first medium layer or second medium layer is silica or low-K material.
17. the formation method of little heater as claimed in claim 11 is characterized in that, the material of described plain conductor is aluminium or copper.
18. the formation method of little heater as claimed in claim 11 is characterized in that, the material of described the first connector, the second connector or the 3rd connector is tungsten or copper.
19. the formation method of little heater as claimed in claim 11, it is characterized in that, described second medium layer form the sense node that is connected with the first connector and with plain conductor that the second connector is connected after, comprise also forming the loading node that is connected with described plain conductor that described plain conductor is connected with testing power supply by loading node.
20. little heater as claimed in claim 19 is characterized in that, the material of described loading node is aluminium or copper.
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| CN201210088186.1A CN103367322B (en) | 2012-03-29 | 2012-03-29 | Micro-heater and formation method |
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| CN201210088186.1A CN103367322B (en) | 2012-03-29 | 2012-03-29 | Micro-heater and formation method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107527902A (en) * | 2016-06-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its control method and domain structure |
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| US5598009A (en) * | 1994-11-15 | 1997-01-28 | Advanced Micro Devices, Inc. | Hot carrier injection test structure and testing technique for statistical evaluation |
| CN100362642C (en) * | 2004-06-28 | 2008-01-16 | 中芯国际集成电路制造(上海)有限公司 | Detecting structure for simultaneously detecting hot carriers of multiple metal-oxide-semiconductor device |
| CN101771023B (en) * | 2008-12-31 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Wafer-level test structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5598009A (en) * | 1994-11-15 | 1997-01-28 | Advanced Micro Devices, Inc. | Hot carrier injection test structure and testing technique for statistical evaluation |
| CN100362642C (en) * | 2004-06-28 | 2008-01-16 | 中芯国际集成电路制造(上海)有限公司 | Detecting structure for simultaneously detecting hot carriers of multiple metal-oxide-semiconductor device |
| CN101771023B (en) * | 2008-12-31 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Wafer-level test structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107527902A (en) * | 2016-06-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its control method and domain structure |
| CN107527902B (en) * | 2016-06-20 | 2020-04-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and control method thereof and layout structure |
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