CN103365749A - Multi-core processor debugging system - Google Patents
Multi-core processor debugging system Download PDFInfo
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Abstract
The invention relates to a multi-core processor debugging system which comprises a master controller, microprocessor IPs (Internet Protocols) and a debugging state controller.Debugging control units in the microprocessor IPs and a debugging control unit in the master controller are connected with the debugging state controller for feeding debugging requests of the microprocessor IPs and the master controller back to the debugging state controller, and transmitting debugging response signals sent by the debugging state controller to the microprocessor IPs and the master controller. In the debugging system, the number of the integrated microprocessor IPs is unrestricted, debugging structures in the microprocessor IPs are not required to be changed, and the debugging system is easy to realize. The debugging state controller receives debugging request signals of the master controller and the microprocessor IPs, and synchronously control debugging of the master controller and the microprocessor IPs, so that cores in the multi-core processor enter or exit a debugging mode simultaneously.
Description
Technical field
The present invention relates to a kind of polycaryon processor, particularly make the polycaryon processor of two-dimensional grid (mesh) framework possess the design of the embedded debug system of on-line debugging ability.
Background technology
All propose some oneself solution for the domestic and international research institution of debugging conceptual design of polycaryon processor, although these methods are different, can be classified as two large classes according to its fundamental characteristics:
● based on traditional JTAG adjustment method.
Adjustment method based on traditional JTAG is generally all carried out effective organization and management by the JTAG mouth that MPSoC is gone up on the different IP kernels, thereby realizes the adjustable of multiple nucleus system.These class methods are more typically studied:
● based on the adjustment method of tracking technique.
Main thought is, at first according to the debugging demand monitoring point is set, and in a single day the monitoring point is triggered, and the target information that needs are collected writes back peculiar buffer memory, and debugger at first reads cache information, reaches debugging purpose thereby then resolve these information.The method has a common shortcoming, can't debug communicating by letter between the IP kernel in the system.
Even multinuclear debugging based on the debugging framework of bus, also is unusual hard problem, is not perfectly solved especially in the polycaryon processor based on the mesh framework, especially at multinuclear synchronously and aspect the cross debugging.
Summary of the invention
The technical matters that the present invention solves is: overcome the deficiencies in the prior art, a kind of polycaryon processor debug system is provided, realize the debugging synchro control to master controller and microprocessor IP, so that each nuclear enters or withdraw from debugging mode simultaneously in the polycaryon processor.
Technical scheme of the present invention is: a kind of polycaryon processor debug system comprises microprocessor IP, master controller, debugging mode controller, debug command write bus, Debugging message read bus; Described microprocessor IP is arranged in two-dimensional mesh trellis structure, and each microprocessor IP comprises microprocessor IP debugging communication link unit and microprocessor IP debugging control module; Described master controller comprises the serial debugging interface of master controller, the debugging communication link unit of master controller, the storage space external interface unit of master controller, the debugging control unit of master controller; Mutual conversion between 8 bit data that the serial debugging interface of the debugging communication link unit realization master controller of master controller receives and sends and 32 bit data of master controller internal bus; The debug command write bus has comprised 32 output data lines, address wire and the write signals that the storage space external interface unit of master controller is sent, the debug command write bus links to each other with the storage space external interface unit of master controller, simultaneously debug command write bus also links to each other with the unit, microprocessor IP debugging communication link unit of each microprocessor IP inside, for microprocessor IP debugging communication link unit provides debug command; The Debugging message read bus is 32 data line, be connected with the input data line of the storage space external interface unit of master controller, the Debugging message read bus also links to each other with the unit, microprocessor IP debugging communication link unit of each microprocessor IP inside simultaneously, the Debugging message of each microprocessor IP is outputed to the storage space external interface unit of master controller; Whether the address information of exporting in the microprocessor IP debugging communication link unit judges debug command write bus among each microprocessor IP is for this microprocessor IP, when judged result when being, receive the data message in the debug command write bus, Parallel debugging Information Read-Out bus is sent the debugging reply data; The storage space external interface unit of master controller also links to each other with the debugging mode controller, for generation of the debug reset signal that withdraws from debugging mode; The microprocessor IP debugging control module of each microprocessor IP inside and the debugging control unit of master controller all are connected to the debugging mode controller, be used for the debugging request of each microprocessor IP and master controller is fed back to the debugging mode controller, the debugging answer signal that also is used for simultaneously the debugging mode controller is sent sends to each microprocessor IP and master controller; The input data line of the output data line of master controller serial line interface, master controller serial line interface is realized and outside data information transfer by the serial debugging interface of master controller; External interface debugging enable signal and external interface debugging trigger pip are all delivered to the debugging mode controller, are used for judging and trigger polycaryon processor entering debugging mode;
Described debugging mode controller comprises or door, with door, not gate, the first two-way selector switch, the second two-way selector switch, the first trigger, the second trigger, the 3rd trigger; With per two microprocessor IP debugging control modules to the debugging mode controller send enter the debugging mode marking signal deliver to one or, will be above-mentioned all or door output deliver to simultaneously again another or; The result of above-mentioned another or door output again with by master controller to the debugging mode controller send enter the debugging mode marking signal deliver to the 3rd or; The result of above-mentioned the 3rd or an output delivers to the S1 port of the first two-way selector switch, and external interface debugging trigger pip inputs to the S0 port of the first two-way selector switch simultaneously; The debug reset signal inputs to the reset terminal R of the first trigger and the reset terminal R of the second trigger simultaneously; The reset signal of external interface inputs to the control end C of the first two-way selector switch and the control end C of the second two-way selector switch simultaneously; One road signal of external interface debugging enable signal is delivered to the S0 port of the second two-way selector switch; The polycaryon processor internal clock signal inputs to respectively the CLK port of the first trigger and the CLK port of the second trigger; The D port of the first two-way selector switch is connected to the D port of the first trigger; The D port of the second two-way selector switch is connected to the D port of the second trigger; The S1 port of the second two-way selector switch is connected to the reset terminal R of the second trigger; The Q port of the second trigger is delivered to and door with another road signal of external interface debugging enable signal behind the door simultaneously through non-, and above-mentioned result with door output is delivered to the 3rd trigger clock period of delay; Result after the delay exports the S port of the second trigger to; The signal of the Q port of the second trigger and the output of the Q port of the first trigger sends to each microprocessor IP and master controller as the debugging answer signal.
The present invention's advantage compared with prior art is:
(1) debugging scheme not only is applicable to the design of the polycaryon processor take microprocessor IP as processing unit, also can be used for having the IP of debug port as the polycaryon processor design of processing unit take other, have simplicity of design, change few characteristics, reduce to greatest extent and change test, checking workload and the design risk of bringing;
(2) debugging scheme is not subjected to the restriction of microprocessor IP kernel number integrated in the polycaryon processor, is applicable to the polycaryon processor of two-dimensional grid (mesh) framework, has extensibility and tailorability;
Guarantee externally under the signal reset condition that (3) the debugging control signal of inner each the microprocessor IP of polycaryon processor is the external debug interface signal state of chip, like this with regard to so that polycaryon processor can directly enter debugging mode under reset mode.
(4) multinuclear is processed inner any one nuclear owing to after carrying out debug command, running into debugging breakpoint or observation station and enter debugging mode, all can trigger the interior all nuclear of polycaryon processor chip and enter debugging mode.
(5) be designed with special debugging and withdraw from control signal, withdraw from simultaneously debugging mode so that all in the polycaryon processor chip are examined, continue simultaneously operation, guarantee the synchronous of operation.
(6) enable interface signal when effective in chip exterior debugging, polycaryon processor withdraws under the control signal effect in debugging, although can temporarily make the debugging enable signal of each microprocessor of chip internal IP invalid, withdraws from debugging mode; But after a clock delay, the debugging enable signal of each nuclear can revert to effective status again, allows each nuclear again to enter debugging mode.
Description of drawings
Fig. 1 is polycaryon processor debug system one-piece construction synoptic diagram;
Fig. 2 is debugging mode controller architecture synoptic diagram.
Embodiment
Polycaryon processor debug system according to this debugging conceptual design mainly contains following embodiment:
Among Fig. 1, microprocessor IP101 is arranged as two-dimensional grid mesh framework, except disposing normal arithmetic logical unit, also comprises the debugging communication link unit 102 of microprocessor IP and the debugging control unit 103 of microprocessor IP.
Debug command write bus 104,32 output data lines, address wire and write signals being sent by the storage space external interface unit 112 of master controller form.Link to each other with each microprocessor IP debugging communication link unit 102, IP101 provides debug command for each microprocessor.
Debugging message read bus 105 as 32 data line, directly is connected with the input data line of the storage space external interface unit 112 of master controller.Link to each other with each microprocessor IP debugging communication link unit 102, be responsible for the Debugging message of microprocessor IP101 is outputed to the storage space external interface unit 112 of master controller.
The control signal 107 that debugging mode controller 108 sends enters and withdraws from the debugging answer signal of debugging mode as control microprocessor IP101 and master controller 111.
External interface debugging enable signal 117 only when this signal is effective, just allows polycaryon processor to enter debugging mode, otherwise, withdraw from debugging mode.
External interface debugging trigger pip 118 when this signal is high level, triggers polycaryon processor and enters debugging mode.
The control signal 107 that debugging mode controller 108 sends links to each other with the debugging control unit 103 of each microprocessor IP and the debugging control unit 113 of master controller, and the debugging answer signal that debugging mode controller 108 is sent sends to the debugging control unit 103 of microprocessor IP and the debugging control unit 113 of master controller.
The outside input of polycaryon processor Debugging message enters master controller serial line interface 109 by the input data line 115 of master controller serial line interface, and master controller serial line interface 109 receives serial data, is reduced to the octet data.Octet data after the debugging communication link unit 110 of master controller will reduce are combined into 32 digital data, and are divided into address information, data writing information, read-write flag information.The debugging control unit 113 of master controller utilizes these information, finishes the access for master controller internal register, storer and IO space under debugging mode.During polycaryon processor output Debugging message, 32 bit data that the debugging control unit 113 of master controller obtains debugging are inputted the debugging communication link unit 110 of master controller, the debugging communication link unit 110 of master controller is according to the byte form, divide to output to master controller serial line interface 109 4 times, utilize output data line 114 outputs of master controller serial line interface.
For the debugging of microprocessor IP, the debug command of sending from the storage space external interface unit 112 of master controller is by the debugging communication link unit 102 of debug command write bus 104 input microprocessor IP; The debugging communication link unit 102 of microprocessor IP is after the debug command of confirming input is debug command for this microprocessor IP, with the debugging control unit 103 of debug command input microprocessor IP, under debugging mode, finish the access for microprocessor IP internal register, storer.By Debugging message read bus 105, the debugging communication link unit 102 of microprocessor IP is with the parallel storage space external interface unit 112 that passes out to master controller of microprocessor IP101 internal information.
In Fig. 1, debugging mode controller 108 is responsible for that whole polycaryon processor is entered and withdraw from debugging mode and is controlled.Its cut-away view is as shown in Figure 2:
In the polycaryon processor in case have microprocessor IP or master controller carrying out break-poing instruction, occuring that Hardware Breakpoint or observation station are hit and when entering debugging mode, corresponding nuclear to enter the debugging mode marking signal effective so that 1 or 2 is effective.
In Fig. 2, what 1 and the master controller that ' debugging mode controller ' interior processing unit sends sent 2 all carries out or logical operation, like this, as long as there is a nuclear to enter debugging mode, or door 8 output useful signals enter the S1 end of the first two-way selector switch two-way selector switch 9.The first two-way selector switch 9, the second two-way selector switch 10 control end C are connected with external reset signal 119, when reset signal 119 effectively the time, select the output of S0 signal; Otherwise, select the output of S1 signal.The input end S0 of the first two-way selector switch 9 is connected with the debugging trigger pip 118 of polycaryon processor external interface; The input end S0 of the second two-way selector switch 10 is connected with the debugging enable signal 117 of polycaryon processor external interface, and input end S1 is connected with the polycaryon processor internal debugging control enable signal 17 of register 12 outputs.Like this, when reset signal is effective, directly select the state of external signal as the control signal of internal debugging pattern.
The first trigger 11, the second trigger 12, the 3rd trigger 15 are register, the input D end of the first trigger 11, the second trigger 12 is connected with the output of the first two-way selector switch 9, the first two-way selector switch 10 respectively, and trigger output is respectively polycaryon processor internal debugging control trigger pip 16, polycaryon processor internal debugging control enable signal 17; The reset terminal R of the first trigger 11, the second trigger 12 withdraws from debugging mode signal 116 with polycaryon processor and is connected, like this, in case it is effective that polycaryon processor withdraws from debugging mode signal 116, force output hold mode ' 0 ' of the first trigger 11, the second trigger 12.Be respectively polycaryon processor internal debugging control enable signal 17 through the output of not gate and the debugging enable signal 117 of polycaryon processor external interface with the input of door 14; Postpone to be connected with the set end S of the second trigger 12 after a clock period through the 3rd trigger 15 with the output of door 14.Such design, guarantee externally to debug under enable signal 117 conditions for validity, even when withdrawing from debugging mode, can temporarily make processor internal debugging control enable signal 17 invalid, but after the delay through a clock, debugging control enable signal 17 can revert to effective status again, allows new debugging request.
The present invention not detailed description is technology as well known to those skilled in the art.
Claims (1)
1. a polycaryon processor debug system is characterized in that: comprise microprocessor IP(101), master controller (111), debugging mode controller (108), debug command write bus (104), Debugging message read bus (105); Described microprocessor IP(101) be arranged in two-dimensional mesh trellis structure, each microprocessor IP(101) comprise microprocessor IP debugging communication link unit (102) and microprocessor IP debugging control module (103); Described master controller (111) comprises the serial debugging interface (109) of master controller, the debugging communication link unit (110) of master controller, the storage space external interface unit (112) of master controller, the debugging control unit (113) of master controller; Mutual conversion between 8 bit data that the serial debugging interface (109) of debugging communication link unit (110) the realization master controller of master controller receives and sends and 32 bit data of master controller internal bus; Debug command write bus (104) has comprised 32 output data lines, address wire and the write signals that the storage space external interface unit (112) of master controller is sent, debug command write bus (104) links to each other with the storage space external interface unit (112) of master controller, simultaneously debug command write bus (104) also with each microprocessor IP(101) inner unit, microprocessor IP debugging communication link unit (102) links to each other, for microprocessor IP debugging communication link unit (102) provides debug command; Debugging message read bus (105) is 32 data line, be connected with the input data line of the storage space external interface unit (112) of master controller, simultaneously Debugging message read bus (105) also with each microprocessor IP(101) inner unit, microprocessor IP debugging communication link unit (102) links to each other, with each microprocessor IP(101) Debugging message output to the storage space external interface unit (112) of master controller; Each microprocessor IP(101) the microprocessor IP debugging communication link unit (102) in judges that whether the address information of output in the debug command write bus (104) is for this microprocessor IP(101), when judged result when being, receive the data message in the debug command write bus (104), Parallel debugging Information Read-Out bus (105) is sent the debugging reply data; The storage space external interface unit (112) of master controller also links to each other with debugging mode controller (108), for generation of the debug reset signal (116) that withdraws from debugging mode; Each microprocessor IP(101) inner microprocessor IP debugging control module (103) and the debugging control unit (113) of master controller all are connected to debugging mode controller (108), be used for each microprocessor IP(101) and the debugging request of master controller (111) feed back to debugging mode controller (108), the debugging answer signal (107) that also is used for simultaneously debugging mode controller (108) is sent sends to each microprocessor IP(101) and master controller (111); The input data line (115) of the output data line of master controller serial line interface (114), master controller serial line interface is realized and outside data information transfer by the serial debugging interface (109) of master controller; External interface debugging enable signal (117) and external interface debugging trigger pip (118) are all delivered to debugging mode controller (108), are used for judging and trigger polycaryon processor entering debugging mode;
Described debugging mode controller (108) comprises or door, with door (14), a not gate, the first two-way selector switch (9), the second two-way selector switch (10), the first trigger (11), the second trigger (12), the 3rd trigger (15); With per two microprocessor IP debugging control modules (103) to debugging mode controller (108) send enter debugging mode marking signal (1) deliver to one or, will be above-mentioned all or door output deliver to simultaneously again another or; The result of above-mentioned another or door output again with by master controller (111) to debugging mode controller (108) send enter debugging mode marking signal (2) deliver to the 3rd or; The result of above-mentioned the 3rd or an output delivers to the S1 port of the first two-way selector switch (9), and external interface debugging trigger pip (118) inputs to the S0 port of the first two-way selector switch (9) simultaneously; Debug reset signal (116) inputs to the reset terminal R of the first trigger (11) and the reset terminal R of the second trigger (12) simultaneously; The reset signal of external interface (119) inputs to the control end C of the first two-way selector switch (9) and the control end C of the second two-way selector switch (10) simultaneously; One road signal of external interface debugging enable signal (117) is delivered to the S0 port of the second two-way selector switch (10); Polycaryon processor internal clock signal (7) inputs to respectively the CLK port of the first trigger (11) and the CLK port of the second trigger (12); The D port of the first two-way selector switch (9) is connected to the D port of the first trigger (11); The D port of the second two-way selector switch (10) is connected to the D port of the second trigger (12); The S1 port of the second two-way selector switch (10) is connected to the reset terminal R of the second trigger (12); The Q port of the second trigger (12) is delivered to and door (14) with another road signal of external interface debugging enable signal (117) behind the door simultaneously through non-, and above-mentioned result with door (14) output is delivered to the 3rd trigger (15) clock period of delay; Result after the delay exports the S port of the second trigger (12) to; The signal of the Q port output of the Q port of the second trigger (12) and the first trigger (11) sends to each microprocessor IP(101 as debugging answer signal (107)) and master controller (111).
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| CN108415842A (en) * | 2018-03-21 | 2018-08-17 | 杭州中天微系统有限公司 | Multi-core processor |
| CN108768667A (en) * | 2018-04-24 | 2018-11-06 | 中船重工（武汉）凌久电子有限责任公司 | A method of for internuclear network communication in multi-core processor piece |
| CN109344018A (en) * | 2018-09-10 | 2019-02-15 | 深圳忆联信息系统有限公司 | Multi-core CPU test method, device, computer equipment and storage medium |
| CN113608788A (en) * | 2021-07-13 | 2021-11-05 | 芯来智融半导体科技(上海)有限公司 | Multi-core processor debugging method, processor, electronic device and storage medium |
| WO2022053030A1 (en) * | 2020-09-14 | 2022-03-17 | 北京希姆计算科技有限公司 | Chip debugging method, chip, and chip debugging system |
| CN115357515A (en) * | 2022-10-19 | 2022-11-18 | 北京紫光芯能科技有限公司 | Debugging method and device of multi-core system, computer equipment and storage medium |
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| WO2022053030A1 (en) * | 2020-09-14 | 2022-03-17 | 北京希姆计算科技有限公司 | Chip debugging method, chip, and chip debugging system |
| CN113608788A (en) * | 2021-07-13 | 2021-11-05 | 芯来智融半导体科技(上海)有限公司 | Multi-core processor debugging method, processor, electronic device and storage medium |
| CN115357515A (en) * | 2022-10-19 | 2022-11-18 | 北京紫光芯能科技有限公司 | Debugging method and device of multi-core system, computer equipment and storage medium |
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