CN103354244B - Oxide semiconductor thin-film transistor and manufacture method thereof - Google Patents
Oxide semiconductor thin-film transistor and manufacture method thereof Download PDFInfo
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- CN103354244B CN103354244B CN201310273449.0A CN201310273449A CN103354244B CN 103354244 B CN103354244 B CN 103354244B CN 201310273449 A CN201310273449 A CN 201310273449A CN 103354244 B CN103354244 B CN 103354244B
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Abstract
A kind of oxide semiconductor thin-film transistor comprises source electrode, drain electrode, channel layer, insulating barrier, the first conductor and the second conductor.Channel layer to be arranged between source electrode and drain electrode and with source electrode and drain separated from one another.Insulating barrier covers source electrode, drain electrode and channel layer.First conductor is at least arranged in the first opening of insulating barrier to contact with source electrode and channel layer.Second conductor is at least arranged in the second opening of insulating barrier to contact with drain electrode and channel layer.
Description
Technical field
The invention relates to a kind of thin-film transistor and manufacture method thereof, and relate to a kind of oxide semiconductor thin-film transistor and manufacture method thereof especially.
Background technology
Generally speaking, the multiple assemblies (as assemblies such as grid, source electrode, drain electrode, channel layer and pixel electrodes) forming oxide semiconductor thin-film transistor can make with multiple tracks processing procedure respectively.Wherein, source electrode and drain electrode are usually to make with processing procedure, and channel layer makes with another road processing procedure, and the sequencing of this twice processing procedure does not limit.For example, after first can forming source electrode and drain electrode, then channel layer is formed again, wherein, when forming the material layer of channel layer with film-plating process, environmental gas (as oxygen plasma, oxygen plasma) in processing procedure may form layer of oxide layer on the surface of source electrode and drain electrode.Then, when channel layer covers source electrode and drain electrode, between channel layer and source electrode and this oxide layer can be there is between channel layer and drain electrode and there is higher contact impedance, oxide semiconductor thin-film transistor assembly reliability is therefore destroyed.
Another manufacture method is, after first forming channel layer, then forms source electrode and drain electrode.But, with etch process patterned conductive layer with formed source electrode and drain electrode time, source electrode and drain electrode between channel layer may because etching solution impact and suffer damage, therefore destroy the assembly reliability of oxide semiconductor thin-film transistor.
Summary of the invention
Oxide semiconductor thin-film transistor of the present invention comprises one source pole, a drain electrode, a channel layer, an insulating barrier, one first conductor and one second conductor.Channel layer to be arranged between source electrode and drain electrode and with source electrode and drain separated from one another.Insulating barrier covers source electrode, drain electrode and channel layer.First conductor is at least arranged in one first opening of insulating barrier to contact with source electrode and channel layer.Second conductor is at least arranged in one second opening of insulating barrier to contact with drain electrode and channel layer.
The manufacture method of oxide semiconductor thin-film transistor of the present invention, comprises the following steps.Form one source pole and a drain electrode.A channel layer is formed between source electrode and drain electrode, and channel layer and source electrode and drain separated from one another.Form an insulating barrier, insulating barrier covers source electrode, drain electrode and channel layer.To one first opening being less than insulating barrier, form one first conductor, the first conductor contacts with source electrode and channel layer.To one second opening being less than insulating barrier, form one second conductor, the second conductor contacts with drain electrode and channel layer.
Based on above-mentioned, the manufacture method of oxide semiconductor thin-film transistor of the present invention, channel layer is separated setting with source electrode and drain electrode, first conductor is connected with source electrode with channel layer through the first opening of insulating barrier, second conductor is connected with drain electrode with channel layer through the second opening of insulating barrier, therefore forms the high oxide semiconductor thin-film transistor of assembly reliability.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Figure 1A to Fig. 1 E is the manufacturing process upper schematic diagram of the oxide semiconductor thin-film transistor of one embodiment of the invention.
Fig. 2 A to Fig. 2 E is respectively the generalized section of the hatching line A-A ' along Figure 1A to Fig. 1 E.
Fig. 3 is the manufacturing process upper schematic diagram of the oxide semiconductor thin-film transistor of another embodiment of the present invention.
Fig. 4 is respectively the generalized section of the hatching line A-A ' along Fig. 3.
Fig. 5 A to Fig. 5 B is the manufacturing process upper schematic diagram of the oxide semiconductor thin-film transistor of another embodiment of the present invention.
Fig. 6 A to Fig. 6 B is respectively the generalized section of the hatching line A-A ' along Fig. 5 A to Fig. 5 B.
[primary clustering symbol description]
100,100a, 100b: oxide semiconductor thin-film transistor
102: substrate
110: gate insulation layer
120: insulating barrier
A-A ': hatching line
C1: the first conductor
C2: the second conductor
CH: channel layer
D: drain electrode
DL: data wire
G: grid
H1: the first opening
H2: the second opening
H3: the three opening
P, P1, P2: dot structure
PE: pixel electrode
S: source electrode
SL: scan line
Embodiment
Figure 1A to Fig. 1 E is the manufacturing process upper schematic diagram of the oxide semiconductor thin-film transistor of one embodiment of the invention.Fig. 2 A to Fig. 2 E is respectively the generalized section of the hatching line A-A ' along Figure 1A to Fig. 1 E.Should be noted that, the upper schematic diagram of Figure 1A to Fig. 1 E omits and illustrates part rete with the clear position illustrating each assembly.Please refer to Figure 1A and Fig. 2 A, on a substrate 102, form scan line SL, a grid G and a gate insulation layer 110.In detail, sputter process first can be used to form a gate material layers, define scan line SL and grid G with a patterning process more afterwards.Patterning process is such as one optical cover process, and it comprises light blockage coating (photo resist coat), exposure (exposure), development (develop), step such as etching (etch), stripping (strip) etc.The material of gate material layers comprises alloy or other conductor materials be applicable to of chromium (Cr), molybdenum (Mo), aluminium (Al), titanium (Ti) or above-mentioned metal.Gate material layers also can be the stack layer of above-mentioned metal or metal alloy.
Then, on substrate 102, gate insulation layer 110 is formed.Gate insulation layer 110 cover gate G and scan line SL.Gate insulation 110 can pass through electricity slurry Assisted Chemical Vapor Shen long-pending (plasma-enhanced chemical vapor deposition, PECVD), and its material comprises silicon dioxide (SiO
2), nitrogen oxide (SiNx) or other be applicable to insulating material.
Please refer to Figure 1B and Fig. 2 B, on substrate 102, form a data wire DL, one source pole S and a drain D.In detail, sputter process first can be used to form source/drain electrode material layer, define data wire DL, source S and drain D with a patterning process more afterwards.Patterning process is such as one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.The material of source/drain material layer comprises alloy or other conductor materials be applicable to of chromium (Cr), molybdenum (Mo), aluminium (Al), titanium (Ti) or above-mentioned metal.Source/drain material layer also can be the stack layer of above-mentioned metal or metal alloy.
Please refer to Fig. 1 C and Fig. 2 C, on substrate 102, between source S and drain D, form channel layer CH.In detail, on substrate 102, form a channel material layer, channel material layer at least covers source S and drain D.The material of channel material layer comprises semi-conducting material, as polysilicon or amorphous silicon.Define channel layer CH with a patterning process more afterwards, channel layer CH is arranged at above grid G.Patterning process is such as one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.Channel layer CH is separated with source S and arranges and be separated setting with drain D, therefore channel layer CH with do not have between source S and drain D entity contacts.In other words, channel layer CH does not cover source S and drain D, therefore, does not overlap each other between channel layer and source S, and does not overlap each other between channel layer CH and drain electrode.
In the present embodiment, process gas when forming channel material layer may on the surface of source S and drain D formation one oxide layer.When with above-mentioned patterning process definition channel layer CH, arrange (namely channel layer CH does not cover source S and drain D) because channel layer CH is separated with source S and drain D, therefore can pass through above-mentioned patterning process and remove oxide layer on the surface of source S and drain D in the lump.For example, can pass through the etching step of patterning process, make etching solution and oxide layer carry out reacting oxide layer to be removed.
In addition, also can after formation channel layer CH, optionally carry out a surface treatment program and the oxide layer on the surface of source S and drain D is removed.Thus, can determine that the surface of source S and drain D does not exist oxide layer further.Surface treatment program is such as Wet-type etching, dry-etching or other surface treatment programs be applicable to.
Please refer to Fig. 1 D and Fig. 2 D, on substrate 102, form an insulating barrier 120.Insulating barrier 120 at least covers pole source S, drain D, channel layer CH and substrate 102, and channel layer CH is between insulating barrier 120 and grid G.In detail, form an insulation material layer on substrate 102, its material comprises silicon dioxide or other insulating material be applicable to.Insulation material layer can pass through electricity slurry Assisted Chemical Vapor Shen long-pending (PECVD) or sputter program is formed.Insulating barrier 120 is defined again afterwards with a patterning process.Patterning process is such as one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.
Insulating barrier 120 has one first opening H1 separated from one another and one second opening H2.First opening H1 exposes adjacent part source S and local channel layer CH simultaneously.For example, the first opening H1 exposes a top surface of part source S and a top surface of local channel layer CH, or the first opening H1 only can expose a sidewall of source S and a sidewall of channel layer CH.
Second opening H2 exposes adjacent part drain D and local channel layer CH simultaneously.For example, the second opening H2 exposes a top surface of part drain D and a top surface of local channel layer CH, or the second opening H2 only can expose a sidewall of drain D and a sidewall of channel layer CH.
Please refer to Fig. 1 E and Fig. 2 E, on substrate 102, form one first conductor C 1 and one second conductor C2.In detail, form a conductor material layer on substrate 102, its material comprises tin indium oxide, indium zinc oxide or other electric conducting materials be applicable to.The first conductor C1 and the second conductor C2 is defined again afterwards with a patterning process.Patterning process is such as one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.First conductor C1 and the second conductor C2 of the present embodiment can be formed simultaneously.In other embodiments, the first conductor C1 and the second conductor C2 also can successively be formed, and the present invention does not limit the formation order of the first conductor C1 and the second conductor C2.
First conductor C1 is at least arranged in the first opening H1, and the source S exposed with the first opening H1 and channel layer CH couple.In the present embodiment, the first conductor C1 more lies along on the surface of insulating barrier 120.For example, the first conductor C1 can directly contact with source S and channel layer CH and be electrically connected.As previously mentioned, owing to the surface of source S almost there is no oxide layer, therefore lower contact impedance can be had between the first conductor C1 and source S.
Second conductor C2 is at least arranged in the second opening H2, and the drain D exposed with the second opening H2 and channel layer CH couple.Thus, the oxide semiconductor thin-film transistor 100 of the present embodiment can roughly be completed.In the present embodiment, the second conductor C2 more lies along region beyond the second opening H2 using as pixel electrode PE.In other words, the present embodiment is using pixel electrode PE as the bonding conductor between drain D and channel layer CH.Thus, scan line SL, data wire DL, pixel electrode PE and oxide semiconductor thin-film transistor 100 just can form a dot structure P.
Second conductor C2 can directly contact with drain D and channel layer CH and be electrically connected.As previously mentioned, owing to the surface of drain D almost there is no oxide layer, therefore lower contact impedance can be had between the second conductor C2 and drain D.In addition, because the present embodiment first makes source S and drain D, then make channel layer CH, therefore do not have in known technology when patterned source S and drain D, the problem that etching solution damages channel layer CH produces.Accordingly, the oxide semiconductor thin-film transistor 100 of the present embodiment can have good assembly reliability.
In addition, simultaneously the present embodiment illustrates as drain D and the bonding conductor of channel layer CH and the pixel electrode PE of dot structure P for the second conductor C2.But, the present invention is not limited thereto.In other embodiments, the second conductor C2 of oxide semiconductor thin-film transistor 100a also only can connect drain D and channel layer CH.And, when formation first conductor C1, the second conductor C2, more form a pixel electrode PE.Pixel electrode PE is separated with the second conductor C2, and pixel electrode PE through insulating barrier 120 one the 3rd opening H3 with drain electrode be electrically connected, as shown in Figure 3 and 4.Certainly, the present embodiment does not limit the production order of the first conductor C1, the second conductor C2 and pixel electrode PE.
The oxide semiconductor thin-film transistor 100 of previous embodiment and oxide semiconductor thin-film transistor 100a all illustrate for bottom gate polar form oxide semiconductor thin-film transistor (bottom gatetype thin film transistor).The present invention is not limited thereto.Fig. 5 A to Fig. 5 B is the manufacturing process upper schematic diagram of the oxide semiconductor thin-film transistor of another embodiment of the present invention.Fig. 6 A to Fig. 6 B is respectively the generalized section of the hatching line A-A ' along Fig. 5 A to Fig. 5 B.The manufacturing process of the present embodiment is similar to previous embodiment, and its different part is: the present embodiment is after completing the first conductor C1 and the second conductor C2, then forms gate insulation layer 110 and grid G.In other words, the oxide semiconductor thin-film transistor 100b of the present embodiment is top grid type oxide semiconductor thin-film transistor (top gate type thin film transistor).
In detail, after carrying out the manufacturing process as Figure 1B to Fig. 1 E and Fig. 2 B to Fig. 2 E, the structure as shown in Fig. 5 A and Fig. 6 A can be formed.Source S, drain D and channel layer CH are directly arranged on substrate 102, and sequentially complete the making of insulating barrier 120, first conductor C1 and the second conductor C2.
Please refer to Fig. 5 B and Fig. 6 B, on substrate 102, form gate insulation layer 110.Gate insulation layer 110 covers source S, drain D, channel layer CH, insulating barrier 120, first conductor C1 and the second conductor C2.Gate insulation layer 110 can pass through electricity slurry Assisted Chemical Vapor Shen long-pending (plasma-enhanced chemical vapor deposition, PECVD), and its material comprises silicon dioxide (SiO
2), nitrogen oxide (SiNx) or other be applicable to insulating material.
Then, on gate insulation layer 110, scan line SL and grid G is formed.So far, the making of oxide semiconductor thin-film transistor 100b is roughly completed.Scan line SL, data wire DL, oxide semiconductor thin-film transistor 100b and pixel electrode PE form a dot structure P2.In detail, sputter process first can be used to form a gate material layers, define scan line SL and grid G with a patterning process more afterwards.Patterning process is such as one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.The material of gate material layers comprises alloy or other conductor materials be applicable to of chromium (Cr), molybdenum (Mo), aluminium (Al), titanium (Ti) or above-mentioned metal.Gate material layers also can be the stack layer of above-mentioned metal or metal alloy.In the present embodiment, grid G is arranged in fact above channel layer CH, and gate insulation layer 110 is arranged between grid G and channel layer CH.
In sum, in the manufacture method of oxide semiconductor thin-film transistor of the present invention, form channel layer separated from one another and source electrode and drain electrode.Couple source electrode and channel layer through the first conductor, and couple drain electrode and channel layer through the second conductor.Almost do not have oxide layer between source electrode and channel layer, and almost do not have oxide layer between drain electrode and channel layer, therefore oxide semiconductor thin-film transistor can have good assembly reliability.In addition, because the present invention first makes source electrode and drain electrode, then make channel layer, therefore do not have be known in patterned source and drain electrode time, etching solution damage channel layer problem produce.Accordingly, oxide semiconductor thin-film transistor of the present invention can have good assembly reliability.
Claims (10)
1. an oxide semiconductor thin-film transistor, is characterized in that, comprising:
One source pole and a drain electrode;
One channel layer, to be arranged between this source electrode and this drain electrode and with this source electrode and this drain electrode separated from one another;
One insulating barrier, cover this source electrode, this drain electrode and this channel layer, this insulating barrier has one first opening and one second opening, and this first opening exposes this source electrode of part and this channel layer of part, and this second opening exposes this drain electrode of part and this channel layer of part;
One first conductor, is at least arranged in this first opening to couple with this source electrode and this channel layer; And
One second conductor, is at least arranged in this second opening to couple with this drain electrode and this channel layer.
2. oxide semiconductor thin-film transistor as claimed in claim 1, it is characterized in that, this first conductor and this second conductor belong to same rete.
3. oxide semiconductor thin-film transistor as claimed in claim 1, is characterized in that, also comprise a grid, and this channel layer to be arranged on this grid and between this insulating barrier and this grid.
4. oxide semiconductor thin-film transistor as claimed in claim 1, it is characterized in that, also comprise a grid, this grid is arranged on this channel layer, and this insulating barrier is between this grid and this channel layer.
5. a manufacture method for oxide semiconductor thin-film transistor, is characterized in that, comprising:
Form one source pole and a drain electrode;
Between this source electrode and this drain electrode, form a channel layer, and this channel layer and this source electrode and this drain electrode separated from one another;
Form an insulating barrier, this insulating barrier covers this source electrode, this drain electrode and this channel layer, this insulating barrier has one first opening and one second opening, and this first opening exposes this source electrode of part and this channel layer of part, and this second opening exposes this drain electrode of part and this channel layer of part;
Form one first conductor to being less than in this first opening, this first conductor and this source electrode and this channel layer couple; And
Form one second conductor to being less than in this second opening, this second conductor and this drain electrode and this channel layer couple.
6. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5, it is characterized in that, this first conductor and this second conductor are formed simultaneously.
7. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5, is characterized in that, is also included in before forming this source electrode and this drain electrode, forms a grid, and this channel layer to be arranged on this grid and between this insulating barrier and this grid.
8. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5, it is characterized in that, be also included in after forming this first conductor and this second conductor, form a grid, this grid is arranged on this channel layer, and this insulating barrier is between this grid and this channel layer.
9. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5, is characterized in that, is also included in after forming this channel layer and before forming this insulating barrier, carries out a surface treatment program to this source electrode and this drain electrode.
10. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5, it is characterized in that, this insulating barrier has more one the 3rd opening, and the 3rd opening exposes a part for this drain electrode, and the manufacture method of this oxide semiconductor thin-film transistor more comprises:
After this insulating barrier of formation, form a pixel electrode to being less than in the 3rd opening, and this pixel electrode and this drain electrode couple.
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| CN102244006A (en) * | 2011-06-14 | 2011-11-16 | 华映视讯（吴江）有限公司 | Thin film transistor and manufacturing method thereof |
| US8119465B1 (en) * | 2010-10-26 | 2012-02-21 | Au Optronics Corporation | Thin film transistor and method for fabricating the same |
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| KR20130017034A (en) * | 2011-08-09 | 2013-02-19 | 엘지디스플레이 주식회사 | Thin film transistor array substrate and the method of manufacturing the substrate |
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| US8119465B1 (en) * | 2010-10-26 | 2012-02-21 | Au Optronics Corporation | Thin film transistor and method for fabricating the same |
| CN102244006A (en) * | 2011-06-14 | 2011-11-16 | 华映视讯（吴江）有限公司 | Thin film transistor and manufacturing method thereof |
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Effective date of registration: 20230609 Address after: Lake 558, Fen Hu Town, Wujiang District, Jiangsu, Suzhou Patentee after: Wujiang FenHu technology entrepreneurship Service Co.,Ltd. Address before: No. 555 Jiangxing East Road, Tongli District, Wujiang Economic Development Zone, Suzhou City, Jiangsu Province, 215217 Patentee before: CPTW (WUJIANG) Co.,Ltd. Patentee before: Chunghwa Picture Tubes, Ltd. |