CN103354244A - Oxide semiconductor film transistor and manufacturing method thereof - Google Patents
Oxide semiconductor film transistor and manufacturing method thereof Download PDFInfo
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- CN103354244A CN103354244A CN2013102734490A CN201310273449A CN103354244A CN 103354244 A CN103354244 A CN 103354244A CN 2013102734490 A CN2013102734490 A CN 2013102734490A CN 201310273449 A CN201310273449 A CN 201310273449A CN 103354244 A CN103354244 A CN 103354244A
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Abstract
The invention provides an oxide semiconductor film transistor including a source electrode, a drain electrode, a channel layer, an insulting layer, a first conductor and a second conductor. The channel layer is arranged between the source electrode and the drain electrode and is isolated from the source electrode and the drain electrode. An insulating layer covers the source electrode, the drain electrode and the channel layer. The first layer is at least disposed in a first opening of the insulating layer, so as to contact with the source electrode and the channel layer. The second conductor is at least disposed in a second opening of the insulating layer, so as to contact with the drain electrode and the channel layer.
Description
Technical field
The invention relates to a kind of thin-film transistor and manufacture method thereof, and particularly relevant for a kind of oxide semiconductor thin-film transistor and manufacture method thereof.
Background technology
Generally speaking, a plurality of assemblies (such as assemblies such as grid, source electrode, drain electrode, channel layer and pixel electrodes) that form oxide semiconductor thin-film transistor can be made with the multiple tracks processing procedure respectively.Wherein, source electrode is made with same processing procedure usually with drain electrode, and channel layer is made with another road processing procedure, and the sequencing of this twice processing procedure does not limit.For example, can form first source electrode and the drain electrode after, then form again channel layer, wherein, when forming the material layer of channel layer with film-plating process, the environmental gas in the processing procedure (such as oxygen plasma, oxygen plasma) may form layer of oxide layer on the surface of source electrode and drain electrode.Then, when channel layer covers source electrode and drains, can there be this oxide layer and has higher contact impedance between channel layer and the source electrode and between channel layer and the drain electrode, therefore destroy oxide semiconductor thin-film transistor assembly reliability.
Another manufacture method is, form channel layer first after, form again source electrode and drain electrode.But, with the etch process patterned conductive layer when forming source electrode and drain electrode, the channel layer between source electrode and drain electrode may suffer damage because of the impact of etching solution, therefore destroys the assembly reliability of oxide semiconductor thin-film transistor.
Summary of the invention
Oxide semiconductor thin-film transistor of the present invention comprises one source pole, a drain electrode, a channel layer, an insulating barrier, one first conductor and one second conductor.Channel layer is arranged between source electrode and the drain electrode and with source electrode and drain separated from one another.Insulating barrier covers source electrode, drain electrode and channel layer.The first conductor is arranged in one first opening of insulating barrier at least to contact with source electrode and channel layer.The second conductor is arranged in one second opening of insulating barrier at least to contact with drain electrode and channel layer.
The manufacture method of oxide semiconductor thin-film transistor of the present invention comprises the following steps.Form one source pole and a drain electrode.Between source electrode and drain electrode, form a channel layer, and channel layer and source electrode and drain separated from one another.Form an insulating barrier, insulating barrier covers source electrode, drain electrode and channel layer.Form one first conductor to one first opening that is less than insulating barrier, the first conductor contacts with source electrode and channel layer.Form one second conductor to one second opening that is less than insulating barrier, the second conductor contacts with drain electrode and channel layer.
Based on above-mentioned, the manufacture method of oxide semiconductor thin-film transistor of the present invention, channel layer is separated setting with source electrode and drain electrode, the first conductor is connected with source electrode with channel layer through the first opening of insulating barrier, the second conductor is connected with drain electrode with channel layer through the second opening of insulating barrier, therefore forms the high oxide semiconductor thin-film transistor of assembly reliability.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Figure 1A to Fig. 1 E looks schematic diagram on the manufacturing process of oxide semiconductor thin-film transistor of one embodiment of the invention.
Fig. 2 A to Fig. 2 E is respectively along the generalized section of the hatching line A-A ' of Figure 1A to Fig. 1 E.
Fig. 3 looks schematic diagram on the manufacturing process of oxide semiconductor thin-film transistor of another embodiment of the present invention.
Fig. 4 is respectively along the generalized section of the hatching line A-A ' of Fig. 3.
Fig. 5 A to Fig. 5 B looks schematic diagram on the manufacturing process of oxide semiconductor thin-film transistor of another embodiment of the present invention.
Fig. 6 A to Fig. 6 B is respectively along the generalized section of the hatching line A-A ' of Fig. 5 A to Fig. 5 B.
[primary clustering symbol description]
100,100a, 100b: oxide semiconductor thin-film transistor
102: substrate
110: gate insulation layer
120: insulating barrier
A-A ': hatching line
C1: the first conductor
C2: the second conductor
CH: channel layer
D: drain electrode
DL: data wire
G: grid
H1: the first opening
H2: the second opening
H3: the 3rd opening
P, P1, P2: dot structure
PE: pixel electrode
S: source electrode
SL: scan line.
Embodiment
Figure 1A to Fig. 1 E looks schematic diagram on the manufacturing process of oxide semiconductor thin-film transistor of one embodiment of the invention.Fig. 2 A to Fig. 2 E is respectively along the generalized section of the hatching line A-A ' of Figure 1A to Fig. 1 E.What must illustrate is to look the schematic diagram omission on Figure 1A to Fig. 1 E and illustrate the part rete with the clear position that illustrates each assembly.Please refer to Figure 1A and Fig. 2 A, on a substrate 102, form one scan line SL, a grid G and a gate insulation layer 110.In detail, can use first sputter process to form a gate material layers, define scan line SL and grid G with a patterning process more afterwards.Patterning process for example is one optical cover process, and it comprises light blockage coating (photo resist coat), exposure (exposure), the steps such as (develop), etching (etch), stripping (strip) of developing.The material of gate material layers comprises alloy or other conductor materials that is fit to of chromium (Cr), molybdenum (Mo), aluminium (Al), titanium (Ti) or above-mentioned metal.Gate material layers also can be above-mentioned metal or the stack layer of metal alloy.
Then, on substrate 102, form gate insulation layer 110.Gate insulation layer 110 cover gate G and scan line SL.Gate insulation 110 can see through electricity slurry assistant chemical gas phase Shen long-pending (plasma-enhanced chemical vapor deposition, PECVD), and its material comprises silicon dioxide (SiO
2), the insulating material that is fit to of nitrogen oxide (SiNx) or other.
Please refer to Figure 1B and Fig. 2 B, on substrate 102, form a data wire DL, one source pole S and a drain D.In detail, can use first sputter process to form the source/drain electrode material layer, define data wire DL, source S and drain D with a patterning process more afterwards.Patterning process for example is one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.The material of source/drain material layer comprises alloy or other conductor materials that is fit to of chromium (Cr), molybdenum (Mo), aluminium (Al), titanium (Ti) or above-mentioned metal.The source/drain material layer also can be above-mentioned metal or the stack layer of metal alloy.
Please refer to Fig. 1 C and Fig. 2 C, between source S and drain D, forming channel layer CH on the substrate 102.In detail, form a channel material layer on substrate 102, the channel material layer covers source S and drain D at least.The material of channel material layer comprises semi-conducting material, such as polysilicon or amorphous silicon.Define channel layer CH with a patterning process more afterwards, channel layer CH is arranged at the grid G top.Patterning process for example is one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.Channel layer CH separates with source S and arranges and separate setting with drain D, so does not have to contact on the entity between channel layer CH and source S and the drain D.In other words, channel layer CH does not cover source S and drain D, therefore, does not overlap each other between channel layer and the source S, and does not overlap each other between channel layer CH and the drain electrode.
Process gas when in the present embodiment, forming the channel material layer may form an oxide layer on the surface of source S and drain D.When with above-mentioned patterning process definition channel layer CH, because channel layer CH separates setting (being that channel layer CH does not cover source S and drain D) with source S and drain D, therefore can see through the lip-deep oxide layer that above-mentioned patterning process removes source S and drain D in the lump.For example, can see through the etching step of patterning process, make etching solution and oxide layer react that oxide layer is removed.
In addition, also can be after forming channel layer CH, optionally carry out a surface treatment program the lip-deep oxide layer of source S and drain D is removed.Thus, can determine further that there is not oxide layer in the surface of source S and drain D.The surface treatment program for example is Wet-type etching, dry-etching or other surface treatment programs that is fit to.
Please refer to Fig. 1 D and Fig. 2 D, on substrate 102, form an insulating barrier 120.Insulating barrier 120 covers utmost point source S, drain D, channel layer CH and substrate 102 at least, and channel layer CH is between insulating barrier 120 and grid G.In detail, form an insulation material layer on substrate 102, its material comprises silicon dioxide or other insulating material that is fit to.Insulation material layer can see through electricity slurry assistant chemical gas phase Shen long-pending (PECVD) or the sputter program forms.Define insulating barrier 120 with a patterning process more afterwards.Patterning process for example is one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.
Insulating barrier 120 has one first opening H1 separated from one another and one second opening H2.The first opening H1 exposes adjacent part source S and local channel layer CH simultaneously.For example, the first opening H1 exposes a top surface of part source S and the top surface of local channel layer CH, and perhaps the first opening H1 can only expose a sidewall of source S and the sidewall of channel layer CH.
The second opening H2 exposes adjacent part drain D and local channel layer CH simultaneously.For example, the second opening H2 exposes a top surface of part drain D and the top surface of local channel layer CH, and perhaps the second opening H2 can only expose a sidewall of drain D and the sidewall of channel layer CH.
Please refer to Fig. 1 E and Fig. 2 E, on substrate 102, form one first conductor C1 and one second conductor C2.In detail, form a conductor material layer on substrate 102, its material comprises tin indium oxide, indium zinc oxide or other electric conducting materials that is fit to.Define the first conductor C1 and the second conductor C2 with a patterning process more afterwards.Patterning process for example is one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.The first conductor C1 and the second conductor C2 of present embodiment can form simultaneously.In other embodiments, the first conductor C1 and the second conductor C2 also can successively form, and the present invention does not limit the formation order of the first conductor C1 and the second conductor C2.
The first conductor C1 is arranged in the first opening H1 at least, and couples with source S and channel layer CH that the first opening H1 exposes.In the present embodiment, the first conductor C1 more lies along on the surface of insulating barrier 120.For example, the first conductor C1 can directly contact and be electrically connected with source S and channel layer CH.As previously mentioned, owing to almost there is not the existence of oxide layer on the surface of source S, therefore can have lower contact impedance between the first conductor C1 and the source S.
The second conductor C2 is arranged in the second opening H2 at least, and couples with drain D and channel layer CH that the second opening H2 exposes.Thus, can roughly finish the oxide semiconductor thin-film transistor 100 of present embodiment.In the present embodiment, the second conductor C2 more lies along zone beyond the second opening H2 with as pixel electrode PE.In other words, present embodiment is as the bonding conductor between drain D and the channel layer CH with pixel electrode PE.Thus, scan line SL, data wire DL, pixel electrode PE and oxide semiconductor thin-film transistor 100 just can form a dot structure P.
The second conductor C2 can directly contact and be electrically connected with drain D and channel layer CH.As previously mentioned, owing to almost there is not the existence of oxide layer on the surface of drain D, therefore can have lower contact impedance between the second conductor C2 and the drain D.In addition, because present embodiment makes first source S and drain D, make channel layer CH again, therefore do not have in the known technology when patterned source S and drain D, the problem that etching solution damages channel layer CH produces.Accordingly, the oxide semiconductor thin-film transistor 100 of present embodiment can have good assembly reliability.
In addition, present embodiment be take the second conductor C2 simultaneously as the pixel electrode PE of the bonding conductor of drain D and channel layer CH and dot structure P as the example explanation.Yet, the invention is not restricted to this.In other embodiments, the second conductor C2 of oxide semiconductor thin-film transistor 100a also can only connect drain D and channel layer CH.And, when forming the first conductor C1, the second conductor C2, more form a pixel electrode PE.Pixel electrode PE separates with the second conductor C2, and pixel electrode PE is through one the 3rd opening H3 and drain electrode electric connection of insulating barrier 120, such as Fig. 3 and shown in Figure 4.Certainly, present embodiment does not limit the production order of the first conductor C1, the second conductor C2 and pixel electrode PE.
The oxide semiconductor thin-film transistor 100 of previous embodiment and oxide semiconductor thin-film transistor 100a are all take bottom gate polar form oxide semiconductor thin-film transistor (bottom gate type thin film transistor) as the example explanation.The invention is not restricted to this.Fig. 5 A to Fig. 5 B looks schematic diagram on the manufacturing process of oxide semiconductor thin-film transistor of another embodiment of the present invention.Fig. 6 A to Fig. 6 B is respectively along the generalized section of the hatching line A-A ' of Fig. 5 A to Fig. 5 B.The manufacturing process of present embodiment is similar to previous embodiment, and its different part is: present embodiment is after finishing the first conductor C1 and the second conductor C2, forms gate insulation layer 110 and grid G again.In other words, the oxide semiconductor thin-film transistor 100b of present embodiment is top grid type oxide semiconductor thin-film transistor (top gate type thin film transistor).
In detail, carry out the manufacturing process such as Figure 1B to Fig. 1 E and Fig. 2 B to Fig. 2 E after, can form the structure shown in Fig. 5 A and Fig. 6 A.Source S, drain D and channel layer CH directly are arranged on the substrate 102, and sequentially finish the making of insulating barrier 120, the first conductor C1 and the second conductor C2.
Please refer to Fig. 5 B and Fig. 6 B, on substrate 102, form gate insulation layer 110.Gate insulation layer 110 covers source S, drain D, channel layer CH, insulating barrier 120, the first conductor C1 and the second conductor C2.Gate insulation layer 110 can see through electricity slurry assistant chemical gas phase Shen long-pending (plasma-enhanced chemical vapor deposition, PECVD), and its material comprises silicon dioxide (SiO
2), the insulating material that is fit to of nitrogen oxide (SiNx) or other.
Then, on gate insulation layer 110, form scan line SL and grid G.So far, roughly finish the making of oxide semiconductor thin-film transistor 100b.Scan line SL, data wire DL, oxide semiconductor thin-film transistor 100b and pixel electrode PE form a dot structure P2.In detail, can use first sputter process to form a gate material layers, define scan line SL and grid G with a patterning process more afterwards.Patterning process for example is one optical cover process, and it comprises the steps such as light blockage coating, exposure, development, etching, stripping.The material of gate material layers comprises alloy or other conductor materials that is fit to of chromium (Cr), molybdenum (Mo), aluminium (Al), titanium (Ti) or above-mentioned metal.Gate material layers also can be above-mentioned metal or the stack layer of metal alloy.In the present embodiment, grid G is arranged in fact channel layer CH top, and gate insulation layer 110 is arranged between grid G and the channel layer CH.
In sum, in the manufacture method of oxide semiconductor thin-film transistor of the present invention, form semiconductor separated from one another and source electrode and drain electrode.See through the first conductor and couple source electrode and channel layer, and couple drain electrode and channel layer through the second conductor.Almost do not have oxide layer to exist between source electrode and the channel layer, and almost do not have the existence of oxide layer between drain electrode and the channel layer, so oxide semiconductor thin-film transistor can have good assembly reliability.In addition, because the present invention makes first source electrode and drain electrode, make channel layer again, therefore do not have when being known in patterned source and drain electrode, the problem that etching solution damages channel layer produces.Accordingly, oxide semiconductor thin-film transistor of the present invention can have good assembly reliability.
Claims (10)
1. an oxide semiconductor thin-film transistor is characterized in that, comprising:
One source pole and a drain electrode;
One channel layer is arranged between this source electrode and this drain electrode and separated from one another with this source electrode and this drain electrode;
One insulating barrier, cover this source electrode, this drain electrode and this channel layer, this insulating barrier has one first opening and one second opening, and this first opening exposes this source electrode of part and this channel layer of part, and this second opening exposes this drain electrode of part and this channel layer of part;
One first conductor is arranged in this first opening at least to couple with this source electrode and this channel layer; And
One second conductor is arranged in this second opening at least to couple with this drain electrode and this channel layer.
2. oxide semiconductor thin-film transistor as claimed in claim 1 is characterized in that, this first conductor and this second conductor belong to same rete.
3. oxide semiconductor thin-film transistor as claimed in claim 1 is characterized in that, also comprises a grid, and this channel layer is arranged on this grid and between this insulating barrier and this grid.
4. oxide semiconductor thin-film transistor as claimed in claim 1 is characterized in that, also comprises a grid, and this grid is arranged on this channel layer, and this insulating barrier is between this grid and this channel layer.
5. the manufacture method of an oxide semiconductor thin-film transistor is characterized in that, comprising:
Form one source pole and a drain electrode;
In this source electrode and should form a channel layer between the drain electrode, and this channel layer is with this source electrode and should drain separated from one another;
Form an insulating barrier, this insulating barrier covers this source electrode, this drain electrode and this channel layer, this insulating barrier has one first opening and one second opening, and this first opening exposes this source electrode of part and this channel layer of part, and this second opening exposes this drain electrode of part and this channel layer of part;
Form one first conductor in this first opening to being less than, this first conductor and this source electrode and this channel layer couple; And
Form one second conductor in this second opening to being less than, this second conductor and this drain electrode and this channel layer couple.
6. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5 is characterized in that, this first conductor and this second conductor form simultaneously.
7. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5 is characterized in that, also is included in to form before this source electrode and this drain electrode, forms a grid, and this channel layer is arranged on this grid and between this insulating barrier and this grid.
8. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5, it is characterized in that, also be included in after this first conductor of formation and this second conductor, form a grid, this grid is arranged on this channel layer, and this insulating barrier is between this grid and this channel layer.
9. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5 is characterized in that, also is included in to form after this channel layer and form before this insulating barrier, and this source electrode and this drain electrode are carried out a surface treatment program.
10. the manufacture method of oxide semiconductor thin-film transistor as claimed in claim 5, it is characterized in that, this insulating barrier has more one the 3rd opening, and the 3rd opening exposes the part of this drain electrode, and the manufacture method of this oxide semiconductor thin-film transistor more comprises:
After forming this insulating barrier, form a pixel electrode in the 3rd opening to being less than, and this pixel electrode and this drain electrode couple.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103728803A (en) * | 2013-12-26 | 2014-04-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
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| US8119465B1 (en) * | 2010-10-26 | 2012-02-21 | Au Optronics Corporation | Thin film transistor and method for fabricating the same |
| KR20130017034A (en) * | 2011-08-09 | 2013-02-19 | 엘지디스플레이 주식회사 | Thin film transistor array substrate and the method of manufacturing the substrate |
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| US20070018163A1 (en) * | 2004-03-12 | 2007-01-25 | Chiang Hai Q | Semiconductor device |
| US8119465B1 (en) * | 2010-10-26 | 2012-02-21 | Au Optronics Corporation | Thin film transistor and method for fabricating the same |
| CN102244006A (en) * | 2011-06-14 | 2011-11-16 | 华映视讯（吴江）有限公司 | Thin film transistor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103728803A (en) * | 2013-12-26 | 2014-04-16 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN103728803B (en) * | 2013-12-26 | 2015-04-08 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| WO2015096396A1 (en) * | 2013-12-26 | 2015-07-02 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, and display device |
| US9620524B2 (en) | 2013-12-26 | 2017-04-11 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, display device |
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