CN103545252B - Array base palte and preparation method thereof, liquid crystal indicator - Google Patents
Array base palte and preparation method thereof, liquid crystal indicator Download PDFInfo
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- CN103545252B CN103545252B CN201310452105.6A CN201310452105A CN103545252B CN 103545252 B CN103545252 B CN 103545252B CN 201310452105 A CN201310452105 A CN 201310452105A CN 103545252 B CN103545252 B CN 103545252B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 44
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 96
- 238000002161 passivation Methods 0.000 claims abstract description 64
- 238000009413 insulation Methods 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 36
- 230000008569 process Effects 0.000 claims abstract description 25
- 238000000059 patterning Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims description 350
- 229920002120 photoresistant polymer Polymers 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 37
- 239000004020 conductor Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 239000012774 insulation material Substances 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 238000004070 electrodeposition Methods 0.000 claims description 14
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 8
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- 238000005516 engineering process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
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- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000001704 evaporation Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
Abstract
The problem the invention provides a kind of array base palte and preparation method thereof, liquid crystal indicator, belong to technical field of liquid crystal display, it can solve, and existing ADS pattern array substrate manufacturing process is complicated, transmitance is low, driving effect bad.Array base palte preparation method of the present invention comprises: by using the patterning processes of ladder exposure to form the figure comprising grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode in substrate; Wherein, described gate insulation layer does not exceed above grid and grid line; The substrate completing abovementioned steps forms passivation layer, and forms the source electrode via hole and drain via that are connected with semiconductor layer in the passivation layer; The substrate completing abovementioned steps is formed by patterning processes the figure comprising source electrode, drain electrode, and is formed the figure comprising the second transparency electrode by patterning processes; Wherein, described source electrode, draining is electrically connected with semiconductor layer respectively by source electrode via hole, drain via.
Description
Technical field
The invention belongs to technical field of liquid crystal display, be specifically related to a kind of array base palte and preparation method thereof, liquid crystal indicator.
Background technology
The liquid crystal indicator of senior super dimension field translative mode (ADS pattern) has the plurality of advantages such as visual angle is wide, transmitance is high, definition is high, therefore becomes a kind of important model of liquid crystal indicator.
As shown in Figure 1, in the array base palte of ADS pattern, first transparency electrode 11 of tabular, grid 21/ grid line 22 of thin-film transistor is all located in substrate 9, gate insulation layer 31 covers the first transparency electrode 11, grid 21, grid line 22, (semiconductor layer 41 adds ohmic contact layer to be provided with semiconductor layer 41 above grid 21, namely transition zones etc. form the active area of thin-film transistor), passivation layer 5, planarization layer 6 covers semiconductor layer 41 and gate insulation layer 31 successively, planarization layer 6 is provided with data wire Data and the second transparency electrode 12, data wire Data, second transparency electrode 12 respectively with the source electrode 71 of thin-film transistor, drain electrode 72 electrical connection, and the second transparency electrode 12 is gap electrode, be positioned at above the first transparency electrode 11.Although of course it is to be understood that it is with the second transparency electrode 12 for pixel electrode above, the first transparency electrode 11 is the situation of public electrode is example; If but the first transparency electrode 11 is pixel electrode (namely it is electrically connected with drain electrode 72), the second transparency electrode 12 is public electrode, is also feasible.
As shown in Figure 1, in the array base palte of existing ADS pattern, grid 21/ grid line 22, semiconductor layer 41, first transparency electrode 11 need to manufacture in different patterning processes respectively, and being these structures of manufacture at least needs to carry out 3 photoetching, therefore its complicated process of preparation.
Simultaneously, gate insulation layer 31 covers whole substrate 9, and namely gate insulation layer 31 also has distribution between the first transparency electrode 11 and the second transparency electrode 12, and gate insulation layer 31 1 aspect of this position increases two interelectrode distances, reduce electric field strength and electric capacity, have impact on driving effect; On the other hand, this gate insulation layer 31 also can affect printing opacity, thus reduces the transmitance of array base palte.
Summary of the invention
Technical problem to be solved by this invention comprises, complicated for existing ADS pattern array substrate manufacturing process, drive the problem that effect is bad, transmitance is low, provide a kind of manufacturing process simple, drive effective, that transmitance is high array base palte and preparation method thereof, liquid crystal indicator.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte preparation method, and it comprises:
Step 1: by using the patterning processes of ladder exposure to form the figure comprising grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode in substrate; Wherein, described gate insulation layer does not exceed above grid and grid line;
Step 2: form passivation layer in the substrate completing abovementioned steps, and form the source electrode via hole and drain via that are connected with semiconductor layer in the passivation layer;
Step 3: formed the figure comprising source electrode, drain electrode in the substrate completing abovementioned steps by patterning processes, and the figure comprising the second transparency electrode is formed by patterning processes; Wherein, described source electrode, draining is electrically connected with semiconductor layer respectively by source electrode via hole, drain via.
Wherein, " patterning processes " comprises the step such as formation rete, coating photoresist, exposure, development, etching, stripping photoresist, and it is by unwanted part in above-mentioned steps removing rete, thus makes the remainder of rete form required figure.
Wherein, " ladder exposure " refers to the exposure carrying out in various degree to the diverse location of photoresist layer, thus makes the photoresist layer after development different at the thickness of diverse location, to complete follow-up patterning processes.
In array base palte preparation method of the present invention, grid line/grid, gate insulation layer, semiconductor layer, the first transparency electrode are being formed with in a patterning processes simultaneously, i.e. its needs single exposure (1Mask) technique, and therefore its preparation technology is simple; Meanwhile, because the gate insulation layer of its array base palte does not exceed above grid and grid line, therefore there is no gate insulation layer between its first transparency electrode, the second transparency electrode, therefore its two interelectrode apart from short, electric field strength is high, electric capacity is large, drives effective; And gate insulation layer also can not to light through having an impact, therefore transmitance is high.
Preferably, described step 1 specifically comprises:
Step 11, in substrate, form transparent conductive material layer, insulation material layer, semiconductor material layer, photoresist layer successively;
Step 12, photoresist layer ladder exposed and develops, gate location is made to retain the photoresist layer of the first thickness, grid line position retains the photoresist layer of the second thickness, first transparency electrode position retains the photoresist layer of the 3rd thickness, all the other positions are without photoresist layer, wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness;
Step 13, removing are without semiconductor material layer, insulation material layer, the transparent conductive material layer in photoresist region;
The photoresist layer of step 14, removing the 3rd thickness, makes the semiconductor material layer of the first transparency electrode position expose;
Step 15, remove semiconductor material layer, the insulation material layer of the first transparency electrode position, form the figure of the first transparency electrode;
Step 16, removing thickness equal the photoresist layer of grid line position remaining photoresist layer thickness, and the semiconductor layer of grid line position is exposed;
The semiconductor material layer of step 17, removing grid line position, forms the figure of grid line;
Step 18, remove remaining photoresist layer, form the figure of grid, gate insulation layer, semiconductor layer.
Further preferably, described step 17 specifically comprises: the semiconductor material layer of removing grid line position, and removes the insulation material layer of grid line position, forms the figure of grid line.
Further preferably, described step 11 also comprises: form grid metal level at transparent conductive material layer and insulating material interlayer; Described step 13 also comprises: remove the grid metal level without photoresist region; Described step 15 also comprises: the grid metal level removing the first transparency electrode position.
Preferably, described ladder exposure is realized by grayscale mask plate or intermediate tone mask plate.
Preferably, described semiconductor layer is made up of metal oxide semiconductor material.
Preferably, described first transparency electrode is public electrode, and described second transparency electrode is pixel electrode, is electrically connected with drain electrode.
Further preferably, described source electrode, drain electrode, the second transparency electrode are all formed over the passivation layer.
Further preferably, described source electrode, drain electrode are formed over the passivation layer; At formation source electrode, between drain electrode and formation second transparency electrode, also comprise: form planarization layer, and formed in planarization layer and the first via hole be connected that drains; Described second transparency electrode is formed on planarization layer, and is electrically connected with drain electrode by the first via hole.
Preferably, described first transparency electrode is electrically connected with drain electrode, and be pixel electrode, described second transparency electrode is public electrode; Described step 2 also comprises: form the second via hole be connected with the first transparency electrode in the passivation layer, described drain electrode is electrically connected with the first transparency electrode by the second via hole.
Further preferably, described source electrode, drain electrode are formed over the passivation layer; At formation source electrode, between drain electrode and formation second transparency electrode, also comprise: form planarization layer; Described second transparency electrode is formed on planarization layer.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte, and it comprises grid, grid line, gate insulation layer, semiconductor layer, the first transparency electrode, the second transparency electrode, source electrode, drain electrode, passivation layer; Wherein
Described passivation layer covers grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode;
Described second transparency electrode is positioned at above passivation layer;
Described source electrode, drain electrode to be arranged in above passivation layer and to be electrically connected with semiconductor layer respectively by the source electrode via hole of passivation layer, drain via;
Described grid, grid line comprise transparent conductive material layer;
Described gate insulation layer does not exceed above grid and grid line.
Array base palte of the present invention is by above-mentioned manufacture technics, therefore its preparation technology is simple; Meanwhile, because its gate insulation layer does not exceed above grid and grid line, therefore there is no gate insulation layer between its first transparency electrode, the second transparency electrode, therefore its two interelectrode apart from short, electric field strength is high, electric capacity is large, drives effective; And gate insulation layer also can not to light through having an impact, therefore transmitance is high.
Preferably, described gate insulation layer is identical with semiconductor layer figure, and is only positioned at above grid.
Preferably, described grid, grid line also comprise the grid metal level be positioned on transparent conductive material layer.
Preferably, described semiconductor layer is made up of metal-oxide semiconductor (MOS).
Preferably, described second transparency electrode is pixel electrode, and be electrically connected with drain electrode, described first transparency electrode is public electrode.
Further preferably, described source electrode, drain electrode, the second transparency electrode are located on passivation layer.
Further preferably, be located at the planarization layer on passivation layer, described source electrode, drain electrode are located on passivation layer, and described second transparency electrode is located on planarization layer, and are electrically connected with drain electrode by the first via hole in planarization layer.
Preferably, described first transparency electrode is electrically connected with drain electrode by the second via hole in passivation layer, and described first transparency electrode is pixel electrode, and described second transparency electrode is public electrode.
Further preferably, described array base palte also comprises: be located at the planarization layer on passivation layer, and described second transparency electrode is located on planarization layer, and described source electrode, drain electrode are located on passivation layer.
The technical scheme that solution the technology of the present invention problem adopts is a kind of liquid crystal indicator, and it comprises above-mentioned array base palte.
Because liquid crystal indicator of the present invention comprises above-mentioned array base palte, thus its manufacturing process simple, drive effective, transmitance is high.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of existing ADS pattern array substrate;
Fig. 2 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Fig. 3 is the cross-sectional view along AA ' face of Fig. 2;
Fig. 4 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Fig. 5 is the cross-sectional view along AA ' face of Fig. 4;
Fig. 6 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Fig. 7 is the cross-sectional view along AA ' face of Fig. 6;
Fig. 8 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Fig. 9 is the cross-sectional view along AA ' face of Fig. 8;
Figure 10 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Figure 11 is the cross-sectional view along AA ' face of Figure 10;
Figure 12 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Figure 13 is the cross-sectional view along AA ' face of Figure 12;
Figure 14 is the plan structure schematic diagram of array base palte in preparation process of embodiments of the invention 2;
Figure 15 is the cross-sectional view along AA ' face of Figure 14;
Figure 16 is the plan structure schematic diagram of the array base palte of embodiments of the invention 2;
Figure 17 is the cross-sectional view along AA ' face of Figure 16;
Figure 18 is the cross-sectional view of the array base palte of embodiments of the invention 3;
Wherein Reference numeral is: 1, transparent conductive material layer; 11, the first transparency electrode; 12, the second transparency electrode; 2, grid metal level; 21, grid; 22, grid line; 3, insulation material layer; 31, gate insulation layer; 4, semiconductor material layer; 41, semiconductor layer; 5, passivation layer; 6, planarization layer; 71, source electrode; 72, drain; 8, photoresist layer; 9, substrate; Data, data wire; Q1, gate location; Q2, grid line position; Q3, the first transparency electrode position; Q4, all the other positions.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment 1:
The present embodiment provides a kind of array base palte preparation method, and it comprises:
Step 1: by using the patterning processes of ladder exposure to form the figure comprising grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode in substrate; Wherein, described gate insulation layer does not exceed above grid and grid line;
Step 2: form passivation layer in the substrate completing abovementioned steps, and form the source electrode via hole and drain via that are connected with semiconductor layer in the passivation layer;
Step 3: formed the figure comprising source electrode, drain electrode in the substrate completing abovementioned steps by patterning processes, and the figure comprising the second transparency electrode is formed by patterning processes; Wherein, described source electrode, draining is electrically connected with semiconductor layer respectively by source electrode via hole, drain via.
Wherein, " patterning processes " comprises the step such as formation rete, coating photoresist, exposure, development, etching, stripping photoresist, and it is by unwanted part in above-mentioned steps removing rete, thus makes the remainder of rete form required figure.
Wherein, " ladder exposure " refers to the exposure carrying out in various degree to the diverse location of photoresist layer, thus makes the photoresist layer after development different at the thickness of diverse location, to complete follow-up patterning processes.
In the array base palte preparation method of the present embodiment, grid line/grid, gate insulation layer, semiconductor layer, the first transparency electrode are being formed with in a patterning processes simultaneously, i.e. its needs single exposure (1Mask) technique, and therefore its preparation technology is simple; Meanwhile, because the gate insulation layer of its array base palte does not exceed above grid and grid line, therefore there is no gate insulation layer between its first transparency electrode, the second transparency electrode, therefore its two interelectrode apart from short, electric field strength is high, electric capacity is large, drives effective; And gate insulation layer also can not to light through having an impact, therefore transmitance is high.
Embodiment 2:
The present embodiment provides a kind of preparation method of array base palte, and as shown in Fig. 2 to Figure 17, it comprises the following steps:
S101, successively formation transparent conductive material layer 1, insulation material layer 3, semiconductor material layer 4, and photoresist layer 8 is coated with on semiconductor material layer 4.
Preferably, between transparent conductive material layer 1 and insulation material layer 3, also can form grid metal level 2.
Wherein, transparent conductive material layer 1 is formed by the material of transparent and electrically conductive, such as tin indium oxide (ITO), and it is for the formation of the first transparency electrode 11, grid 21, grid line 22.
Grid metal level 2 is made up of the metal or alloy such as molybdenum, aluminium usually, is mainly used in jointly forming grid 21, grid line 22 with transparent conductive material layer 1, thus improves the electric conductivity of grid 21, grid line 22.
Obviously, owing to having transparent conductive material layer 1, therefore also can not form grid metal level 2 in theory, and directly form grid 21, grid line 22 with transparent conductive material layer 1.If should be appreciated that in this step and do not form grid metal level 2, then in subsequent step, the operation of " removing grid metal level 2 " is also no longer carried out accordingly.
Insulation material layer 3 can be silicon nitride or silica etc., and it is mainly used in forming gate insulation layer 31, thus makes grid 21 and semiconductor layer 41 insulate and form the moving interface of charge carrier.
Semiconductor material layer 4 is formed by semi-conducting material, and it is mainly used in forming semiconductor layer 41.Preferably, described semiconductor layer 41 (semiconductor material layer 4) is made up of metal-oxide semiconductor (MOS), such as, be oxidized gallium indium zinc (IGZO).
Wherein, substrate 9 also can be pre-formed with the known structure such as resilient coating; Each layer also can adopt other known materials; The method forming each layer can be the known technique such as sputtering, evaporation, chemical vapour deposition (CVD), coating.Because the material, technique, parameter etc. of the various rete of above-mentioned formation are all known, therefore these contents are all not described in detail in the present embodiment.
S102, as shown in Figure 2 and Figure 3, photoresist layer 8 ladder is exposed and developed, the photoresist layer 8 of the first thickness is retained at gate location Q1, grid line position Q2 retains the photoresist layer 8 of the second thickness, first transparency electrode position Q3 retains the photoresist layer 8 of the 3rd thickness, all the other positions Q4 is without photoresist layer 8, and wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness.
That is, by carrying out exposure in various degree to the diverse location of photoresist layer 8, make the photoresist layer after development 8 be divided into three kinds of different thickness as shown in Figure 3, also have subregion in addition without photoresist layer 8.
Preferably, ladder exposure realizes by grayscale mask plate or intermediate tone mask plate.
S103, removing, without semiconductor material layer 4, insulation material layer 3, grid metal level 2, the transparent conductive material layer 1 in photoresist region, obtain structure as shown in Figure 4, Figure 5.
That is, by methods such as etchings, removing is without semiconductor material layer 4, insulation material layer 3, grid metal level 2, the transparent conductive material layer 1 of photoresist region Q4 successively, thus is separated with the transparent conductive material layer 1 in other regions by the transparent conductive material layer 1 of the first transparency electrode region Q1.
Wherein, etching can adopt known method to carry out, and according to the difference of layers of material and etching technics, can be remove multiple rete in once etching, also can be each etching only removing rete simultaneously; Because etching technics, etching parameters etc. are all known, therefore these contents are all not described in detail in the present embodiment.
The photoresist layer 8 of S104, removing the 3rd thickness, makes the semiconductor material layer 4 of the first transparency electrode position Q3 expose, obtains structure as shown in Figure 6, Figure 7.
That is, by the photoresist layer 8 of ashing (Ashing) according to thickness difference technique removing the 3rd thickness of photoresist layer 8, the photoresist layer 8 of such first transparency electrode position Q3 is completely removed, its semiconductor material layer 4 exposes, and the photoresist layer 8 of gate location Q1 and grid line position Q2 is just corresponding thinning, thus obtain structure as shown in Figure 6, Figure 7.
Wherein, due to the characteristic of cineration technics, therefore the photoresist layer 8 area reality of gate location Q1 and grid line position Q2 also can reduce a little, but can not produce materially affect because of it to the structure of final products, therefore not shown.
S105, as shown in Figure 8, Figure 9, remove semiconductor material layer 4, insulation material layer 3, the grid metal level 2 of the first transparency electrode position Q3, form the figure of the first transparency electrode 11 (being generally plate electrode).
Now, because the photoresist layer 8 of the first transparency electrode position Q3 is removed, therefore semiconductor material layer 4, insulation material layer 3, the grid metal level 2 of this position is removed successively by etching technics, transparent conductive material layer 1 is exposed, forms the figure of transparent first transparency electrode 11.
S106, removing thickness equal the photoresist layer 8 of grid line position Q2 remaining photoresist layer 8 thickness, the semiconductor layer 41 of grid line position Q2 is exposed, obtains structure as shown in Figure 10, Figure 11.
That is, by the remaining photoresist layer 8 (its thickness can equal the second thickness and deduct the 3rd thickness) of cineration technics removing grid line position Q2, the semiconductor layer 41 at this place is exposed, simultaneously, the photoresist layer 8 of gate location Q1 continues thinning, thus obtains structure as shown in Figure 10, Figure 11.
The semiconductor material layer 4 of S107, removing grid line position Q2, and preferably remove this position simultaneously, form the figure of grid line 22, obtain structure as shown in Figure 12 and Figure 13.
That is, removed semiconductor material layer 4, the insulation material layer 3 of grid line position Q2 by etching technics successively, grid metal level 2 is exposed, form the figure of grid line 22.
Wherein, in this step, the insulation material layer 3 of grid line position Q2 is also eliminated together, thus there is no gate insulation layer 31 above grid line 22 in final products, the graphs coincide of gate insulation layer 31 and semiconductor layer 41, and be all only positioned at above grid 21; The advantage of this technique is, certain corrosive agent can be selected directly once semiconductor material layer 4 and insulation material layer 3 to be removed, thus Simplified flowsheet.
But, should be appreciated that if in this step, only the semiconductor material layer 4 of removing grid line position Q2, and to retain insulation material layer 3 be also feasible; Like this, in the final product, still have gate insulation layer 31 (but semiconductor layer 41 is only positioned at above grid 21) above grid line 22, this gate insulation layer 31 can increase grid line 22 and data wire spacing, thus the coupling capacitance between both reductions.
Wherein, the present embodiment is what to have the situation of grid metal level 2 be example, and namely its grid line 22 is made up of jointly grid metal level 2 and transparent conductive material layer 1, thus improves the electric conductivity of grid line 22; But should be appreciated that then now grid line position Q2 only remains transparent conductive material layer 1 if do not form grid metal level 2 in step S101, namely grid line 22 also can be directly made up of transparent conductive material.
S108, as shown in Figure 14, Figure 15, remove whole remaining photoresist layer 8, form the figure of grid 21, gate insulation layer 31, semiconductor layer 41.
That is, peel off whole remaining photoresist layer 8 (i.e. the photoresist layer 8 of gate location Q1), semiconductor layer 41 is exposed, form the figure of grid 21, gate insulation layer 31, semiconductor layer 41.
Visible, in the present embodiment, only just prepared the figure of grid line 22/ grid 21, gate insulation layer 31, semiconductor layer 41, first transparency electrode 11 by single exposure, therefore its exposure frequency obviously reduces, preparation method is simple simultaneously.
Simultaneously, in the array base palte of the present embodiment, semiconductor layer 41 does not exceed above grid 21 and grid line 22, namely gate insulation layer 31 is not had between its first transparency electrode 11 and second transparency electrode 12, therefore the distance between the first transparency electrode 11 and the second transparency electrode 12 is short, and electric field strength and electric capacity greatly, drive effective, simultaneously gate insulation layer 31 also can not to light through having an impact, therefore transmitance is high.
S109, formation passivation layer 5 (PVX), and in passivation layer 5, form the source electrode via hole and drain via that are connected with semiconductor layer 41.
Wherein, passivation layer 5 can be made up of the material such as silicon nitride, silica, and its Main Function is protection semiconductor layer 41, and makes other structural insulations of the first transparency electrode 11 and top.
S110, on passivation layer 5, to be formed source electrode 71, drain electrode 72 by patterning processes, this source electrode 71, drain electrode 72 are electrically connected with semiconductor layer 41 respectively by source electrode via hole, drain via, thus form thin-film transistor structure.
S111, preferred, form planarization layer 6, and formed in planarization layer 6 and 72 the first via holes be connected that drain.
Wherein, planarization layer 6 is made up of materials such as resins usually, and its section difference being mainly used in the structures such as thin-film transistor to cause " is filled and led up ", makes the surface integral of array base palte is tending towards smooth, so that follow-up alignment films even film layer is formed, and be beneficial to the uniform scratch of friction orientation technique.
S112, on planarization layer 6, to be formed the second transparency electrode 12, second transparency electrode 12 by patterning processes be connected with drain electrode 72 by the first via hole in planarization layer 6; Wherein, this second transparency electrode 12 is gap electrode, is positioned at above the first transparency electrode 11, thus array base palte prepared by the method for the present embodiment is the array base palte of ADS pattern.
In the present embodiment, the second transparency electrode 12 connects drain electrode 72, and namely the second transparency electrode 12 is pixel electrodes, and the first transparency electrode 11 is public electrode.
Wherein, when formation the second transparency electrode 12, also can form data wire Data (being connected with source electrode 71 by via hole), public electrode wire (not shown, will to be connected with the first transparency electrode 11 by via hole) simultaneously, thus obtain the structure as shown in Figure 16,17.
Certainly, data wire Data, public electrode wire etc. also can be formed in other steps, such as can form data wire Data, public electrode wire in the step forming source electrode 71 and drain electrode 72 simultaneously, now data wire Data is directly connected with source electrode 71, and public electrode wire is still connected with the first transparency electrode 11; Or, independent step also can be used to form data wire Data, public electrode wire etc. at the same time or separately; At this, it is no longer limited.
Of course it is to be understood that above planarization layer 6 not necessarily, if when not having planarization layer 6, then source electrode 71, drain electrode the 72, second transparency electrode 12 all can be formed on passivation layer 5, and the second transparency electrode 12 directly connects drain electrode 72.
S113, continuation form other known structure (not shown)s such as alignment film, complete the preparation of array base palte.
Embodiment 3:
As shown in figure 18, the present embodiment provides a kind of preparation method of array base palte, and its front 8 step (S201-S208) is identical with front 8 steps (S101-S108) of embodiment 2, and difference is, the present embodiment from the 9th step for:
S209, formation passivation layer 5 (PVX), and in passivation layer 5, form the source electrode via hole and drain via that are connected with semiconductor layer 41, and the second via hole be connected with the first transparency electrode 11.
S210, on passivation layer 5, to be formed source electrode 71, drain electrode 72 by patterning processes, this source electrode 71, drain electrode 72 are electrically connected with semiconductor layer 41 respectively by source electrode via hole, drain via, thus form thin-film transistor structure.
Meanwhile, drain electrode 72 is also connected with the first transparency electrode 11 by the second via hole.
That is, in the present embodiment, the first transparency electrode 11 connects drain electrode 72, and namely the first transparency electrode 11 is pixel electrodes, and the second transparency electrode 12 is public electrode.
S211, preferred, form planarization layer 6 (ESLayer).
S212, on planarization layer, form the second transparency electrode 12 by patterning processes, this second transparency electrode 12 is gap electrode, is positioned at above the first transparency electrode 11.
Wherein, while formation second transparency electrode 12, also can form data wire Data (being connected with source electrode 71 by via hole), public electrode wire (not shown, to be electrically connected with the second transparency electrode 12).
Now, because public electrode wire needs to be electrically connected with the second transparency electrode 12, therefore it is preferably formed with the second transparency electrode 12 simultaneously; Data wire Data then still can be formed in the step manufacturing source electrode 71 and drain electrode 72 simultaneously.
Of course it is to be understood that above planarization layer 6 not necessarily, if when not having planarization layer 6, then source electrode 71, drain electrode the 72, second transparency electrode 12 all can be formed in (now the second transparency electrode 12 is not connected with drain electrode 72) on passivation layer 5.
S213, continuation form other known structure (not shown)s such as alignment film, complete the preparation of array base palte.
Visible, in array base palte preparation method of the present invention, can be the first transparency electrode 11 as pixel electrode, the second transparency electrode 12 as public electrode, also can be the first transparency electrode 11 as public electrode, the second transparency electrode 12 is as pixel electrode; Only be which electrode is connected with drain electrode 72 with the difference of upper type, which electrode is connected with public electrode wire, and the change of this connected mode realizes by the conventional meanses such as hole site of crossing adjusted in the preparation order of each lead-in wire, each layer, be not described in detail at this.
Should be appreciated that the non-essential structure of planarization layer 6 in above two embodiments, if do not form planarization layer 6, then data wire Data, the second transparency electrode 12 etc. can be formed directly on passivation layer 5.
Be to be understood that, in above two embodiments, position, the preparation order of source electrode 71, drain electrode 72, data wire Data, the second transparency electrode 12, public electrode wire etc. all can carry out multiple change, such as source electrode 71, drain electrode 72 can be formed on passivation layer 5, also can be formed on planarization layer 6 (now also need to be formed via hole in planarization layer 6 to make source electrode 71, drain electrode 72 is electrically connected with semiconductor layer 41); Data wire Data, public electrode wire can be formed on passivation layer 5, also can be formed on planarization layer 6.In a word; no matter how the position of these structures, connected mode change; as long as but the preparation process of array base palte comprises the step forming grid 21, grid line 22, gate insulation layer 31, semiconductor layer 41, first transparency electrode 11 with patterning processes simultaneously; and its gate insulation layer 31 does not exceed above grid 21 and grid line 22, then namely belong to protection scope of the present invention.
Embodiment 4:
As shown in Fig. 2 to Figure 18, the present embodiment provides a kind of array base palte, and it comprises grid 21, grid line 22, gate insulation layer 31, semiconductor layer 41, first transparency electrode 11 (can be plate electrode), the second transparency electrode 12, source electrode 71, drain electrode 72, passivation layer 5.
As shown in Figure 16, Figure 17, in the array base palte of the present embodiment, grid 21, grid line 22 comprise transparent conductive material layer 1.
That is, grid 21, the grid line 22 of the array base palte of the present embodiment can be made up of the material of the first transparency electrode 11, therefore they synchronously can be formed with the first transparency electrode 11, thus simplify preparation technology.
Preferably, grid 21, grid line 22 also comprise the grid metal level 2 be positioned on transparent conductive material layer 1, and namely grid 21, grid line 22 jointly can be made up of transparent conductive material layer 1 and grid metal level 2, thus strengthen its electric conductivity.
Certainly, can there is no grid metal level 2 in theory yet, and directly form grid 21, grid line 22 with transparent conductive material layer 1.
Wherein, gate insulation layer 31 does not exceed above grid 21 and grid line 22; Thus there is no gate insulation layer 31 between the first transparency electrode 11, second transparency electrode 12, therefore two interelectrode apart from short, electric field strength is high, and electric capacity is large, drives effective; And gate insulation layer 31 also can not to light through having an impact, therefore transmitance is high.
Preferably, gate insulation layer 31 is identical with semiconductor layer 41 figure, and is only positioned at above grid 21.
Because gate insulation layer 31 is identical with semiconductor layer 41 figure, therefore they can be formed in once etching simultaneously, and preparation efficiency is high.
Certainly, gate insulation layer 31 also can be different from semiconductor layer 41 figure, and above grid line 22, also have distribution (semiconductor layer 41 is only positioned at above grid 21), can increase the distance between grid line 22 and data wire like this, the coupling capacitance between both reductions.
Preferably, semiconductor layer 41 is made up of metal oxide semiconductor material.
Passivation layer 5 cover gate 21, gate insulation layer 31, semiconductor layer 41, grid line 22, first transparency electrode 11.
And source electrode 71, drain electrode 72 are positioned at above passivation layer 5, and are electrically connected with semiconductor layer 41 respectively by the source electrode via hole in passivation layer 5 and drain via.
Second transparency electrode 12 is positioned at above passivation layer 5, and it can be gap electrode, and is positioned at above the first transparency electrode 11.
As shown in figure 17, in the present embodiment, preferably the second transparency electrode 12 is electrically connected with drain electrode 72, and namely wherein the first transparency electrode 11 is public electrode (it also will be electrically connected with public electrode wire), and the second transparency electrode 12 is pixel electrode.
Now, the second transparency electrode 12 preferably can with source electrode 71, draining together with 72 is all located on passivation layer 5, and directly 72 to connect (also can synchronously with drain electrode 72 being formed) with draining.
Preferably, passivation layer 5 is also coated with planarization layer 6.
When having planarization layer 6, the second transparency electrode 12 is preferably located on planarization layer 6, and source electrode 71, drain electrode 72 still can be located on passivation layer 5, and the second transparency electrode 12 72 to be electrically connected with draining by the first via hole in planarization layer 6.
Preferably, as a kind of mode of the present embodiment, as shown in figure 18, also can be that the first transparency electrode 11 is electrically connected with drain electrode 72 by the second via hole in passivation layer 5, namely the first transparency electrode 11 is pixel electrode, and the second transparency electrode 12 is public electrode (it also will be electrically connected with public electrode wire).
Now, preferred source electrode 71, drain electrode the 72, second transparency electrode 12 are all positioned on passivation layer 5, but the second transparency electrode 12 is not connected with drain electrode 72.
Certainly, preferably, also can comprise the planarization layer 6 covering passivation layer 5 in the array base palte of the present embodiment, when having planarization layer 6, then source electrode 71, drain electrode 72 are preferably formed on passivation layer 5, and the second transparency electrode 12 is preferably located on planarization layer 6.
Certainly, also should comprise other known structure such as public electrode wire, data wire Data, alignment film in the array base palte of the present embodiment, be not described in detail at this.
Embodiment 5:
Present embodiments provide a kind of liquid crystal indicator, it comprises above-mentioned array base palte.Described liquid crystal indicator can be: any product or parts with Presentation Function such as display panels, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
The liquid crystal indicator of the present embodiment comprises above-mentioned array base palte, therefore its preparation technology is simple, driveability good, transmitance is high.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (21)
1. an array base palte preparation method, is characterized in that, comprising:
Step 1: by using the patterning processes of ladder exposure to form the figure comprising grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode in substrate; Wherein, described gate insulation layer does not exceed the edge of grid and grid line;
Step 2: form passivation layer in the substrate completing abovementioned steps, and form the source electrode via hole and drain via that are connected with semiconductor layer in the passivation layer;
Step 3: formed the figure comprising source electrode, drain electrode in the substrate completing abovementioned steps by patterning processes, and the figure comprising the second transparency electrode is formed by patterning processes; Wherein, described source electrode, draining is electrically connected with semiconductor layer respectively by source electrode via hole, drain via.
2. array base palte preparation method according to claim 1, is characterized in that, described step 1 specifically comprises:
Step 11, in substrate, form transparent conductive material layer, insulation material layer, semiconductor material layer, photoresist layer successively;
Step 12, photoresist layer ladder exposed and develops, gate location is made to retain the photoresist layer of the first thickness, grid line position retains the photoresist layer of the second thickness, first transparency electrode position retains the photoresist layer of the 3rd thickness, all the other positions are without photoresist layer, wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness;
Step 13, removing are without semiconductor material layer, insulation material layer, the transparent conductive material layer in photoresist region;
The photoresist layer of step 14, removing the 3rd thickness, makes the semiconductor material layer of the first transparency electrode position expose;
Step 15, remove semiconductor material layer, the insulation material layer of the first transparency electrode position, form the figure of the first transparency electrode;
Step 16, removing thickness equal the photoresist layer of grid line position remaining photoresist layer thickness, and the semiconductor layer of grid line position is exposed;
The semiconductor material layer of step 17, removing grid line position, forms the figure of grid line;
Step 18, remove remaining photoresist layer, form the figure of grid, gate insulation layer, semiconductor layer.
3. array base palte preparation method according to claim 2, is characterized in that, described step 17 specifically comprises:
The semiconductor material layer of removing grid line position, and remove the insulation material layer of grid line position, form the figure of grid line.
4. array base palte preparation method according to claim 2, is characterized in that,
Described step 11 also comprises: form grid metal level at transparent conductive material layer and insulating material interlayer;
Described step 13 also comprises: remove the grid metal level without photoresist region;
Described step 15 also comprises: the grid metal level removing the first transparency electrode position.
5. array base palte preparation method according to claim 1, is characterized in that,
Described ladder exposure is realized by grayscale mask plate or intermediate tone mask plate.
6. array base palte preparation method according to claim 1, is characterized in that,
Described semiconductor layer is made up of metal oxide semiconductor material.
7. array base palte preparation method as claimed in any of claims 1 to 6, is characterized in that,
Described first transparency electrode is public electrode, and described second transparency electrode is pixel electrode, is electrically connected with drain electrode.
8. array base palte preparation method according to claim 7, is characterized in that,
Described source electrode, drain electrode, the second transparency electrode are all formed over the passivation layer.
9. array base palte preparation method according to claim 7, is characterized in that,
Described source electrode, drain electrode are formed over the passivation layer;
At formation source electrode, between drain electrode and formation second transparency electrode, also comprise: form planarization layer, and formed in planarization layer and the first via hole be connected that drains;
Described second transparency electrode is formed on planarization layer, and is electrically connected with drain electrode by the first via hole.
10. array base palte preparation method as claimed in any of claims 1 to 6, is characterized in that,
Described first transparency electrode is electrically connected with drain electrode, and be pixel electrode, described second transparency electrode is public electrode;
Described step 2 also comprises: form the second via hole be connected with the first transparency electrode in the passivation layer, described drain electrode is electrically connected with the first transparency electrode by the second via hole.
11. array base palte preparation methods according to claim 10, is characterized in that,
Described source electrode, drain electrode are formed over the passivation layer;
At formation source electrode, between drain electrode and formation second transparency electrode, also comprise: form planarization layer;
Described second transparency electrode is formed on planarization layer.
12. 1 kinds of array base paltes, it comprises grid, grid line, gate insulation layer, semiconductor layer, the first transparency electrode, the second transparency electrode, source electrode, drain electrode, passivation layer; Wherein
Described passivation layer covers grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode;
Described second transparency electrode is positioned at above passivation layer;
Described source electrode, drain electrode to be arranged in above passivation layer and to be electrically connected with semiconductor layer respectively by the source electrode via hole of passivation layer, drain via;
It is characterized in that,
Described grid, grid line comprise transparent conductive material layer;
Described gate insulation layer does not exceed the edge of grid and grid line.
13. array base paltes according to claim 12, is characterized in that,
Described gate insulation layer is identical with semiconductor layer figure, and is only positioned at above grid.
14. array base paltes according to claim 12, is characterized in that,
Described grid, grid line also comprise the grid metal level be positioned on transparent conductive material layer.
15. array base paltes according to claim 12, is characterized in that,
Described semiconductor layer is made up of metal-oxide semiconductor (MOS).
16., according to claim 12 to the array base palte described in any one in 15, is characterized in that,
Described second transparency electrode is pixel electrode, and be electrically connected with drain electrode, described first transparency electrode is public electrode.
17. array base paltes according to claim 16, is characterized in that,
Described source electrode, drain electrode, the second transparency electrode are located on passivation layer.
18. array base paltes according to claim 12, is characterized in that, also comprise:
Be located at the planarization layer on passivation layer, described source electrode, drain electrode are located on passivation layer, and described second transparency electrode is located on planarization layer, and are electrically connected with drain electrode by the first via hole in planarization layer.
19., according to claim 12 to the array base palte described in any one in 15, is characterized in that,
Described first transparency electrode is electrically connected with drain electrode by the second via hole in passivation layer, and described first transparency electrode is pixel electrode, and described second transparency electrode is public electrode.
20. array base paltes according to claim 19, is characterized in that, also comprise:
Be located at the planarization layer on passivation layer, described second transparency electrode is located on planarization layer, and described source electrode, drain electrode are located on passivation layer.
21. 1 kinds of liquid crystal indicators, is characterized in that, comprising:
As the array base palte in claim 12 to 20 as described in any one.
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| CN104078423A (en) * | 2014-06-24 | 2014-10-01 | 京东方科技集团股份有限公司 | Array substrate manufacturing method, array substrate and display device |
| CN104851894B (en) | 2015-06-03 | 2017-12-22 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN105870136A (en) * | 2016-06-27 | 2016-08-17 | 京东方科技集团股份有限公司 | Array substrate, making method thereof and display device |
| CN106959536A (en) * | 2017-03-31 | 2017-07-18 | 上海中航光电子有限公司 | Display panel, the method and display device for making display panel |
| CN107167974A (en) * | 2017-07-07 | 2017-09-15 | 惠科股份有限公司 | Array base palte and its manufacture method and the display panel of application |
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