CN103545252A - Array substrate and manufacturing method thereof and liquid crystal display device - Google Patents
Array substrate and manufacturing method thereof and liquid crystal display device Download PDFInfo
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- CN103545252A CN103545252A CN201310452105.6A CN201310452105A CN103545252A CN 103545252 A CN103545252 A CN 103545252A CN 201310452105 A CN201310452105 A CN 201310452105A CN 103545252 A CN103545252 A CN 103545252A
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- 239000000758 substrate Substances 0.000 title claims abstract description 21
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 96
- 238000002161 passivation Methods 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000000203 mixture Substances 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims description 350
- 229920002120 photoresistant polymer Polymers 0.000 claims description 58
- 238000009413 insulation Methods 0.000 claims description 55
- 238000002360 preparation method Methods 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 37
- 239000004020 conductor Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
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- 238000004070 electrodeposition Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 4
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- 238000002834 transmittance Methods 0.000 abstract 1
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- 238000005516 engineering process Methods 0.000 description 9
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
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- 238000001704 evaporation Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate and a manufacturing method thereof and a liquid crystal display device, belongs to the technical field of liquid crystal display, and is capable of solving the problems of complicated manufacturing process, low transmittance and poor drive effect of existing ADS (advanced super dimension switch) mode array substrates. The array substrate manufacturing method includes forming a graph comprising a grid line, a grid electrode, a grid insulated layer, a semiconductor layer and a first transparent electrode on a base through the composition process with stepped exposure, then forming a passivation layer on the base and forming a source via and a drain via which are connected with the semiconductor layer in the passivation layer, further, forming a graph comprising a source electrode and a drain electrode on the base through the composition process, and finally forming a graph comprising a second transparent electrode through the composition process. The grid insulated layer is not higher than the grid line and the grid electrode, and the source electrode and the drain electrode are electrically connected with the semiconductor layer through the source via and the drain via respectively.
Description
Technical field
The invention belongs to technical field of liquid crystal display, be specifically related to a kind of array base palte and preparation method thereof, liquid crystal indicator.
Background technology
The liquid crystal indicator of a senior super dimension translative mode (ADS pattern) has the plurality of advantages such as visual angle is wide, transmitance is high, definition is high, therefore become a kind of important model of liquid crystal indicator.
As shown in Figure 1, in the array base palte of ADS pattern, the first tabular transparency electrode 11, grid 21/ grid line 22 of thin-film transistor is all located in substrate 9, gate insulation layer 31 covers the first transparency electrode 11, grid 21, grid line 22, grid 21 tops are provided with semiconductor layer 41, and (semiconductor layer 41 adds ohmic contact layer, transition zones etc. form the active area of thin-film transistor), passivation layer 5, planarization layer 6 covers semiconductor layer 41 and gate insulation layer 31 successively, planarization layer 6 is provided with data wire Data and the second transparency electrode 12, data wire Data, the second transparency electrode 12 respectively with the source electrode 71 of thin-film transistor, drain electrode 72 is electrically connected to, and the second transparency electrode 12 is gap electrode, be positioned at the first transparency electrode 11 tops.Although of course it is to be understood that it is that to take the second transparency electrode 12 be pixel electrode above, the first transparency electrode 11 for the situation of public electrode be example; If but the first transparency electrode 11 is pixel electrode (being that it is electrically connected to drain electrode 72), the second transparency electrode 12 is public electrode, is also feasible.
As shown in Figure 1, in the array base palte of existing ADS pattern, grid 21/ grid line 22, semiconductor layer 41, the first transparency electrode 11 need in different composition technique, to manufacture respectively, and being these structures of manufacture at least needs to carry out 3 photoetching, so its complicated process of preparation.
Simultaneously, gate insulation layer 31 has covered whole substrate 9, and gate insulation layer 31 also has distribution in the first transparency electrode 11 and 12 of the second transparency electrodes, and the gate insulation layer 31 of this position has increased two interelectrode distances on the one hand, reduce electric field strength and electric capacity, affected driving effect; On the other hand, this gate insulation layer 31 also can affect printing opacity, thereby reduces the transmitance of array base palte.
Summary of the invention
Technical problem to be solved by this invention comprises, complicated for existing ADS pattern array substrate manufacturing process, drive the problem that effect is bad, transmitance is low, provide a kind of manufacturing process simple, drive effective, transmitance is high array base palte and preparation method thereof, liquid crystal indicator.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte preparation method, and it comprises:
Step 1: the composition technique by the exposure of use ladder in substrate forms the figure that comprises grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode; Wherein, described gate insulation layer does not exceed grid and grid line top;
Step 2: form passivation layer in the substrate that completes abovementioned steps, and form source electrode via hole and the drain via being connected with semiconductor layer in passivation layer;
Step 3: form by composition technique the figure that comprises source electrode, drain electrode in the substrate that completes abovementioned steps, and form by composition technique the figure that comprises the second transparency electrode; Wherein, described source electrode, drain electrode are electrically connected to semiconductor layer by source electrode via hole, drain via respectively.
Wherein, " composition technique " comprises steps such as forming rete, coating photoresist, exposure, development, etching, stripping photoresist, and it can remove unwanted part in rete by above-mentioned steps, thereby makes the remainder of rete form required figure.
Wherein, " ladder exposure " refer to the diverse location of photoresist layer carried out to exposure in various degree, thereby the photoresist layer after making to develop is different at the thickness of diverse location, to complete follow-up composition technique.
In array base palte preparation method of the present invention, grid line/grid, gate insulation layer, semiconductor layer, the first transparency electrode be with form in a composition technique simultaneously, i.e. its needs single exposure (1Mask) technique, so its preparation technology is simple; Meanwhile, because the gate insulation layer of its array base palte does not exceed grid and grid line top, thus between its first transparency electrode, the second transparency electrode, there is no gate insulation layer, so its two interelectrode distance is short, and electric field strength is high, and electric capacity is large, drives effective; And gate insulation layer can not exert an influence to seeing through of light yet, therefore transmitance is high.
Preferably, described step 1 specifically comprises:
Step 13, remove semiconductor material layer, insulation material layer, transparent conductive material layer without photoresist region;
Step 14, remove the photoresist layer of the 3rd thickness, the semiconductor material layer of the first transparency electrode position is exposed;
Step 15, the semiconductor material layer of removing the first transparency electrode position, insulation material layer, form the figure of the first transparency electrode;
Step 16, remove the photoresist layer that thickness equals grid line position remaining photoresist layer thickness, the semiconductor layer of grid line position is exposed;
Step 17, remove the semiconductor material layer of grid line position, form the figure of grid line;
Step 18, remove remaining photoresist layer, form the figure of grid, gate insulation layer, semiconductor layer.
Further preferably, described step 17 specifically comprises: remove the semiconductor material layer of grid line position, and remove the insulation material layer of grid line position, form the figure of grid line.
Further preferably, described step 11 also comprises: at transparent conductive material layer and insulating material interlayer, form grid metal level; Described step 13 also comprises: remove the grid metal level without photoresist region; Described step 15 also comprises: the grid metal level of removing the first transparency electrode position.
Preferably, described ladder exposure realizes by gray scale mask plate or intermediate tone mask plate.
Preferably, described semiconductor layer is made by metal oxide semiconductor material.
Preferably, described the first transparency electrode is public electrode, and described the second transparency electrode is pixel electrode, is electrically connected to drain electrode.
Further preferably, described source electrode, drain electrode, the second transparency electrode are all formed on passivation layer.
Further preferably, described source electrode, drain electrode are formed on passivation layer; Forming between source electrode, drain electrode and formation the second transparency electrode, also comprising: forming planarization layer, and form the first via hole being connected with drain electrode in planarization layer; Described the second transparency electrode is formed on planarization layer, and is electrically connected to drain electrode by the first via hole.
Preferably, described the first transparency electrode is electrically connected to drain electrode, is pixel electrode, and described the second transparency electrode is public electrode; Described step 2 also comprises: in passivation layer, form the second via hole being connected with the first transparency electrode, described drain electrode is electrically connected to the first transparency electrode by the second via hole.
Further preferably, described source electrode, drain electrode are formed on passivation layer; Forming between source electrode, drain electrode and formation the second transparency electrode, also comprising: forming planarization layer; Described the second transparency electrode is formed on planarization layer.
The technical scheme that solution the technology of the present invention problem adopts is a kind of array base palte, and it comprises grid, grid line, gate insulation layer, semiconductor layer, the first transparency electrode, the second transparency electrode, source electrode, drain electrode, passivation layer; Wherein
Described passivation layer covers grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode;
Described the second transparency electrode is positioned at passivation layer top;
Described source electrode, drain electrode are arranged in passivation layer top and also by source electrode via hole, the drain via of passivation layer, are electrically connected to semiconductor layer respectively;
Described grid, grid line comprise transparent conductive material layer;
Described gate insulation layer does not exceed grid and grid line top.
Array base palte of the present invention can be manufactured by above-mentioned technique, therefore its preparation technology is simple; Meanwhile, because its gate insulation layer does not exceed grid and grid line top, thus between its first transparency electrode, the second transparency electrode, there is no gate insulation layer, so its two interelectrode distance is short, and electric field strength is high, and electric capacity is large, drives effective; And gate insulation layer can not exert an influence to seeing through of light yet, therefore transmitance is high.
Preferably, described gate insulation layer is identical with semiconductor layer figure, and is only positioned at grid top.
Preferably, described grid, grid line also comprise the grid metal level being positioned on transparent conductive material layer.
Preferably, described semiconductor layer is made by metal-oxide semiconductor (MOS).
Preferably, described the second transparency electrode is pixel electrode, is electrically connected to drain electrode, and described the first transparency electrode is public electrode.
Further preferably, described source electrode, drain electrode, the second transparency electrode are located on passivation layer.
Further preferably, be located at the planarization layer on passivation layer, described source electrode, drain electrode are located on passivation layer, and described the second transparency electrode is located on planarization layer, and are electrically connected to drain electrode by the first via hole in planarization layer.
Preferably, described the first transparency electrode is electrically connected to drain electrode by the second via hole in passivation layer, and described the first transparency electrode is pixel electrode, and described the second transparency electrode is public electrode.
Further preferably, described array base palte also comprises: be located at the planarization layer on passivation layer, described the second transparency electrode is located on planarization layer, and described source electrode, drain electrode are located on passivation layer.
The technical scheme that solution the technology of the present invention problem adopts is a kind of liquid crystal indicator, and it comprises above-mentioned array base palte.
Because liquid crystal indicator of the present invention comprises above-mentioned array base palte, thus its manufacturing process simple, drive effective, transmitance is high.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of existing ADS pattern array substrate;
Fig. 2 is the array base palte of an embodiments of the invention 2 plan structure schematic diagram in preparation process;
Fig. 3 is the cross-sectional view along AA ' face of Fig. 2;
Fig. 4 is the array base palte of an embodiments of the invention 2 plan structure schematic diagram in preparation process;
Fig. 5 is the cross-sectional view along AA ' face of Fig. 4;
Fig. 6 is the array base palte of an embodiments of the invention 2 plan structure schematic diagram in preparation process;
Fig. 7 is the cross-sectional view along AA ' face of Fig. 6;
Fig. 8 is the array base palte of an embodiments of the invention 2 plan structure schematic diagram in preparation process;
Fig. 9 is the cross-sectional view along AA ' face of Fig. 8;
Figure 10 is the array base palte of an embodiments of the invention 2 plan structure schematic diagram in preparation process;
Figure 11 is the cross-sectional view along AA ' face of Figure 10;
Figure 12 is the array base palte of an embodiments of the invention 2 plan structure schematic diagram in preparation process;
Figure 13 is the cross-sectional view along AA ' face of Figure 12;
Figure 14 is the array base palte of an embodiments of the invention 2 plan structure schematic diagram in preparation process;
Figure 15 is the cross-sectional view along AA ' face of Figure 14;
Figure 16 is the plan structure schematic diagram of the array base palte of embodiments of the invention 2;
Figure 17 is the cross-sectional view along AA ' face of Figure 16;
Figure 18 is the cross-sectional view of the array base palte of embodiments of the invention 3;
Wherein Reference numeral is: 1, transparent conductive material layer; 11, the first transparency electrode; 12, the second transparency electrode; 2, grid metal level; 21, grid; 22, grid line; 3, insulation material layer; 31, gate insulation layer; 4, semiconductor material layer; 41, semiconductor layer; 5, passivation layer; 6, planarization layer; 71, source electrode; 72, drain electrode; 8, photoresist layer; 9, substrate; Data, data wire; Q1, gate location; Q2, grid line position; Q3, the first transparency electrode position; Q4, all the other positions.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Embodiment 1:
The present embodiment provides a kind of array base palte preparation method, and it comprises:
Step 1: the composition technique by the exposure of use ladder in substrate forms the figure that comprises grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode; Wherein, described gate insulation layer does not exceed grid and grid line top;
Step 2: form passivation layer in the substrate that completes abovementioned steps, and form source electrode via hole and the drain via being connected with semiconductor layer in passivation layer;
Step 3: form by composition technique the figure that comprises source electrode, drain electrode in the substrate that completes abovementioned steps, and form by composition technique the figure that comprises the second transparency electrode; Wherein, described source electrode, drain electrode are electrically connected to semiconductor layer by source electrode via hole, drain via respectively.
Wherein, " composition technique " comprises steps such as forming rete, coating photoresist, exposure, development, etching, stripping photoresist, and it can remove unwanted part in rete by above-mentioned steps, thereby makes the remainder of rete form required figure.
Wherein, " ladder exposure " refer to the diverse location of photoresist layer carried out to exposure in various degree, thereby the photoresist layer after making to develop is different at the thickness of diverse location, to complete follow-up composition technique.
In the array base palte preparation method of the present embodiment, grid line/grid, gate insulation layer, semiconductor layer, the first transparency electrode be with form in a composition technique simultaneously, i.e. its needs single exposure (1Mask) technique, so its preparation technology is simple; Meanwhile, because the gate insulation layer of its array base palte does not exceed grid and grid line top, thus between its first transparency electrode, the second transparency electrode, there is no gate insulation layer, so its two interelectrode distance is short, and electric field strength is high, and electric capacity is large, drives effective; And gate insulation layer can not exert an influence to seeing through of light yet, therefore transmitance is high.
Embodiment 2:
The present embodiment provides a kind of preparation method of array base palte, and as shown in Fig. 2 to Figure 17, it comprises the following steps:
S101, form transparent conductive material layer 1, insulation material layer 3, semiconductor material layer 4 successively, and on semiconductor material layer 4, be coated with photoresist layer 8.
Preferably, between transparent conductive material layer 1 and insulation material layer 3, also can form grid metal level 2.
Wherein, transparent conductive material layer 1 is that the material by transparent and electrically conductive forms, tin indium oxide (ITO) for example, and it is used to form the first transparency electrode 11, grid 21, grid line 22.
Obviously, owing to thering is transparent conductive material layer 1, therefore also can not form grid metal level 2 in theory, and directly with transparent conductive material layer 1, form grid 21, grid line 22.If should be appreciated that in this step and do not form grid metal level 2, the operation of " removing grid metal level 2 " in subsequent step is also no longer carried out accordingly.
Wherein, in substrate 9, also the known structure such as resilient coating can be pre-formed; Each layer also can adopt other known materials; The method that forms each layer can be the known techniques such as sputter, evaporation, chemical vapour deposition (CVD), coating.Because the material of the above-mentioned various retes of formation, technique, parameter etc. are all known, therefore these contents are all not described in detail in the present embodiment.
S102, as shown in Figure 2 and Figure 3, photoresist layer 8 ladders are exposed and developed, the photoresist layer 8 that retains the first thickness at gate location Q1, grid line position Q2 retains the photoresist layer 8 of the second thickness, the first transparency electrode position Q3 retains the photoresist layer 8 of the 3rd thickness, all the other position Q4 are without photoresist layer 8, and wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness.
That is to say, by the diverse location of photoresist layer 8 is carried out to exposure in various degree, make the photoresist layer 8 after developing be divided into as shown in Figure 3 three kinds of different thickness, also have in addition subregion without photoresist layer 8.
Preferably, ladder exposure can realize by gray scale mask plate or intermediate tone mask plate.
S103, remove semiconductor material layer 4, insulation material layer 3, grid metal level 2, transparent conductive material layer 1 without photoresist region, obtain structure as shown in Figure 4, Figure 5.
That is to say, by methods such as etchings, remove successively semiconductor material layer 4, insulation material layer 3, grid metal level 2, transparent conductive material layer 1 without photoresist region Q4, thereby the transparent conductive material layer of the first transparency electrode region Q1 1 and the transparent conductive material layer 1 in other regions are separated.
Wherein, etching can adopt known method to carry out, and according to the difference of layers of material and etching technics, can be to remove a plurality of retes in an etching simultaneously, can be also that each etching is only removed a rete; Because etching technics, etching parameters etc. is all known, therefore these contents are all not described in detail in the present embodiment.
S104, remove the photoresist layer 8 of the 3rd thickness, the semiconductor material layer 4 of the first transparency electrode position Q3 is exposed, obtain structure as shown in Figure 6, Figure 7.
That is to say, by ashing (Ashing), according to the thickness difference technique of photoresist layer 8, remove the photoresist layer 8 of the 3rd thickness, the photoresist layer 8 of such the first transparency electrode position Q3 is thoroughly removed, its semiconductor material layer 4 exposes, and the photoresist layer 8 of gate location Q1 and grid line position Q2 is corresponding attenuate, thereby obtain structure as shown in Figure 6, Figure 7.
Wherein, due to the characteristic of cineration technics, therefore the photoresist layer 8 area reality of gate location Q1 and grid line position Q2 also can dwindle a little, but because it can not produce materially affect to the structure of final products, therefore not shown.
S105, as shown in Figure 8, Figure 9, removes semiconductor material layer 4, insulation material layer 3, the grid metal level 2 of the first transparency electrode position Q3, forms the figure of the first transparency electrode 11 (being generally plate electrode).
Now, because the photoresist layer 8 of the first transparency electrode position Q3 has been removed, therefore can remove successively semiconductor material layer 4, insulation material layer 3, the grid metal level 2 of this position by etching technics, transparent conductive material layer 1 is exposed, form the figure of transparent the first transparency electrode 11.
S106, remove the photoresist layer 8 that thickness equals grid line position Q2 remaining photoresist layer 8 thickness, the semiconductor layer 41 of grid line position Q2 is exposed, obtain structure as shown in Figure 10, Figure 11.
That is to say, by cineration technics, remove the remaining photoresist layer 8 of grid line position Q2 (its thickness can equal the second thickness and deduct the 3rd thickness), the semiconductor layer 41 at this place is exposed, simultaneously, the photoresist layer 8 of gate location Q1 continues attenuate, thereby obtains structure as shown in Figure 10, Figure 11.
S107, remove the semiconductor material layer 4 of grid line position Q2, and preferably remove this position simultaneously, form the figure of grid line 22, obtain structure as shown in Figure 12 and Figure 13.
That is to say, by etching technics, remove successively semiconductor material layer 4, the insulation material layer 3 of grid line position Q2, grid metal level 2 is exposed, form the figure of grid line 22.
Wherein, in this step, the insulation material layer 3 of grid line position Q2 has also been removed together, thereby in final products, grid line 22 tops do not have gate insulation layer 31, the graphs coincide of gate insulation layer 31 and semiconductor layer 41, and be all only positioned at grid 21 tops; The advantage of this technique is, can select certain corrosive agent directly once semiconductor material layer 4 and insulation material layer 3 to be removed, thereby simplifies technique.
But, should be appreciated that if in this step, only remove the semiconductor material layer 4 of grid line position Q2, and retain insulation material layer 3, be also feasible; Like this, in final products, still have gate insulation layer 31 (but semiconductor layer 41 is only positioned at grid 21 tops) above grid line 22, this gate insulation layer 31 can increase grid line 22 and data wire spacing, thereby reduces the coupling capacitance of the two.
Wherein, the present embodiment is what to have the situation of grid metal level 2 be example, and its grid line 22 consists of jointly grid metal level 2 and transparent conductive material layer 1, thereby improves the electric conductivity of grid line 22; But should be appreciated that now grid line position Q2 only remains transparent conductive material layer 1 if do not form grid metal level 2 in step S101, grid line 22 also can directly consist of transparent conductive material.
S108, as shown in Figure 14, Figure 15, remove whole remaining photoresist layers 8, form the figure of grid 21, gate insulation layer 31, semiconductor layer 41.
That is to say, peel off whole remaining photoresist layers 8 (being the photoresist layer 8 of gate location Q1), semiconductor layer 41 is exposed, form the figure of grid 21, gate insulation layer 31, semiconductor layer 41.
Visible, in the present embodiment, only by single exposure, just prepared the figure of grid line 22/ grid 21, gate insulation layer 31, semiconductor layer 41, the first transparency electrode 11 simultaneously, therefore its exposure frequency obviously reduces, preparation method is simple.
Simultaneously, in the array base palte of the present embodiment, semiconductor layer 41 does not exceed grid 21 and grid line 22 tops, be that its first transparency electrode 11 and 12 of the second transparency electrodes do not have gate insulation layer 31, therefore the distance of 12 of the first transparency electrode 11 and the second transparency electrodes is short, and electric field strength and electric capacity are large, drive effective, gate insulation layer 31 can not exert an influence to seeing through of light yet simultaneously, so transmitance is high.
S109, formation passivation layer 5 (PVX), and in passivation layer 5, form source electrode via hole and the drain via being connected with semiconductor layer 41.
Wherein, passivation layer 5 can consist of materials such as silicon nitride, silica, and its Main Function is protection semiconductor layer 41, and makes other structural insulations of the first transparency electrode 11 and top.
S110, form source electrode 71, drain 72 by composition technique on passivation layer 5, this source electrode 71, draining 72 is electrically connected to semiconductor layer 41 respectively by source electrode via hole, drain via, thus formation thin-film transistor structure.
S111, preferred, forms planarization layer 6, and in planarization layer 6, forms and drain electrode 72 the first via holes that are connected.
Wherein, planarization layer 6 is made by materials such as resins conventionally, and the section poor " filling and leading up " that it is mainly used in the structures such as thin-film transistor to cause makes to be tending towards smooth on the surface integral of array base palte, so that follow-up alignment films even film layer forms, and be beneficial to the even friction of friction orientation technique.
S112, by composition technique, on planarization layer 6, form the second transparency electrode 12, the second transparency electrodes 12 and be connected with drain electrode 72 by the first via hole in planarization layer 6; Wherein, this second transparency electrode 12 is gap electrode, be positioned at the first transparency electrode 11 tops, thereby array base palte prepared by the method for the present embodiment is the array base palte of ADS pattern.
In the present embodiment, the second transparency electrode 12 connects drain electrode 72, and the second transparency electrode 12 is pixel electrodes, and the first transparency electrode 11 is public electrode.
Wherein, when forming the second transparency electrode 12, also can form data wire Data (being connected with source electrode 71 by via hole), public electrode wire (not shown, to be connected with the first transparency electrode 11 by via hole) simultaneously, thereby obtain the structure as shown in Figure 16,17.
Certainly, data wire Data, public electrode wire etc. also can form in other steps, for example can in the step that forms source electrode 71 and drain electrode 72, form data wire Data, public electrode wire simultaneously, now data wire Data is directly connected with source electrode 71, and public electrode wire is still connected with the first transparency electrode 11; Or, also can use independent step to form at the same time or separately data wire Data, public electrode wire etc.; At this, it is no longer limited.
Of course it is to be understood that above planarization layer 6 not necessarily, if while there is no planarization layer 6, source electrode 71,72, second transparency electrode 12 that drains all can be formed on passivation layer 5, and the second transparency electrode 12 directly connects drain electrode 72.
S113, continuation form other known structure (not shown)s such as alignment film, complete the preparation of array base palte.
Embodiment 3:
As shown in figure 18, the present embodiment provides a kind of preparation method of array base palte, and its front 8 steps (S201-S208) are identical with front 8 steps (S101-S108) of embodiment 2, and difference is, the present embodiment since the 9th step for:
S209, formation passivation layer 5 (PVX), and in passivation layer 5, form source electrode via hole and the drain via being connected with semiconductor layer 41, and the second via hole being connected with the first transparency electrode 11.
S210, form source electrode 71, drain 72 by composition technique on passivation layer 5, this source electrode 71, draining 72 is electrically connected to semiconductor layer 41 respectively by source electrode via hole, drain via, thus formation thin-film transistor structure.
Meanwhile, drain and 72 be also connected with the first transparency electrode 11 by the second via hole.
That is to say, in the present embodiment, the first transparency electrode 11 connects drain electrode 72, and the first transparency electrode 11 is pixel electrodes, and the second transparency electrode 12 is public electrode.
S211, preferred, forms planarization layer 6 (ES Layer).
S212, by composition technique, form the second transparency electrode 12 on planarization layer, this second transparency electrode 12 is gap electrode, is positioned at the first transparency electrode 11 tops.
Wherein, when forming the second transparency electrode 12, also can form data wire Data (being connected with source electrode 71 by via hole), public electrode wire (not shown, to be electrically connected to the second transparency electrode 12).
Now, because public electrode wire need to be electrically connected to the second transparency electrode 12, so it preferably forms with the second transparency electrode 12 simultaneously; Data wire Data still can form in the step of manufacturing source electrode 71 and drain electrode 72 simultaneously.
Of course it is to be understood that above planarization layer 6 not necessarily, if while there is no planarization layer 6, source electrode 71,72, second transparency electrode 12 that drains all can be formed on (now the second transparency electrode 12 is not connected with drain electrode 72) on passivation layer 5.
S213, continuation form other known structure (not shown)s such as alignment film, complete the preparation of array base palte.
Visible, in array base palte preparation method of the present invention, can be the first transparency electrode 11 as pixel electrode, the second transparency electrode 12 is as public electrode, can be also the first transparency electrode 11 as public electrode, the second transparency electrode 12 is as pixel electrode; Difference with upper type is only which electrode is connected with drain electrode 72, which electrode is connected with public electrode wire, and the change of this connected mode can realize by preparation order of each lead-in wire of adjustment, the conventional meanses such as hole site of crossing in each layer, at this, be not described in detail.
Should be appreciated that planarization layer 6 nonessential structure in above two embodiment, if do not form planarization layer 6, data wire Data, the second transparency electrode 12 etc. can be formed directly on passivation layer 5.
Be to be understood that, in above two embodiment, source electrode 71, drain 72, position, the preparation order of data wire Data, the second transparency electrode 12, public electrode wire etc. all can carry out multiple variation, for example source electrode 71, draining 72 can be formed on passivation layer 5, also can be formed on planarization layer 6 (now also need in planarization layer 6, form via hole so that source electrode 71, draining 72 is electrically connected to semiconductor layer 41); Data wire Data, public electrode wire can be formed on passivation layer 5, also can be formed on planarization layer 6.In a word; no matter how the position of these structures, connected mode change; but as long as the preparation process of array base palte comprises the step that forms grid 21, grid line 22, gate insulation layer 31, semiconductor layer 41, the first transparency electrode 11 by composition technique simultaneously; and its gate insulation layer 31 does not exceed grid 21 and grid line 22 tops, belongs to protection scope of the present invention.
Embodiment 4:
As shown in Fig. 2 to Figure 18, the present embodiment provides a kind of array base palte, and it comprises grid 21, grid line 22, gate insulation layer 31, semiconductor layer 41, the first transparency electrode 11 (can be plate electrode), the second transparency electrode 12, source electrode 71, drain 72, passivation layer 5.
As shown in Figure 16, Figure 17, in the array base palte of the present embodiment, grid 21, grid line 22 comprise transparent conductive material layer 1.
That is to say, the grid 21 of the array base palte of the present embodiment, grid line 22 can consist of the material of the first transparency electrode 11, therefore they can synchronize with the first transparency electrode 11 formation, thereby simplify preparation technology.
Preferably, grid 21, grid line 22 also comprise the grid metal level 2 being positioned on transparent conductive material layer 1, and grid 21, grid line 22 can jointly be comprised of transparent conductive material layer 1 and grid metal level 2, thereby strengthen its electric conductivity.
Certainly, can there is no grid metal level 2 in theory yet, and directly with transparent conductive material layer 1, form grid 21, grid line 22.
Wherein, gate insulation layer 31 does not exceed grid 21 and grid line 22 tops; Thereby the first transparency electrode 11,12 of the second transparency electrodes do not have gate insulation layer 31, therefore two interelectrode distances are short, and electric field strength is high, and electric capacity is large, drives effective; And gate insulation layer 31 can not exert an influence to seeing through of light yet, therefore transmitance is high.
Preferably, gate insulation layer 31 is identical with semiconductor layer 41 figures, and is only positioned at grid 21 tops.
Because gate insulation layer 31 is identical with semiconductor layer 41 figures, therefore they can form in an etching simultaneously, preparation efficiency is high.
Certainly, gate insulation layer 31 also can be different from semiconductor layer 41 figures, and above grid line 22, also have distribution (41 of semiconductor layers are positioned at grid 21 tops), can increase the distance between grid line 22 and data wire like this, reduce the coupling capacitance of the two.
Preferably, semiconductor layer 41 is made by metal oxide semiconductor material.
And source electrode 71, draining 72 is positioned at passivation layer 5 tops, and by source electrode via hole and drain via in passivation layer 5, be electrically connected to semiconductor layer 41 respectively.
The second transparency electrode 12 is positioned at passivation layer 5 tops, and it can be gap electrode, and is positioned at the first transparency electrode 11 tops.
As shown in figure 17, in the present embodiment, preferably the second transparency electrode 12 is electrically connected to drain electrode 72, and wherein the first transparency electrode 11 is public electrode (it also will be electrically connected to public electrode wire), and the second transparency electrode 12 is pixel electrode.
Now, the second transparency electrode 12 preferably can be with source electrode 71, draining is all located on passivation layer 5 together with 72, and directly connects (also can with drain 72 synchronize formation) with drain electrode 72.
Preferably, on passivation layer 5, be also coated with planarization layer 6.
When having planarization layer 6, the second transparency electrode 12 is preferably located on planarization layer 6, and source electrode 71, drains and 72 still can be located on passivation layer 5, and the second transparency electrode 12 72 is electrically connected to draining by the first via hole in planarization layer 6.
Preferably, as a kind of mode of the present embodiment, as shown in figure 18, also can be that the first transparency electrode 11 is electrically connected to drain electrode 72 by the second via hole in passivation layer 5, the first transparency electrode 11 is pixel electrode, and the second transparency electrode 12 is public electrode (it also will be electrically connected to public electrode wire).
Now, preferably source electrode 71,72, second transparency electrode 12 that drains are all positioned on passivation layer 5, but the second transparency electrode 12 is not connected with drain electrode 72.
Certainly, preferred, in the array base palte of the present embodiment, also can comprise the planarization layer 6 that covers passivation layer 5, when thering is planarization layer 6, source electrode 71, draining 72 is preferably formed on passivation layer 5, and the second transparency electrode 12 is preferably located on planarization layer 6.
Certainly, in the array base palte of the present embodiment, also should comprise other known structure such as public electrode wire, data wire Data, alignment film, at this, be not described in detail.
Embodiment 5:
The present embodiment provides a kind of liquid crystal indicator, and it comprises above-mentioned array base palte.Described liquid crystal indicator can be: any product or parts with Presentation Function such as display panels, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
The liquid crystal indicator of the present embodiment comprises above-mentioned array base palte, therefore its preparation technology is simple, driveability good, transmitance is high.
Be understandable that, above execution mode is only used to principle of the present invention is described and the illustrative embodiments that adopts, yet the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (21)
1. an array base palte preparation method, is characterized in that, comprising:
Step 1: the composition technique by the exposure of use ladder in substrate forms the figure that comprises grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode; Wherein, described gate insulation layer does not exceed grid and grid line top;
Step 2: form passivation layer in the substrate that completes abovementioned steps, and form source electrode via hole and the drain via being connected with semiconductor layer in passivation layer;
Step 3: form by composition technique the figure that comprises source electrode, drain electrode in the substrate that completes abovementioned steps, and form by composition technique the figure that comprises the second transparency electrode; Wherein, described source electrode, drain electrode are electrically connected to semiconductor layer by source electrode via hole, drain via respectively.
2. array base palte preparation method according to claim 1, is characterized in that, described step 1 specifically comprises:
Step 11, in substrate, form successively transparent conductive material layer, insulation material layer, semiconductor material layer, photoresist layer;
Step 12, photoresist layer ladder is exposed and developed, make gate location retain the photoresist layer of the first thickness, grid line position retains the photoresist layer of the second thickness, the first transparency electrode position retains the photoresist layer of the 3rd thickness, all the other positions are without photoresist layer, wherein the first thickness is greater than the second thickness, and the second thickness is greater than the 3rd thickness;
Step 13, remove semiconductor material layer, insulation material layer, transparent conductive material layer without photoresist region;
Step 14, remove the photoresist layer of the 3rd thickness, the semiconductor material layer of the first transparency electrode position is exposed;
Step 15, the semiconductor material layer of removing the first transparency electrode position, insulation material layer, form the figure of the first transparency electrode;
Step 16, remove the photoresist layer that thickness equals grid line position remaining photoresist layer thickness, the semiconductor layer of grid line position is exposed;
Step 17, remove the semiconductor material layer of grid line position, form the figure of grid line;
Step 18, remove remaining photoresist layer, form the figure of grid, gate insulation layer, semiconductor layer.
3. array base palte preparation method according to claim 2, is characterized in that, described step 17 specifically comprises:
Remove the semiconductor material layer of grid line position, and remove the insulation material layer of grid line position, form the figure of grid line.
4. array base palte preparation method according to claim 2, is characterized in that,
Described step 11 also comprises: at transparent conductive material layer and insulating material interlayer, form grid metal level;
Described step 13 also comprises: remove the grid metal level without photoresist region;
Described step 15 also comprises: the grid metal level of removing the first transparency electrode position.
5. array base palte preparation method according to claim 1, is characterized in that,
Described ladder exposure realizes by gray scale mask plate or intermediate tone mask plate.
6. array base palte preparation method according to claim 1, is characterized in that,
Described semiconductor layer is made by metal oxide semiconductor material.
7. according to the array base palte preparation method described in any one in claim 1 to 6, it is characterized in that,
Described the first transparency electrode is public electrode, and described the second transparency electrode is pixel electrode, is electrically connected to drain electrode.
8. array base palte preparation method according to claim 7, is characterized in that,
Described source electrode, drain electrode, the second transparency electrode are all formed on passivation layer.
9. array base palte preparation method according to claim 7, is characterized in that,
Described source electrode, drain electrode are formed on passivation layer;
Forming between source electrode, drain electrode and formation the second transparency electrode, also comprising: forming planarization layer, and form the first via hole being connected with drain electrode in planarization layer;
Described the second transparency electrode is formed on planarization layer, and is electrically connected to drain electrode by the first via hole.
10. according to the array base palte preparation method described in any one in claim 1 to 6, it is characterized in that,
Described the first transparency electrode is electrically connected to drain electrode, is pixel electrode, and described the second transparency electrode is public electrode;
Described step 2 also comprises: in passivation layer, form the second via hole being connected with the first transparency electrode, described drain electrode is electrically connected to the first transparency electrode by the second via hole.
11. array base palte preparation methods according to claim 10, is characterized in that,
Described source electrode, drain electrode are formed on passivation layer;
Forming between source electrode, drain electrode and formation the second transparency electrode, also comprising: forming planarization layer;
Described the second transparency electrode is formed on planarization layer.
12. 1 kinds of array base paltes, it comprises grid, grid line, gate insulation layer, semiconductor layer, the first transparency electrode, the second transparency electrode, source electrode, drain electrode, passivation layer; Wherein
Described passivation layer covers grid line, grid, gate insulation layer, semiconductor layer, the first transparency electrode;
Described the second transparency electrode is positioned at passivation layer top;
Described source electrode, drain electrode are arranged in passivation layer top and also by source electrode via hole, the drain via of passivation layer, are electrically connected to semiconductor layer respectively;
It is characterized in that,
Described grid, grid line comprise transparent conductive material layer;
Described gate insulation layer does not exceed grid and grid line top.
13. array base paltes according to claim 12, is characterized in that,
Described gate insulation layer is identical with semiconductor layer figure, and is only positioned at grid top.
14. array base paltes according to claim 12, is characterized in that,
Described grid, grid line also comprise the grid metal level being positioned on transparent conductive material layer.
15. array base paltes according to claim 12, is characterized in that,
Described semiconductor layer is made by metal-oxide semiconductor (MOS).
16. according to claim 12 to the array base palte described in any one in 15, it is characterized in that,
Described the second transparency electrode is pixel electrode, is electrically connected to drain electrode, and described the first transparency electrode is public electrode.
17. array base paltes according to claim 16, is characterized in that,
Described source electrode, drain electrode, the second transparency electrode are located on passivation layer.
18. array base paltes according to claim 12, is characterized in that, also comprise:
Be located at the planarization layer on passivation layer, described source electrode, drain electrode are located on passivation layer, and described the second transparency electrode is located on planarization layer, and are electrically connected to drain electrode by the first via hole in planarization layer.
19. according to claim 12 to the array base palte described in any one in 15, it is characterized in that,
Described the first transparency electrode is electrically connected to drain electrode by the second via hole in passivation layer, and described the first transparency electrode is pixel electrode, and described the second transparency electrode is public electrode.
20. array base paltes according to claim 19, is characterized in that, also comprise:
Be located at the planarization layer on passivation layer, described the second transparency electrode is located on planarization layer, and described source electrode, drain electrode are located on passivation layer.
21. 1 kinds of liquid crystal indicators, is characterized in that, comprising:
Array base palte as described in any one in claim 12 to 20.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104133313A (en) * | 2014-06-18 | 2014-11-05 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal display device |
| CN104851894A (en) * | 2015-06-03 | 2015-08-19 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, and display device |
| WO2015196633A1 (en) * | 2014-06-24 | 2015-12-30 | 京东方科技集团股份有限公司 | Array substrate manufacturing method, array substrate and display device |
| CN105870136A (en) * | 2016-06-27 | 2016-08-17 | 京东方科技集团股份有限公司 | Array substrate, making method thereof and display device |
| CN106959536A (en) * | 2017-03-31 | 2017-07-18 | 上海中航光电子有限公司 | Display panel, the method and display device for making display panel |
| CN107167974A (en) * | 2017-07-07 | 2017-09-15 | 惠科股份有限公司 | Array substrate, manufacturing method thereof and display panel applied to array substrate |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070252142A1 (en) * | 2006-04-26 | 2007-11-01 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
| US20080266498A1 (en) * | 2007-04-27 | 2008-10-30 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and method for manufacturing the same |
| CN102655117A (en) * | 2011-11-09 | 2012-09-05 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method, and display device |
| CN102655154A (en) * | 2012-02-27 | 2012-09-05 | 京东方科技集团股份有限公司 | OTFT (Organic Thin Film Transistor) array substrate, display device and manufacturing method thereof |
| CN103236419A (en) * | 2013-04-26 | 2013-08-07 | 京东方科技集团股份有限公司 | Preparation method of array substrate, array substrate and display device |
| CN203465496U (en) * | 2013-09-27 | 2014-03-05 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal display device |
-
2013
- 2013-09-27 CN CN201310452105.6A patent/CN103545252B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070252142A1 (en) * | 2006-04-26 | 2007-11-01 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
| US20080266498A1 (en) * | 2007-04-27 | 2008-10-30 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and method for manufacturing the same |
| CN102655117A (en) * | 2011-11-09 | 2012-09-05 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method, and display device |
| CN102655154A (en) * | 2012-02-27 | 2012-09-05 | 京东方科技集团股份有限公司 | OTFT (Organic Thin Film Transistor) array substrate, display device and manufacturing method thereof |
| CN103236419A (en) * | 2013-04-26 | 2013-08-07 | 京东方科技集团股份有限公司 | Preparation method of array substrate, array substrate and display device |
| CN203465496U (en) * | 2013-09-27 | 2014-03-05 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal display device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104133313A (en) * | 2014-06-18 | 2014-11-05 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal display device |
| WO2015196633A1 (en) * | 2014-06-24 | 2015-12-30 | 京东方科技集团股份有限公司 | Array substrate manufacturing method, array substrate and display device |
| CN104851894A (en) * | 2015-06-03 | 2015-08-19 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, and display device |
| CN104851894B (en) * | 2015-06-03 | 2017-12-22 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| US10510784B2 (en) | 2015-06-03 | 2019-12-17 | Boe Technology Group Co., Ltd. | Array substrate and method of manufacturing the same, and display apparatus |
| CN105870136A (en) * | 2016-06-27 | 2016-08-17 | 京东方科技集团股份有限公司 | Array substrate, making method thereof and display device |
| CN106959536A (en) * | 2017-03-31 | 2017-07-18 | 上海中航光电子有限公司 | Display panel, the method and display device for making display panel |
| CN107167974A (en) * | 2017-07-07 | 2017-09-15 | 惠科股份有限公司 | Array substrate, manufacturing method thereof and display panel applied to array substrate |
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|---|---|
| CN103545252B (en) | 2015-12-09 |
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