CN103346090B - Method for manufacturing transversely-diffusing metal oxide semiconductor device - Google Patents
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Abstract
The invention provides a method for manufacturing a transversely-diffusing metal oxide semiconductor device. The method includes the steps of providing a base, wherein a source electrode active region is arranged in the substrate and provided with a first part, a second part and a third part, preparing an isolation structure, forming a first trap, a second trap and a third trap in the substrate, wherein the third trap is at least located at the edge position of the second part of the source electrode active region in the second direction, forming a drain region in the second trap, forming a source region in the first part of the source electrode active region, and forming a contact region in the first trap, and forming grid structures on part of the first trap and part of the second trap. The method for manufacturing the transversely-diffusing metal oxide semiconductor device can effectively avoid the double peak effect, and therefore the performance of the transversely-diffusing metal oxide semiconductor device is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of transverse diffusion metal oxide semiconductor device
Manufacture method.
Background technology
LDMOS (lateral diffusion metal oxide semiconductor,
Abbreviation LDMOS) transistor operation when there is high-breakdown-voltage (breakdown voltage) and low opening resistor (on-
State resistance), therefore, either on typical power IC, or in intelligent electric power integrated circuit
On, LDMOS transistor all plays particularly important role.
As depicted in figs. 1 and 2, Fig. 1 is horizontal proliferation of the prior art to the structural representation of LDMOS of the prior art
The top view of metal oxide semiconductor device, Fig. 2 is the profile of AA' along the line in Fig. 1.LDMOS includes substrate 100, first
First trap 102 of conduction type, the second trap 103 of the second conduction type, the drain region 105 of the second conduction type, the second conductive-type
The source region 106 of type, the contact area 107 of the first conduction type and grid structure 108, active area is carried out by isolation structure 110
Isolation.The drain region 105 is located in second trap 103, as the leakage of the transverse diffusion metal oxide semiconductor device
Pole, the source region 106 is located in first trap 102, as the source electrode of the transverse diffusion metal oxide semiconductor device,
The contact area 107 is located in first trap 102, for connecting the ditch of the transverse diffusion metal oxide semiconductor device
Road.First trap 102 described in the covering part of the grid structure 108 and part second trap 103, general, the grid knot
Structure 108 is made up of gate dielectric 181 and grid 182.
It is as shown in figure 3, in figure 3, horizontal but in actual application, LDMOS of the prior art has double-hump effect
Coordinate represents grid voltage Vg, and vertical coordinate represents electric current Id, occurs two peak values (dashed region in figure in whole Id-Vg curves
Shown in domain), referred to as double-hump effect.Its performance is that MOS (partly lead by metal-oxide at subcritical area (sub-threshold)
Body) (Vg when being not yet turned on<), Vt transistor occurs in that significantly electric leakage (I-leakage).The appearance in advance of this electric leakage,
The failure of transistor and the low yields of product can be directly resulted in.
The content of the invention
It is an object of the invention to provide a kind of manufacture method of transverse diffusion metal oxide semiconductor device, Neng Gouyou
Effect double-hump effect is avoided, so as to improve the performance of transverse diffusion metal oxide semiconductor device.
To solve above-mentioned technical problem, the present invention provides a kind of manufacturer of transverse diffusion metal oxide semiconductor device
Method, including：
Substrate is provided, there is source electrode active area in the substrate, the source electrode active area has Part I, Part II
And Part III, the Part I, Part II and Part III are arranged in order in a first direction；
Isolation structure is prepared, the isolation structure is used to isolate active area；
The first trap, the second trap and the 3rd trap, the Part I of the source electrode active area and are formed in the substrate
Two parts are located in first trap, and the 3rd of the source electrode active area is located in second trap, and the 3rd trap is at least
Positioned at the Part II marginal position in a second direction of the source electrode active area；
Drain region is formed in second trap, in the Part I of the source electrode active area source region is formed, described
Contact area is formed in one trap；
Grid structure is formed on part first trap and part second trap, the grid structure covers the source
The Part II and Part III of pole active area；
Wherein, the substrate, the first trap, the 3rd trap and contact area are the first conduction type and mix, second trap, leakage
Area and source region are the second conduction type and mix.
Further, in the step of the first trap, the second trap and three traps are formed in the substrate, it is initially formed described
Three traps, re-form first trap.
Further, the doping content of the 3rd trap is 1015cm-3-1017cm-3。
Further, depth of the depth of the 3rd trap more than first trap.
Further, the edge of the 3rd trap from the edge of the Part II of the source electrode active area in a second direction
Distance be 50nm～1 μm.
Further, the edge of the 3rd trap from the edge of second trap in a first direction with a distance from for 50nm～
1μm。
Further, first conduction type is p-type, and second conduction type is N-type；Or first conductive-type
Type is N-type, and second conduction type is p-type.
Further, the isolation structure is shallow groove isolation structure.
Compared with prior art, the manufacture method of the transverse diffusion metal oxide semiconductor device that the present invention is provided has
Advantages below：
The transverse diffusion metal oxide semiconductor device that the present invention is provided, forms the 3rd trap in the substrate, described
3rd trap is located at least in the Part II of source electrode active area marginal position in a second direction, compared with prior art,
Due to the injection of the 3rd trap so that the ion of the Part II of source electrode active area marginal position in a second direction
Other positions of the doping content higher than the source electrode active area.When in follow-up preparation technology, when the source electrode active area
When the ion concentration of Part II marginal position in a second direction is lost, the injection of the 3rd trap can be to ion
The loss of concentration provides compensation so that the Part II of source electrode active area marginal position in a second direction from
Sub- concentration is not less than other positions, so as to avoid double-hump effect, improves the performance of transverse diffusion metal oxide semiconductor device.
Description of the drawings
Fig. 1 is the top view of transverse diffusion metal oxide semiconductor device of the prior art；
Fig. 2 is the profile of AA' along the line in Fig. 1；
Fig. 3 is the Id-Vg graph of relation of transverse diffusion metal oxide semiconductor device of the prior art；
Fig. 4 is the profile of BB' along the line in Fig. 1；
Fig. 5 is the flow chart of the manufacture method of the transverse diffusion metal oxide semiconductor device of one embodiment of the invention；
Fig. 6 a- Fig. 6 g are each in the manufacture method of the transverse diffusion metal oxide semiconductor device of one embodiment of the invention
The schematic diagram of device in step；
Fig. 7 is the Id-Vg graph of relation of the transverse diffusion metal oxide semiconductor device of one embodiment of the invention；
Fig. 8 is the top view of the transverse diffusion metal oxide semiconductor device of another embodiment of the present invention.
Specific embodiment
In the transverse diffusion metal oxide semiconductor device of prior art, the LDMOS
There is in use double-hump effect in device so that the transverse diffusion metal oxide semiconductor device failure and low yields.
Inventor is preparing the isolation through the further investigation discovery to prior art transverse diffusion metal oxide semiconductor device
During structure 110, groove 120 occurs at the edge of the isolation structure 110, as shown in figure 4, depositing due to the groove 120
So that in follow-up preparation technology, the ion concentration encircled of first trap 102 in Fig. 4 in encircled
The ion concentration of outer first trap 102 is low, so as to cause double-hump effect.Inventor further study show that, can be in institute
State in substrate the 3rd trap of formation, the 3rd trap is located at least in the Part II of the source electrode active area (BB ' in a second direction
The direction that line is located) marginal position, due to the injection of the 3rd trap so that the Part II of the source electrode active area is the
Other positions of the ion doping concentration of the marginal position on two directions higher than the source electrode active area.When in follow-up preparation work
In skill, when the ion concentration in encircled in Fig. 4 is lost, the injection of the 3rd trap can be to the damage of ion concentration
Lose and compensation is provided, so that the ion concentration in Fig. 4 in encircled is not less than other positions, so as to avoid double-hump effect,
Improve the performance of transverse diffusion metal oxide semiconductor device.
The manufacture method of the transverse diffusion metal oxide semiconductor device of the present invention is carried out below in conjunction with schematic diagram
More detailed description, which show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change here
The present invention of description, and still realize the advantageous effects of the present invention.Therefore, description below is appreciated that for this area skill
Art personnel's is widely known, and is not intended as limitation of the present invention.
Referring to the drawings the present invention more particularly described below by way of example in the following passage.Will according to following explanation and right
Book, advantages and features of the invention is asked to become apparent from.It should be noted that, accompanying drawing is in the form of simplifying very much and using non-
Accurately ratio, only aids in illustrating the purpose of the embodiment of the present invention to convenience, lucidly.
The core concept of the present invention is to provide a kind of manufacture method of transverse diffusion metal oxide semiconductor device,
Form the 3rd trap in the substrate, the 3rd trap is located at least in the Part II of the source electrode active area in a second direction
Marginal position, due to the injection of the 3rd trap so that the Part II of source electrode active area edge in a second direction
The ion doping concentration of position is higher than the other positions of the source electrode active area, when in follow-up preparation technology, when the source
When the ion concentration of the Part II of pole active area marginal position in a second direction is lost, the injection of the 3rd trap
Compensation can be provided to the loss of ion concentration, so that the Part II of source electrode active area side in a second direction
The ion concentration of edge position is not less than other positions.The manufacture method of the transverse diffusion metal oxide semiconductor device is concrete
Including：
Step S11, there is provided substrate, in the substrate have source electrode active area, the source electrode active area have Part I,
Part II and Part III, the Part I, Part II and Part III are arranged in order in a first direction；
Step S12, forms the first trap, the second trap and the 3rd trap in the substrate, and the first of the source electrode active area
Part and Part II are located in first trap, and the 3rd of the source electrode active area is located in second trap, and described the
Three traps are located at least in the Part II of source electrode active area marginal position in a second direction；
Step S13, prepares isolation structure, and the isolation structure is used to isolate active area；
Step S14, in second trap drain region is formed, and in the Part I of the source electrode active area source region is formed,
Contact area is formed in first trap；
Step S15, on part first trap and part second trap grid structure is formed, and the grid structure covers
Cover the Part II and Part III of the source electrode active area.
The transverse diffusion metal oxide semiconductor device of the present embodiment is illustrated below in conjunction with Fig. 5 and Fig. 6 a- Fig. 6 g
Manufacture method, wherein, Fig. 5 for the transverse diffusion metal oxide semiconductor device of one embodiment of the invention manufacture method
Flow chart, Fig. 6 a- Fig. 6 g are each in the manufacture method of the transverse diffusion metal oxide semiconductor device of one embodiment of the invention
The schematic diagram of device in step.
As shown in figure 5, first, carry out step S11, there is provided substrate 200, there is source electrode active area in the substrate 200
201, the source electrode active area 201 has Part I 210, Part II 212 and Part III 213, the Part I
210th, Part II 212 and Part III 213 are arranged in order on X in a first direction, as described in Fig. 6 a.
Then, step S12 is carried out, prepares isolation structure 210, the isolation structure 210 is used to isolate active area, wherein,
Active area for this area conventional meaning active area, including contact area, source electrode active area 201 and drain region, as shown in Figure 6 b.
In the present embodiment, the isolation structure 210 is shallow groove isolation structure.
Then, step S13 is carried out, the first trap 202, the second trap 203 and the 3rd trap 204 is formed in the substrate 200,
The Part I 210 and Part II 212 of the source electrode active area 201 is located in first trap 202, the source electrode active area
The 3rd 213 of 201 is located in second trap 203, and the 3rd trap 204 is located at least in the of the source electrode active area 201
Marginal position of two parts 212 in second direction Y, as fig. 6 c.
Fig. 6 d are the profile of CC' along the line in Fig. 6 c, due to the injection of the 3rd trap 204, the note of the 3rd trap 204
The ion for entering can be diffused in the Part II 212 of the source electrode active area 201 so that the second of the source electrode active area 201
The ion doping concentration of the marginal position (i.e. encircled in Fig. 6 d) in a second direction of part 212 has higher than the source electrode
The other positions of source region 201, when in follow-up preparation technology, when the ion concentration of the encircled in Fig. 6 d is lost
When, the injection of the 3rd trap 204 can provide compensation to the loss of ion concentration, so that the encircled in Fig. 6 d
Ion concentration is not less than other positions.
In this step, the formation order of first trap 202, the second trap 203 and the 3rd trap 204 does not do concrete limit
System, can be with, is initially formed first trap 202, re-forms the second trap 203, eventually forms the 3rd trap 204.In the present embodiment, first
The 3rd trap 204 is formed, first trap 202 is re-formed, the second trap 203 is eventually formed, is conducive to being walked with the technique on line
It is rapid to integrate.
Wherein, the doping content of the 3rd trap 204 is preferably 1015cm-3-1017cm-3, can effectively compensate loss
Ion, but the doping content of the 3rd trap 204 is not limited to as 1015cm-3-1017cm-3If, the 3rd trap 204
Doping content can compensate the ion of loss, also within the thought range of the present invention.In the present embodiment, the 3rd trap 204
Depth more than the depth of first trap 202, be conducive to the ion of effectively compensation loss, but the depth of the 3rd trap 204
Degree is also less than the depth of first trap 202.
Wherein, the edge of the 3rd trap 204 can coincide with the edge of Part II 212, it is also possible to described
The edge of two traps 203 coincides, but the film in order to avoid between rings, preferably, the edge of the 3rd trap 204 is from the source
The edge of the Part II 212 of pole active area 201 in second direction Y apart from a be 50nm～1 μm, the 3rd trap 204
Edge distance b on the edge of second trap 203 in a first direction X is 50nm～1 μm, but, apart from a and apart from b not
It is limited to above-mentioned data, as long as the encircled that the ion of the 3rd trap 204 is diffused in Fig. 6 d can be caused, also the present invention's
Within thought range.
Subsequently, step S14 is carried out, drain region 205 is formed in second trap 203, the of the source electrode active area 201
Source region 206 is formed in a part 210, contact area 207 is formed in first trap 202, as shown in fig 6e.
Finally, as shown in Figure 6 f, step S15 is carried out, on part first trap 202 and part second trap 203
Grid structure 208 is formed, the grid structure 208 covers the Part II 212 and Part III of the source electrode active area 201
213。
Fig. 6 g are the profile of DD' along the line in Fig. 6 f, when the isolation structure 210 is prepared, in the isolation structure 210
Edge groove 220 occurs, due to the presence of the groove 220 so that in follow-up preparation technology, Fig. 6 g encircleds
The ion concentration of interior first trap 202 has loss, but due to the injection of the 3rd trap 204, the 3rd trap 204
Injection can provide compensation to the loss of ion concentration, so that the ion concentration in Fig. 6 g encircleds is not less than other positions
Put, so as to avoid double-hump effect, improve the performance of transverse diffusion metal oxide semiconductor device.Fig. 7 is implemented for the present invention one
The Id-Vg graph of relation of the transverse diffusion metal oxide semiconductor device of example, in the figure 7, abscissa represents grid voltage
Vg, vertical coordinate represents electric current Id, and in the figure 7, whole Id-Vg curves do not occur bimodal, illustrate the horizontal stroke of one embodiment of the invention
Can have that what is arrived very much to avoid double-hump effect to diffused metal oxide emiconductor device.
In the present embodiment, the substrate 200, the first trap 202, the 3rd trap 204 and contact area 207 are the first conductive-type
Type mixes, and second trap 203, drain region 205 and source region 206 are the second conduction type and mix.Further, described first lead
Electric type is p-type, and second conduction type is N-type；Or first conduction type is N-type, second conduction type is P
Type.
The present invention is not limited to above example, wherein, the size and shape of the 3rd trap 204 does not do concrete limit
System, as shown in figure 8, Fig. 8 is the top view of the transverse diffusion metal oxide semiconductor device of another embodiment of the present invention, in figure
It is equivalent in meaning in identical label and Fig. 6 g, when the 3rd trap 204 be shaped as shown in Fig. 8 structure when, the described 3rd
The injection of trap 204 can also provide compensation to the loss of ion concentration, also within the thought range of the present invention.In addition, may be used also
First to prepare second trap, the 3rd trap, subsequently, isolation structure is prepared, then prepare the first trap；Or, isolation structure is first prepared, with
Afterwards, second trap, the 3rd trap are prepared, then prepares the first trap, also within the thought range of the present invention.
In sum, the present invention provides a kind of preparation method of transverse diffusion metal oxide semiconductor device, described
The 3rd trap is formed in substrate, the 3rd trap is located at least in the Part II of source electrode active area edge in a second direction
Position.Compared with prior art, the transverse diffusion metal oxide semiconductor device that the present invention is provided has advantages below：
The transverse diffusion metal oxide semiconductor device that the present invention is provided, forms the 3rd trap in the substrate, described
3rd trap is located at least in the Part II of source electrode active area marginal position in a second direction, compared with prior art,
Due to the injection of the 3rd trap so that the ion of the Part II of source electrode active area marginal position in a second direction
Other positions of the doping content higher than the source electrode active area.When in follow-up preparation technology, when the source electrode active area
When the ion concentration of Part II marginal position in a second direction is lost, the injection of the 3rd trap can be to ion
The loss of concentration provides compensation so that the Part II of source electrode active area marginal position in a second direction from
Sub- concentration is not less than other positions, so as to avoid double-hump effect, improves the performance of transverse diffusion metal oxide semiconductor device.
Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (8)
1. a kind of manufacture method of transverse diffusion metal oxide semiconductor device, it is characterised in that include：
There is provided substrate, in the substrate have source electrode active area, the source electrode active area have Part I, Part II and
Part III, the Part I, Part II and Part III are arranged in order in a first direction；
Isolation structure is prepared, the isolation structure is used to isolate active area；
Form the first trap, the second trap and the 3rd trap, the Part I of the source electrode active area and in the substrate respectively
Two parts are located in first trap, and the Part III of the source electrode active area is located in second trap, and the 3rd trap is extremely
Less positioned at the Part II marginal position in a second direction of the source electrode active area；
Drain region is formed in second trap, in the Part I of the source electrode active area source region is formed, in first trap
Middle formation contact area；
Grid structure is formed on part first trap and part second trap, the grid structure covers the source electrode to be had
The Part II and Part III of source region, also, the grid structure exposes the 3rd trap and part is described first
Point；
Wherein, the substrate, the first trap, the 3rd trap and contact area be the first conduction type doping, second trap, drain region and
Source region is the doping of the second conduction type.
2. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 1, it is characterised in that in institute
In stating the step of formed in substrate the first trap, the second trap and three traps, the 3rd trap is initially formed, re-forms described first
Trap.
3. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 1, it is characterised in that described
The doping content of the 3rd trap is 1015cm-3-1017cm-3。
4. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 1, it is characterised in that described
Depth of the depth of the 3rd trap more than first trap.
5. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 1, it is characterised in that described
The edge of the 3rd trap from the edge of the Part II of the source electrode active area in a second direction with a distance from be 50nm～1 μm.
6. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 1, it is characterised in that described
The edge of the 3rd trap from the edge of second trap in a first direction with a distance from be 50nm～1 μm.
7. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 1, it is characterised in that institute
It is p-type to state the first conduction type, and second conduction type is N-type；Or first conduction type is N-type, described second leads
Electric type is p-type.
8. the manufacture method of transverse diffusion metal oxide semiconductor device as claimed in claim 1, it is characterised in that described
Isolation structure is shallow groove isolation structure.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930946A (en) * | 2009-06-19 | 2010-12-29 | 新加坡格罗方德半导体制造私人有限公司 | Integrated circuit (IC) system and manufacture method thereof with high voltage transistor |
| CN102097475A (en) * | 2009-11-27 | 2011-06-15 | 美格纳半导体有限公司 | Semiconductor device and method for fabricating semiconductor device |
| CN103151386A (en) * | 2013-03-27 | 2013-06-12 | 上海宏力半导体制造有限公司 | Laterally diffused metal oxide semiconductor device and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930946A (en) * | 2009-06-19 | 2010-12-29 | 新加坡格罗方德半导体制造私人有限公司 | Integrated circuit (IC) system and manufacture method thereof with high voltage transistor |
| CN102097475A (en) * | 2009-11-27 | 2011-06-15 | 美格纳半导体有限公司 | Semiconductor device and method for fabricating semiconductor device |
| CN103151386A (en) * | 2013-03-27 | 2013-06-12 | 上海宏力半导体制造有限公司 | Laterally diffused metal oxide semiconductor device and manufacturing method thereof |
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