CN103345938B - The wordline control method of flash memory and the method for deleting of flash memory - Google Patents
The wordline control method of flash memory and the method for deleting of flash memory Download PDFInfo
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- CN103345938B CN103345938B CN201310261449.9A CN201310261449A CN103345938B CN 103345938 B CN103345938 B CN 103345938B CN 201310261449 A CN201310261449 A CN 201310261449A CN 103345938 B CN103345938 B CN 103345938B
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Abstract
The wordline control method of a kind of flash memory and the method for deleting of flash memory, the wordline control method of described flash memory includes: between the first moment and the second moment, applies the first positive electricity and is depressed into wordline, and described second moment lags behind described first moment；Between described second moment and the 3rd moment, apply the second positive electricity and be depressed into described wordline, described 3rd moment lags behind described second moment, described second positive voltage is higher than described first positive voltage, and the time between described second moment and the 3rd moment accounts for 10% to 20% of the time between described first moment and the 3rd moment.The wordline control method of the flash memory that technical solution of the present invention provides and the method for deleting of flash memory, it is possible to slow down the catagen speed of tunnel oxide in flash memory, improve the durability of flash memory.
Description
Technical field
The present invention relates to memory technology field, particularly to wordline control method and the flash memory of a kind of flash memory
Method for deleting.
Background technology
Flash memory (Flash Memory) is as a kind of integrated circuit memory devices, owing to it has high speed, height
Density, the plurality of advantages such as data can be maintained to after micro, power-off, be widely used in as portable
In the electronic products such as formula computer, mobile phone, digital music player.Flash memory is as a kind of non-volatile memories
Device, its operation principles is to control the switch of gate pole passage by changing the critical voltage of memory element, with
Reach to store the purpose of data, make storage data in the memory unit will not disappear because of power interruptions.
Nowadays flash memory has already taken up most of market share of nonvolatile memory, becomes with fastest developing speed non-
Volatile memory.
Generally, when flash memory carries out erasing process, need flash memory is applied higher voltage.Wiping
Cheng Zhong, the tunnel oxide in flash memory bears bigger voltage stress.Bigger voltage stress causes tunnel
Wear the degeneration of oxide layer, and then reduce the durability of whole flash memory.Durability is to weigh reliability of flash memory
One important indicator, refers to that flash memory still will not lose efficacy after repeatedly erasing processes.Tunnelling oxygen in flash memory
The catagen speed changing layer is the fastest, and the durability of flash memory is the lowest.
Along with the application of flash memory is more and more extensive, slow down the catagen speed of tunnel oxide, raising in flash memory
The durability of flash memory is a problem demanding prompt solution.
Summary of the invention
What the present invention solved is the problem that the tunnel oxide catagen speed in flash memory is fast, flash memory durability is low.
For solving the problems referred to above, the present invention provides the wordline control method of a kind of flash memory, including: first
Between moment and the second moment, applying the first positive electricity and be depressed into wordline, described second moment lags behind described
One moment；Between described second moment and the 3rd moment, apply the second positive electricity and be depressed into described wordline, institute
Stating for the 3rd moment lags behind described second moment, and described second positive voltage is higher than described first positive voltage, institute
The time between the second moment and the 3rd moment of stating accounts for the time between described first moment and the 3rd moment
10% to 20%.
Wordline control method based on above-mentioned flash memory, the invention provides the method for deleting of a kind of flash memory, institute
State flash memory and include the first wordline, the second wordline, the first drain region, the second drain region and source region,
The method for deleting of described flash memory includes: between the first moment and the second moment, applies the first positive electricity and is depressed into
Described first wordline and the second wordline, described second moment lags behind described first moment；Described second
Between moment and the 3rd moment, apply the second positive electricity and be depressed into described first wordline and the second wordline, described
Three moment lagged behind described second moment, and described second positive voltage is higher than described first positive voltage, and described the
Time between two moment and the 3rd moment accounts for 10% of the time between described first moment and the 3rd moment
To 20%；Between described first moment and the 3rd moment, applying 0V voltage extremely described first drain region,
Second drain region and source region.
Optionally, the span of the time between described first moment and the 3rd moment is 2ms to 20ms.
Optionally, the span of described first positive voltage is 9V to 11V.
Optionally, the span of described second positive voltage is 12V to 13V.
Optionally, the time between described second moment and described 3rd moment is according to described first positive voltage
Determine with the size of described second positive voltage: when described first positive voltage determines, described second moment and
Time between described 3rd moment reduces with the increase of described second positive voltage；At described second positive electricity
When pressure determines, the time between described second moment and described 3rd moment is with the increasing of described first positive voltage
Reduce greatly.
Wordline control method based on above-mentioned flash memory, the invention provides the method for deleting of another kind of flash memory,
Described flash memory includes the first control gate, the second control gate, source region, drain region and wordline, described
The method for deleting of flash memory includes: between the first moment and the second moment, applies the first positive electricity and is depressed into described
Wordline, described second moment lags behind described first moment；Between described second moment and the 3rd moment,
Applying the second positive electricity and be depressed into described wordline, described 3rd moment lags behind described second moment, and described second
Positive voltage is higher than described first positive voltage, and the time between described second moment and the 3rd moment accounts for described the
10% to 20% of time between one moment and the 3rd moment；Described first moment and the 3rd moment it
Between, apply negative electricity and be depressed into described first control gate and the second control gate, apply 0V voltage to described source area
Territory and drain region.
Optionally, the span of described first positive voltage is 5V to 7V.
Optionally, the span of described second positive voltage is 8V to 9V.
Optionally, the span of described negative voltage is-6V to-8V.
Compared with prior art, technical scheme had the advantage that in the first moment and second
Between moment, the first positive electricity applying magnitude of voltage less is depressed into wordline, reduces between floating boom and wordline
Pressure reduction, i.e. reduces the voltage stress that tunnel oxide bears；Described second moment and the 3rd moment it
Between, applying the second positive electricity and be depressed into described wordline, described second positive voltage is higher than described first positive voltage, protects
Electronics in card floating boom is all flowed away by described wordline.Therefore, technical solution of the present invention is used to provide
The wordline control method of flash memory carries out erasing process to flash memory, on the premise of ensureing erasing effect, effectively
Reduce the voltage stress that described tunnel oxide bears, it is possible to slow down the degeneration of described tunnel oxide
Speed, improves the durability of described flash memory.
Accompanying drawing explanation
Fig. 1 is the wordline control method flow chart of the flash memory of the embodiment of the present invention；
Fig. 2 is the cross-sectional view of the flash memory that the embodiment of the present invention 1 relates to；
Fig. 3 is the method for deleting flow chart of the flash memory of the embodiment of the present invention 1；
Fig. 4 is the erasing voltage in the embodiment of the present invention 1 and prior art applied the flash memory shown in Fig. 2
Contrast schematic diagram；
Fig. 5 is that multiple flash memory is repeatedly wiped under the method for deleting of the embodiment of the present invention 1 and prior art
CURRENT DISTRIBUTION contrast schematic diagram after removing；
Fig. 6 is the cross-sectional view of the flash memory that the embodiment of the present invention 2 relates to；
Fig. 7 is the method for deleting flow chart of the flash memory of the embodiment of the present invention 2；
Fig. 8 is the erasing voltage in the embodiment of the present invention 2 and prior art applied the flash memory shown in Fig. 6
Contrast schematic diagram.
Detailed description of the invention
Just as described in the background art, the tunnel during flash memory is carried out erasing process, in flash memory
Wear oxide layer and bear bigger voltage stress.Described tunnel oxide is under bigger voltage stress effect
The degeneration that can produce, and then reduce the durability of whole flash memory.The inventor of the technical program passes through research,
Provide the wordline control method of a kind of flash memory.
Fig. 1 is the wordline control method flow chart of the flash memory of the embodiment of the present invention.With reference to Fig. 1, described flash memory
Wordline control method include:
Step S11: between the first moment and the second moment, applies the first positive electricity and is depressed into wordline, and described
Two moment lagged behind described first moment；
Step S12: between described second moment and the 3rd moment, applies the second positive electricity and is depressed into described wordline,
Described 3rd moment lags behind described second moment, and described second positive voltage is higher than described first positive voltage,
Time between described second moment and the 3rd moment accounts for the time between described first moment and the 3rd moment
10% to 20%.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Embodiment 1
Fig. 2 is the cross-sectional view of the flash memory that the embodiment of the present invention 1 relates to.With reference to Fig. 2, described sudden strain of a muscle
Bag deposit includes: Semiconductor substrate 10, and described Semiconductor substrate 10 has spaced first drain region
11 and second drain region 12；Source region 13, is arranged at described first drain region 11 and described
Between two drain regions 12；First storage bit unit 14, is positioned at described source region 13 and described first
Between drain region 11, described first storage bit unit 14 has the first floating boom 140；Second storage position is single
Unit 15, between described source region 13 and described second drain region 12, described second storage position
Unit 15 has the second floating boom 150；First wordline 16, is arranged at described first drain region 11 and institute
State between the first storage bit unit 14；Second wordline 17, is arranged at described second drain region 12 and institute
State between the second storage bit unit 15；Wherein, described first wordline 16 and described first storage bit unit
By tunnel oxide between 14 and between described second wordline 17 and described second storage bit unit 15
18 separate.
Generally, when the flash memory shown in Fig. 2 is carried out erasing process, by described first wordline 16 and institute
State between the first storage bit unit 14 and in described second wordline 17 and described second storage bit unit 15
Between form pressure reduction, thus form raceway groove in a flash memory.Electronics on described first floating boom 140 passes through ditch
Road arrives described first wordline 16, flows away from described first wordline 16；Electricity on described second floating boom 150
Son arrives described second wordline 17 by raceway groove, flows away from described second wordline 17, it is achieved the wiping to flash memory
Remove.
Fig. 3 is the method for deleting flow chart of the flash memory of the embodiment of the present invention 1.With reference to Fig. 3, described flash memory
Method for deleting includes:
Step S31: between the first moment and the second moment, applies the first positive electricity and is depressed into described first wordline
With the second wordline, described second moment lags behind described first moment；
Step S32: between described second moment and the 3rd moment, applies the second positive electricity and is depressed into described first
Wordline and the second wordline, described 3rd moment lags behind described second moment, and described second positive voltage is higher than
Described first positive voltage, the time between described second moment and the 3rd moment accounts for described first moment and the
10% to 20% of time between three moment；
Step S33: between described first moment and the 3rd moment, applies 0V voltage to described first leakage
Territory, polar region, the second drain region and source region.
For principle and the effect of technical solution of the present invention are better described, Fig. 4 gives the present embodiment with existing
Having the erasing voltage contrast schematic diagram in technology applied the flash memory shown in Fig. 2, transverse axis represents the erasing time,
Unit: ms, the longitudinal axis represents the erasing voltage of applying, unit: V.
Specifically, between described first moment t1 and described second moment t2, apply to described first word
Voltage on line 16 is the first positive voltage V1, apply to the voltage in described second wordline 17 be described the
One positive voltage V1；
Between described second moment t2 and the 3rd moment t3, apply the electricity to described first wordline 16
Pressure is the second positive voltage V2, and the voltage applied to described second wordline 17 is described second positive voltage V2,
Described second positive voltage V2 is higher than described first positive voltage V1；
Between described first moment t1 and described 3rd moment t3, apply to described first drain region 11
On voltage be always 0V voltage V3, the voltage applied to described second drain region 12 is always
0V voltage V3, the voltage applied to described source region 13 is always 0V voltage V3.
Specifically, described first moment t1 is the moment starting to apply erasing voltage, described 3rd moment t3
For terminating to apply the moment of erasing voltage, the time between described first moment t1 and described 3rd moment t3
It is the erasing time.The described erasing time can set according to concrete circuit structure, device parameters etc.
Fixed, in the present embodiment, the span in described erasing time is 2ms to 20ms.
Time between described second moment t2 and described 3rd moment t3 account for the 10% of the described erasing time to
20%.Further, the concrete time between described second moment t2 and described 3rd moment t3 can basis
Described first positive voltage V1 and the size of described second positive voltage V2 and be suitably configured or adjust.
When described first positive voltage V1 determines, between described second moment t2 and described 3rd moment t3
Time reduce with the increase of described second positive voltage V2, the most described second positive voltage V2 is relatively big,
Time between the most described second moment t2 and described 3rd moment t3 is shorter；If described second positive voltage
V2 is less, and the time between the most described second moment t2 and described 3rd moment t3 is longer.
When described second positive voltage V2 determines, between described second moment t2 and described 3rd moment t3
Time reduce with the increase of described first positive voltage V1, the most described first positive voltage V1 is relatively big,
Time between the most described second moment t2 and described 3rd moment t3 is shorter；If described first positive voltage
V1 is less, and the time between the most described second moment t2 and described 3rd moment t3 is longer.
When described first positive voltage V1 and described second positive voltage V2 can operate according to carrying out erasing, institute
State between the first wordline 16 and described first storage bit unit 14 and described second wordline 17 and described
Pressure reduction required between two storage bit unit 15 determines.In the present embodiment, described first positive voltage V1
Span be 9V to 11V, the span of described second positive voltage V2 is 12V to 13V.
With reference to Fig. 4, in prior art, between described first moment t1 and described 3rd moment t3, execute
Add to the voltage in described first wordline 16 and be always the 4th positive voltage V4, apply to described second wordline
Voltage on 17 is always described 4th positive voltage V4, i.e. at described second moment t2, applies to the most described the
Voltage in one wordline 16 and described second wordline 17 does not changes.In technical solution of the present invention,
Described second moment t2, applies the voltage to described first wordline 16 and described second wordline 17 by institute
State the first positive voltage V1 and switch to described second positive voltage V2, described first positive voltage V1 less than described
4th positive voltage V4, described second positive voltage V2 are higher than described 4th positive voltage V4.
In the present embodiment, between described first moment t1 and described second moment t2, apply described first
Positive voltage V1 is to described first wordline 16 and described second wordline 17, in described first floating boom 140 and institute
State between the first wordline 16 and between described second floating boom 150 and described second wordline 17, form ditch
Road, the electronics on described first floating boom 140 is flowed away by described first wordline 16, described second floating boom 150
On electronics flowed away by described second wordline 17.
Owing to described first positive voltage V1 is less than described 4th positive voltage V4, compared with prior art, originally
In embodiment between described first floating boom 140 and described first wordline 16 and at described second floating boom
The electric field intensity formed between 150 and described second wordline 17 reduces.To described second moment t2, described
The electronics do not wiped on a small quantity it is likely present on first floating boom 140 and described second floating boom 150.
For ensureing the erasing effect of flash memory, between described second moment t2 and described 3rd moment t3, execute
Add higher than the second positive voltage V2 of described 4th positive voltage V4 to described first wordline 16 and described second
Wordline 17, makes to be present on described first floating boom 140 electronics do not wiped on a small quantity by described first wordline
16 flow away, and make to be present on described second floating boom 150 electronics do not wiped on a small quantity by described second wordline
17 flow away.
In the present embodiment, due to described first wordline 16 and described second wordline 17 are applied described the
One positive voltage V1 is less than the described 4th positive voltage V4 applied in prior art, and just applies described first
The time of voltage V1 accounts for the 80%～90% of whole erasing time；To described first wordline 16 and described second
The described second positive voltage V2 that wordline 17 applies is higher than described 4th positive voltage applied in prior art
V4, and the time applying described second positive voltage V2 account for the 10%～20% of the whole erasing time.Therefore,
Compared with prior art, flash memory is carried out erasing process whole during, at described first floating boom 140
And shape between described first wordline 16 and between described second floating boom 150 and described second wordline 17
The electric field intensity become reduces, and the voltage stress that described tunnel oxide 18 bears reduces, therefore, it is possible to subtract
The catagen speed of slow described tunnel oxide 18, improves the durability of flash memory.
After flash memory is repeatedly wiped, the tunnel oxide degraded layer in flash memory, when reading flash memory, read
The electric current got can reduce.Therefore, the electric current read time by observing and flash memory being read
Value size, it can be determined that the degenerate case of tunnel oxide in flash memory, the electric current i.e. read is the least, says
Tunnel oxide catagen speed in bright flash memory is the fastest, and the durability of flash memory is the lowest.
Fig. 5 is after multiple flash memory is repeatedly wiped under the method for deleting of the present embodiment and prior art
CURRENT DISTRIBUTION comparison diagram, transverse axis represents electric current, after i.e. carrying out erasing operation, flash memory is carried out read operation reading
The electric current arrived, unit: μ A, the longitudinal axis represents and reads described in the standard deviation of standard normal distribution, i.e. correspondence
CURRENT DISTRIBUTION probability.
Specifically, the condition that flash memory carries out in the present embodiment erasing process is: described first positive voltage V1
For 11V, described second positive voltage V2 is 12.5V, described first moment t1 to described 3rd moment t3
Between time be 2ms, described second moment t2 is 200 μ s to the time between described 3rd moment t3.
The condition that flash memory carries out in prior art erasing process is: described 4th positive voltage V4 is 11.8V, institute
The time stated between the first moment t1 to described 3rd moment t3 is 2ms.
With reference to Fig. 5, the curve with triangle mark represents that multiple flash memory is under the method for deleting of prior art
Current profile after wiping first, the curve with rhombus mark represents that multiple flash memory is in this reality
Execute the current profile after wiping first under the method for deleting of example, with the curve table of circle markings
Show that multiple flash memory carries out the current profile after wiping, band under the method for deleting of prior art 90,000 times
The curve having square markings represents that multiple flash memory carries out 90,000 erasings under the method for deleting of the present embodiment
After current profile.
From fig. 5, it can be seen that multiple flash memories carry out head under the method for deleting of prior art and the present embodiment
After secondary erasing, flash memory is read, the size of current read in prior art and the present embodiment
Difference is the least, and after wiping first, the tunnel oxide degraded layer difference in flash memory is the least.Multiple flash memories
The current value read after carrying out 90,000 erasings under the method for deleting of prior art is significantly lower than this enforcement
The current value read after carrying out 90,000 erasings under the method for deleting of example.Therefore, the present embodiment is used
After flash memory is repeatedly wiped by method for deleting, the tunnel oxide catagen speed in flash memory is slower, it is possible to
Improve the durability of flash memory.
Embodiment 2
Fig. 6 is the cross-sectional view of the flash memory that the embodiment of the present invention 2 relates to.With reference to Fig. 6, described flash memory
Including: Semiconductor substrate 100, described Semiconductor substrate 100 has spaced source region 200 He
Drain region 300；Wordline 400, is arranged between described source region 200 and drain region 300；First
Storage bit unit 500, between described wordline 400 and described source region 200, described first storage position
Unit 500 has spaced first control gate 510 and the first floating boom 520；Second storage bit unit 600,
Between described wordline 400 and described drain region 300, described second storage bit unit 600 has interval
The second control gate 610 and the second floating boom 620 arranged；Wherein, said two storage bit unit and described word
Between line 400 and between described wordline 400 and described Semiconductor substrate 100 by tunnel oxide 700 every
Open.
Fig. 7 is the flow chart of the method for deleting of the flash memory of the embodiment of the present invention 2.With reference to Fig. 7, described flash memory
Method for deleting include:
S71: between the first moment and the second moment, applies the first positive electricity and is depressed into described wordline, and described
Two moment lagged behind described first moment；
S72: between described second moment and the 3rd moment, applies the second positive electricity and is depressed into described wordline, institute
Stating for the 3rd moment lags behind described second moment, and described second positive voltage is higher than described first positive voltage, institute
The time between the second moment and the 3rd moment of stating accounts for the time between described first moment and the 3rd moment
10% to 20%；
S73: between described first moment and the 3rd moment, apply negative electricity be depressed into described first control gate and
Second control gate, applies 0V voltage to described source region and drain region.
Fig. 8 is that the erasing voltage contrast in the present embodiment and prior art applied the flash memory shown in Fig. 6 is shown
Being intended to, transverse axis represents the erasing time, unit: ms, and the longitudinal axis represents the erasing voltage of applying, unit: V.
For preferably the present embodiment being understood, below in conjunction with the accompanying drawings the method for deleting of the present embodiment flash memory is entered
Row describes in detail.
With reference to Fig. 6 and Fig. 8, between the first moment t1 and the second moment t2, apply to described wordline 400
On voltage be the first positive voltage U1；
Between described second moment t2 and the 3rd moment t3, the voltage applied to described wordline 400 is
Second positive voltage U2, described second positive voltage U2 are higher than described first positive voltage U1；
Between described first moment t1 and described 3rd moment t3, apply to described first control gate 510
On voltage be always negative voltage U3, the voltage applied to described second control gate 610 is always described
Negative voltage U3, the voltage applied to described source region 200 and described drain region 300 is always 0V
Voltage U4.
Specifically, described first moment t1 is the moment starting to apply erasing voltage, described 3rd moment t3
For terminating to apply the moment of erasing voltage, the time between described first moment t1 and described 3rd moment t3
It is the erasing time.The described erasing time can set according to concrete circuit structure, device parameters etc.
Fixed, in the present embodiment, the span in described erasing time is 2ms to 20ms.
Time between described second moment t2 and described 3rd moment t3 account for the 10% of the described erasing time to
20%.Further, the concrete time between described second moment t2 and described 3rd moment t3 can basis
Described first positive voltage U1 and the size of described second positive voltage U2 and be suitably configured or adjust.
When described first positive voltage U1 determines, between described second moment t2 and described 3rd moment t3
Time reduce with the increase of described second positive voltage U2, the most described second positive voltage U2 is relatively big,
Time between the most described second moment t2 and described 3rd moment t3 is shorter；If described second positive voltage
U2 is less, and the time between the most described second moment t2 and described 3rd moment t3 is longer.
When described second positive voltage U2 determines, between described second moment t2 and described 3rd moment t3
Time reduce with the increase of described first positive voltage U1, the most described first positive voltage U1 is relatively big,
Time between the most described second moment t2 and described 3rd moment t3 is shorter；If described first positive voltage
U1 is less, and the time between the most described second moment t2 and described 3rd moment t3 is longer.
Described first positive voltage U1, described second positive voltage U2 and described negative voltage U3 can be according to entering
During row erasing operation, between described wordline 400 and described first storage bit unit 500 and described wordline
Pressure reduction required between 400 and described second storage bit unit 600 determines.In the present embodiment, described
The span of one positive voltage U1 is 5V to 7V, and the span of described second positive voltage U2 is 8V
To 9V, the span of described negative voltage U3 is-6V to-8V.
Similar to Example 1, in the present embodiment, due to described wordline 400 is applied described first just
Voltage U1 is less than the 5th voltage U5 applied described wordline 400 in prior art, and applies described the
The time of one positive voltage U1 accounts for the 80%～90% of whole erasing time；The institute that described wordline 400 is applied
State the second positive voltage U2 and be higher than described 5th voltage U5, and apply the time of described second positive voltage U2
Account for the 10%～20% of the whole erasing time.Therefore, compared with prior art, flash memory is carried out erasing process
Whole during, between described first floating boom 520 and described wordline 400 and described second float
The electric field intensity formed between grid 620 and described wordline 400 reduces, and described tunnel oxide 700 bears
Voltage stress reduce, therefore, it is possible to slow down the catagen speed of described tunnel oxide 700, improve dodge
The durability deposited.
In sum, wordline control method and the wiping of flash memory of the flash memory of technical solution of the present invention offer are provided
Except flash memory is wiped by method, it is possible to reduce the catagen speed of tunnel oxide in flash memory, improve flash memory
Durability.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (12)
1. a wordline control method for flash memory, the erasing for described flash memory operates, it is characterised in that including:
Between the first moment and the second moment, applying the first positive electricity and be depressed into wordline, described second moment is stagnant
After in described first moment；
Between described second moment and the 3rd moment, apply the second positive electricity and be depressed into described wordline, described
Three moment lagged behind described second moment, and described second positive voltage is higher than described first positive voltage, and described the
Time between two moment and the 3rd moment accounts for 10% of the time between described first moment and the 3rd moment
To 20%.
2. a method for deleting for flash memory, described flash memory includes: the first wordline, the second wordline, the first drain region
Territory, the second drain region and source region, it is characterised in that the method for deleting of described flash memory includes:
Between the first moment and the second moment, apply the first positive electricity and be depressed into described first wordline and the second word
Line, described second moment lags behind described first moment；
Between described second moment and the 3rd moment, apply the second positive electricity and be depressed into described first wordline and
Two wordline, described 3rd moment lags behind described second moment, and described second positive voltage is higher than described first
Positive voltage, the time between described second moment and the 3rd moment account for described first moment and the 3rd moment it
Between time 10% to 20%；
Between described first moment and the 3rd moment, apply 0V voltage to described first drain region, the
Two drain regions and source region.
The method for deleting of flash memory the most according to claim 2, it is characterised in that described first moment and the
The span of the time between three moment is 2ms to 20ms.
The method for deleting of flash memory the most according to claim 2, it is characterised in that described first positive voltage
Span is 9V to 11V.
The method for deleting of flash memory the most according to claim 2, it is characterised in that described second positive voltage
Span is 12V to 13V.
The method for deleting of flash memory the most according to claim 2, it is characterised in that described second moment and institute
The time stated between the 3rd moment determines according to the size of described first positive voltage and described second positive voltage:
When described first positive voltage determines, the time between described second moment and described 3rd moment is with described
The increase of the second positive voltage and reduce；When described second positive voltage determines, described second moment and described
Time between 3rd moment reduces with the increase of described first positive voltage.
7. a method for deleting for flash memory, described flash memory includes: the first control gate, the second control gate, source area
Territory, drain region and wordline, it is characterised in that the method for deleting of described flash memory includes:
Between the first moment and the second moment, apply the first positive electricity and be depressed into described wordline, when described second
Lag behind described first moment quarter；
Between described second moment and the 3rd moment, apply the second positive electricity and be depressed into described wordline, described
Three moment lagged behind described second moment, and described second positive voltage is higher than described first positive voltage, and described the
Time between two moment and the 3rd moment accounts for 10% of the time between described first moment and the 3rd moment
To 20%；
Between described first moment and the 3rd moment, apply negative electricity and be depressed into described first control gate and second
Control gate, applies 0V voltage to described source region and drain region.
The method for deleting of flash memory the most according to claim 7, it is characterised in that described first positive voltage
Span is 5V to 7V.
The method for deleting of flash memory the most according to claim 7, it is characterised in that described second positive voltage
Span is 8V to 9V.
The method for deleting of flash memory the most according to claim 7, it is characterised in that described first moment and the
The span of the time between three moment is 2ms to 20ms.
The method for deleting of 11. flash memories according to claim 7, it is characterised in that the value of described negative voltage
Scope is-6V to-8V.
The method for deleting of 12. flash memories according to claim 7, it is characterised in that described second moment and institute
The time stated between the 3rd moment determines according to the size of described first positive voltage and described second positive voltage:
When described first positive voltage determines, the time between described second moment and described 3rd moment is with described
The increase of the second positive voltage and reduce；When described second positive voltage determines, described second moment and described
Time between 3rd moment reduces with the increase of described first positive voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310261449.9A CN103345938B (en) | 2013-06-26 | 2013-06-26 | The wordline control method of flash memory and the method for deleting of flash memory |
Applications Claiming Priority (1)
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