CN103345938A - Word line control method and erasing method for flash memory - Google Patents
Word line control method and erasing method for flash memory Download PDFInfo
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- CN103345938A CN103345938A CN2013102614499A CN201310261449A CN103345938A CN 103345938 A CN103345938 A CN 103345938A CN 2013102614499 A CN2013102614499 A CN 2013102614499A CN 201310261449 A CN201310261449 A CN 201310261449A CN 103345938 A CN103345938 A CN 103345938A
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Abstract
The invention discloses a word line control method and an erasing method for a flash memory. The word line control method comprises the following steps of: applying a first positive voltage to a word line at the time between a first moment and a second moment, wherein the second moment lags behind the first moment; applying a second positive voltage to the word line at the time between the second moment and a third moment, wherein the third moment lags behind the second moment, the second positive voltage is higher than the first positive voltage, and the time between the second moment and the third moment accounts for 10%-20% of the time between the first moment and the third moment. According to the word line control method and the erasing method provided by the technical scheme of the invention, the degradation speed of a tunnel oxide layer in the flash memory can be reduced and the durability of the flash memory can be improved.
Description
Technical field
The present invention relates to the memory technology field, particularly a kind of word line traffic control method of flash memory and the method for deleting of flash memory.
Background technology
Flash memory (Flash Memory) is as a kind of integrated circuit memory devices, because but it has high speed, high density micro, still can keep plurality of advantages such as data after cutting off the power supply, be widely used in as in the electronic products such as portable computer, mobile phone, digital music player.Flash memory is as a kind of nonvolatile memory, and its operation principles is to control the switch of gate pole passage by the critical voltage that changes storage unit, to reach the purpose of storage data, the data that are stored in the storage unit can not disappeared because of power interruption.Nowadays flash memory has occupied most of market share of nonvolatile memory, becomes nonvolatile memory with fastest developing speed.
Usually, when flash memory is wiped processing, need apply higher voltage to flash memory.In erase process, the tunnel oxide in the flash memory has born bigger voltage stress.Bigger voltage stress causes the degeneration of tunnel oxide, and then reduces the permanance of whole flash memory.Permanance is to weigh an important indicator of flash memory reliability, refers to still can not lose efficacy through repeatedly wiping processing back flash memory.The catagen speed of the tunnel oxide in the flash memory is more fast, and the permanance of flash memory is more low.
Along with the application of flash memory more and more widely, slow down the catagen speed of tunnel oxide in the flash memory, the permanance that improves flash memory is a problem demanding prompt solution.
Summary of the invention
The present invention solves is the problem that the tunnel oxide catagen speed is fast, the flash memory permanance is low in the flash memory.
For addressing the above problem, the invention provides a kind of word line traffic control method of flash memory, comprising: between first moment and second moment, apply first positive voltage to the word line, described second lags behind described first constantly constantly; Between described second moment and the 3rd moment, apply second positive voltage to described word line, the described the 3rd lags behind described second constantly constantly, described second positive voltage is higher than described first positive voltage, described second constantly and the 3rd time between constantly accounted for described first constantly and the 3rd between constantly time 10% to 20%.
Word line traffic control method based on above-mentioned flash memory, the invention provides a kind of method for deleting of flash memory, described flash memory comprises the first word line, the second word line, first drain region, second drain region and source region, the method for deleting of described flash memory comprises: between first moment and second moment, apply first positive voltage to the described first word line and the second word line, described second lags behind described first constantly constantly; Between described second moment and the 3rd moment, apply second positive voltage to the described first word line and the second word line, the described the 3rd lags behind described second constantly constantly, described second positive voltage is higher than described first positive voltage, described second constantly and the 3rd time between constantly accounted for described first constantly and the 3rd between constantly time 10% to 20%; Between described first moment and the 3rd moment, apply 0V voltage extremely described first drain region, second drain region and source region.
Optionally, described first constantly and the 3rd the span of time between constantly be 2ms to 20ms.
Optionally, the span of described first positive voltage is 9V to 11V.
Optionally, the span of described second positive voltage is 12V to 13V.
Optionally, time between described second moment and described the 3rd moment is determined according to the size of described first positive voltage and described second positive voltage: when described first positive voltage was determined, the increase of the time between described second moment and described the 3rd moment with described second positive voltage reduced; When described second positive voltage was determined, the increase of the time between described second moment and described the 3rd moment with described first positive voltage reduced.
Word line traffic control method based on above-mentioned flash memory, the invention provides the method for deleting of another kind of flash memory, described flash memory comprises first control gate, second control gate, source region, drain region and word line, the method for deleting of described flash memory comprises: between first moment and second moment, apply first positive voltage to described word line, described second lags behind described first constantly constantly; Between described second moment and the 3rd moment, apply second positive voltage to described word line, the described the 3rd lags behind described second constantly constantly, described second positive voltage is higher than described first positive voltage, described second constantly and the 3rd time between constantly accounted for described first constantly and the 3rd between constantly time 10% to 20%; Between described first moment and the 3rd moment, apply negative voltage to described first control gate and second control gate, apply 0V voltage to described source region and drain region.
Optionally, the span of described first positive voltage is 5V to 7V.
Optionally, the span of described second positive voltage is 8V to 9V.
Optionally, the span of described negative voltage be-6V is to-8V.
Compared with prior art, technical scheme of the present invention has the following advantages: between first moment and second moment, apply the first less positive voltage of magnitude of voltage to the word line, reduced the pressure reduction between floating boom and the word line, namely reduced the voltage stress that tunnel oxide bears; Between described second moment and the 3rd moment, apply second positive voltage to described word line, described second positive voltage is higher than described first positive voltage, guarantees that the electronics in the floating boom is all walked by described word linear flow.Therefore, the word line traffic control method of the flash memory that the use technical solution of the present invention provides is wiped processing to flash memory, wipe under the prerequisite of effect in assurance, reduced the voltage stress that described tunnel oxide bears effectively, can slow down the catagen speed of described tunnel oxide, improve the permanance of described flash memory.
Description of drawings
Fig. 1 is the word line traffic control method flow diagram of the flash memory of the embodiment of the invention;
Fig. 2 is the cross-sectional view of the flash memory that relates to of the embodiment of the invention 1;
Fig. 3 is the method for deleting process flow diagram of the flash memory of the embodiment of the invention 1;
Fig. 4 is the erasing voltage contrast synoptic diagram that in the embodiment of the invention 1 and the prior art flash memory shown in Figure 2 is applied;
Fig. 5 is the distribution of current contrast synoptic diagram of a plurality of flash memories after repeatedly wiping under the method for deleting of the embodiment of the invention 1 and prior art;
Fig. 6 is the cross-sectional view of the flash memory that relates to of the embodiment of the invention 2;
Fig. 7 is the method for deleting process flow diagram of the flash memory of the embodiment of the invention 2;
Fig. 8 is the erasing voltage contrast synoptic diagram that in the embodiment of the invention 2 and the prior art flash memory shown in Figure 6 is applied.
Embodiment
Just as described in the background art, flash memory to be wiped in the process of processing, the tunnel oxide in the flash memory has born bigger voltage stress.Described tunnel oxide is understood the degeneration that produces under bigger voltage stress effect, and then reduces the permanance of whole flash memory.The inventor of the technical program provides a kind of word line traffic control method of flash memory through research.
Fig. 1 is the word line traffic control method flow diagram of the flash memory of the embodiment of the invention.With reference to figure 1, the word line traffic control method of described flash memory comprises:
Step S11: between first moment and second moment, apply first positive voltage to the word line, described second lags behind described first constantly constantly;
Step S12: between described second moment and the 3rd moment, apply second positive voltage to described word line, the described the 3rd lags behind described second constantly constantly, described second positive voltage is higher than described first positive voltage, described second constantly and the 3rd time between constantly accounted for described first constantly and the 3rd between constantly time 10% to 20%.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing specific embodiments of the invention are described in detail.
Fig. 2 is the cross-sectional view of the flash memory that relates to of the embodiment of the invention 1.With reference to figure 2, described flash memory comprises: Semiconductor substrate 10 has first drain region 11 and second drain region 12 that arrange at interval on the described Semiconductor substrate 10; Source region 13 is arranged between described first drain region 11 and described second drain region 12; First storage bit unit 14, between described source region 13 and described first drain region 11, described first storage bit unit 14 has first floating boom 140; Second storage bit unit 15, between described source region 13 and described second drain region 12, described second storage bit unit 15 has second floating boom 150; The first word line 16 is arranged between described first drain region 11 and described first storage bit unit 14; The second word line 17 is arranged between described second drain region 12 and described second storage bit unit 15; Wherein, separate by tunnel oxide 18 between the described first word line 16 and described first storage bit unit 14 and between the described second word line 17 and described second storage bit unit 15.
Usually, flash memory shown in Figure 2 is wiped when handling, by forming pressure reduction between the described first word line 16 and described first storage bit unit 14 and between the described second word line 17 and described second storage bit unit 15, thereby in flash memory, formed raceway groove.Electronics on described first floating boom 140 arrives the described first word line 16 by raceway groove, flows away from the described first word line 16; Electronics on described second floating boom 150 arrives the described second word line 17 by raceway groove, flows away from the described second word line 17, realizes wiping flash memory.
Fig. 3 is the method for deleting process flow diagram of the flash memory of the embodiment of the invention 1.With reference to figure 3, the method for deleting of described flash memory comprises:
Step S31: between first moment and second moment, apply first positive voltage to the described first word line and the second word line, described second lags behind described first constantly constantly;
Step S32: between described second moment and the 3rd moment, apply second positive voltage to the described first word line and the second word line, the described the 3rd lags behind described second constantly constantly, described second positive voltage is higher than described first positive voltage, described second constantly and the 3rd time between constantly accounted for described first constantly and the 3rd between constantly time 10% to 20%;
Step S33: between described first moment and the 3rd moment, apply 0V voltage extremely described first drain region, second drain region and source region.
Be principle and the effect that technical solution of the present invention is described better, Fig. 4 has provided the erasing voltage contrast synoptic diagram that in present embodiment and the prior art flash memory shown in Figure 2 is applied, and transverse axis is represented the erasing time, unit: ms, the longitudinal axis is represented the erasing voltage that applies, unit: V.
Particularly, between described first moment t1 and described second moment t2, the voltage that is applied on the described first word line 16 is the first positive voltage V1, and the voltage that is applied on the described second word line 17 is the described first positive voltage V1;
Between described second moment t2 and the 3rd moment t3, the voltage that is applied on the described first word line 16 is the second positive voltage V2, the voltage that is applied on the described second word line 17 is the described second positive voltage V2, and the described second positive voltage V2 is higher than the described first positive voltage V1;
Between described first moment t1 and described the 3rd moment t3, the voltage that is applied on described first drain region 11 is always 0V voltage V3, the voltage that is applied on described second drain region 12 is always 0V voltage V3, and the voltage that is applied on the described source region 13 is always 0V voltage V3.
Particularly, described first moment t1 is the moment that begins to apply erasing voltage, and described the 3rd moment t3 is for finishing to apply the moment of erasing voltage, and the time between described first moment t1 and described the 3rd moment t3 is the erasing time.The described erasing time can be set according to concrete circuit structure, device parameters etc., and in the present embodiment, the span in described erasing time is 2ms to 20ms.
Time between described second moment t2 and described the 3rd moment t3 accounts for 10% to 20% of the described erasing time.Further, described second constantly t2 and the described the 3rd the concrete time between the t3 can suitably arrange or adjust according to the size of the described first positive voltage V1 and the described second positive voltage V2 constantly.
When the described first positive voltage V1 determines, the increase of time between described second moment t2 and described the 3rd moment t3 with the described second positive voltage V2 reduces, the even described second positive voltage V2 is bigger, and then the time between described second moment t2 and described the 3rd moment t3 is shorter; If the described second positive voltage V2 is less, then the time between described second moment t2 and described the 3rd moment t3 is longer.
When the described second positive voltage V2 determines, the increase of time between described second moment t2 and described the 3rd moment t3 with the described first positive voltage V1 reduces, the even described first positive voltage V1 is bigger, and then the time between described second moment t2 and described the 3rd moment t3 is shorter; If the described first positive voltage V1 is less, then the time between described second moment t2 and described the 3rd moment t3 is longer.
The described first positive voltage V1 and the described second positive voltage V2 can be when carrying out erase operation, and required pressure reduction is determined between the described first word line 16 and described first storage bit unit 14 and between the described second word line 17 and described second storage bit unit 15.In the present embodiment, the span of the described first positive voltage V1 is 9V to 11V, and the span of the described second positive voltage V2 is 12V to 13V.
With reference to figure 4, in the prior art, between described first moment t1 and described the 3rd moment t3, the voltage that is applied on the described first word line 16 is always the 4th positive voltage V4, the voltage that is applied on the described second word line 17 is always described the 4th positive voltage V4, namely at described second moment t2, the voltage that is applied on the described first word line 16 and the described second word line 17 does not change.In the technical solution of the present invention, at described second moment t2, the voltage that is applied on the described first word line 16 and the described second word line 17 switches to the described second positive voltage V2 by the described first positive voltage V1, the described first positive voltage V1 is lower than described the 4th positive voltage V4, and the described second positive voltage V2 is higher than described the 4th positive voltage V4.
In the present embodiment, between described first moment t1 and described second moment t2, apply the described first positive voltage V1 to the described first word line 16 and the described second word line 17, forming raceway groove between described first floating boom 140 and the described first word line 16 and between described second floating boom 150 and the described second word line 17, electronics on described first floating boom 140 flows away by the described first word line 16, and the electronics on described second floating boom 150 flows away by the described second word line 17.
Because the described first positive voltage V1 is lower than described the 4th positive voltage V4, compared with prior art, reduce in the electric field intensity that forms between described first floating boom 140 and the described first word line 16 and between described second floating boom 150 and the described second word line 17 in the present embodiment.To described second moment t2, may also there be the electronics of not wiping on a small quantity on described first floating boom 140 and described second floating boom 150.
For guaranteeing the effect of wiping of flash memory, between described second moment t2 and described the 3rd moment t3, apply the second positive voltage V2 that is higher than described the 4th positive voltage V4 to the described first word line 16 and the described second word line 17, make to be present on described first floating boom 140 electronics of not wiping on a small quantity and to flow away by the described first word line 16, make to be present in the electronics of not wiping on a small quantity on described second floating boom 150 and to flow away by the described second word line 17.
In the present embodiment, because the described first positive voltage V1 that the described first word line 16 and the described second word line 17 are applied is lower than described the 4th positive voltage V4 that applies in the prior art, and the time that applies the described first positive voltage V1 account for 80%～90% of the whole erasing time; The described second positive voltage V2 that the described first word line 16 and the described second word line 17 are applied is higher than described the 4th positive voltage V4 that applies in the prior art, and the time that applies the described second positive voltage V2 accounts for 10%～20% of the whole erasing time.Therefore, compared with prior art, flash memory is wiped in the whole process of processing, reduce in the electric field intensity that forms between described first floating boom 140 and the described first word line 16 and between described second floating boom 150 and the described second word line 17, the voltage stress that described tunnel oxide 18 bears reduces, therefore, can slow down the catagen speed of described tunnel oxide 18, improve the permanance of flash memory.
After flash memory repeatedly wiped, the tunnel oxide degraded layer in the flash memory, when reading flash memory, the electric current that reads can reduce to some extent.Therefore, the current value size of reading when by observing flash memory being carried out read operation can be judged the degenerate case of tunnel oxide in the flash memory, and the electric current that namely reads is more little, illustrates that the tunnel oxide catagen speed in the flash memory is more fast, and the permanance of flash memory is more low.
Fig. 5 is the distribution of current comparison diagrams of a plurality of flash memories after repeatedly wiping under the method for deleting of present embodiment and prior art, transverse axis is represented electric current, namely carry out behind the erase operation flash memory being carried out the electric current that read operation reads, unit: μ A, the longitudinal axis is represented the standard deviation of standardized normal distribution, i.e. the corresponding described distribution of current probability that reads.
Particularly, the condition of in the present embodiment flash memory being wiped processing is: the described first positive voltage V1 is 11V, the described second positive voltage V2 is 12.5V, described first moment t1 is 2ms to the time between described the 3rd moment t3, and the time between extremely described the 3rd moment t3 of described second moment t2 is 200 μ s.The condition of in the prior art flash memory being wiped processing is: described the 4th positive voltage V4 is 11.8V, described first constantly t1 the time between the t3 is 2ms constantly to the described the 3rd.
With reference to figure 5, the curve that has the triangle mark is represented the distribution of current curve of a plurality of flash memories after wiping first under the method for deleting of prior art, the curve that has the rhombus mark is represented the distribution of current curve of a plurality of flash memories after wiping first under the method for deleting of present embodiment, the curve that has a circle markings is represented the distribution of current curve of a plurality of flash memories after carrying out under the method for deleting of prior art wiping for 90,000 times, and the curve that has a square markings is represented the distribution of current curve of a plurality of flash memories after carrying out under the method for deleting of present embodiment wiping for 90,000 times.
As can be seen from Figure 5, a plurality of flash memories are after wiping first under the method for deleting of prior art and present embodiment, flash memory is carried out read operation, the size of current difference that reads in prior art and the present embodiment is very little, and the tunnel oxide degraded layer difference of namely wiping first in the flash memory of back is very little.The current value that the current value that a plurality of flash memories read after carrying out under the method for deleting of prior art wiping for 90,000 times reads after being starkly lower than and carrying out wiping for 90,000 times under the method for deleting of present embodiment.Therefore, after the method for deleting of employing present embodiment was repeatedly wiped flash memory, the tunnel oxide catagen speed in the flash memory was slower, can improve the permanance of flash memory.
Fig. 6 is the cross-sectional view of the flash memory that relates to of the embodiment of the invention 2.With reference to figure 6, described flash memory comprises: Semiconductor substrate 100 has the source region 200 and the drain region 300 that arrange at interval on the described Semiconductor substrate 100; Word line 400 is arranged between described source region 200 and the drain region 300; First storage bit unit 500, between described word line 400 and described source region 200, described first storage bit unit 500 has first control gate 510 and first floating boom 520 that arranges at interval; Second storage bit unit 600, between described word line 400 and described drain region 300, described second storage bit unit 600 has second control gate 610 and second floating boom 620 that arranges at interval; Wherein, separate by tunnel oxide 700 between described two storage bit unit and the described word line 400 and between described word line 400 and the described Semiconductor substrate 100.
Fig. 7 is the process flow diagram of method for deleting of the flash memory of the embodiment of the invention 2.With reference to figure 7, the method for deleting of described flash memory comprises:
S71: between first moment and second moment, apply first positive voltage to described word line, described second lags behind described first constantly constantly;
S72: between described second moment and the 3rd moment, apply second positive voltage to described word line, the described the 3rd lags behind described second constantly constantly, described second positive voltage is higher than described first positive voltage, described second constantly and the 3rd time between constantly accounted for described first constantly and the 3rd between constantly time 10% to 20%;
S73: between described first moment and the 3rd moment, apply negative voltage to described first control gate and second control gate, apply 0V voltage to described source region and drain region.
Fig. 8 is the erasing voltage contrast synoptic diagram that in present embodiment and the prior art flash memory shown in Figure 6 is applied, and transverse axis is represented the erasing time, unit: ms, the longitudinal axis represent the erasing voltage that applies, unit: V.For better present embodiment being understood, be elaborated below in conjunction with the method for deleting of accompanying drawing to the present embodiment flash memory.
With reference to figure 6 and Fig. 8, between first moment t1 and second moment t2, the voltage that is applied on the described word line 400 is the first positive voltage U1;
Between described second moment t2 and the 3rd moment t3, the voltage that is applied on the described word line 400 is the second positive voltage U2, and the described second positive voltage U2 is higher than the described first positive voltage U1;
Between described first moment t1 and described the 3rd moment t3, the voltage that is applied on described first control gate 510 is always negative voltage U3, the voltage that is applied on described second control gate 610 is always described negative voltage U3, and the voltage that is applied on described source region 200 and the described drain region 300 is always 0V voltage U 4.
Particularly, described first moment t1 is the moment that begins to apply erasing voltage, and described the 3rd moment t3 is for finishing to apply the moment of erasing voltage, and the time between described first moment t1 and described the 3rd moment t3 is the erasing time.The described erasing time can be set according to concrete circuit structure, device parameters etc., and in the present embodiment, the span in described erasing time is 2ms to 20ms.
Time between described second moment t2 and described the 3rd moment t3 accounts for 10% to 20% of the described erasing time.Further, described second constantly t2 and the described the 3rd the concrete time between the t3 can suitably arrange or adjust according to the size of the described first positive voltage U1 and the described second positive voltage U2 constantly.
When the described first positive voltage U1 determines, the increase of time between described second moment t2 and described the 3rd moment t3 with the described second positive voltage U2 reduces, the even described second positive voltage U2 is bigger, and then the time between described second moment t2 and described the 3rd moment t3 is shorter; If the described second positive voltage U2 is less, then the time between described second moment t2 and described the 3rd moment t3 is longer.
When the described second positive voltage U2 determines, the increase of time between described second moment t2 and described the 3rd moment t3 with the described first positive voltage U1 reduces, the even described first positive voltage U1 is bigger, and then the time between described second moment t2 and described the 3rd moment t3 is shorter; If the described first positive voltage U1 is less, then the time between described second moment t2 and described the 3rd moment t3 is longer.
The described first positive voltage U1, the described second positive voltage U2 and described negative voltage U3 can be when carrying out erase operation, and required pressure reduction is determined between described word line 400 and described first storage bit unit 500 and between described word line 400 and described second storage bit unit 600.In the present embodiment, the span of the described first positive voltage U1 is 5V to 7V, and the span of the described second positive voltage U2 is 8V to 9V, and the span of described negative voltage U3 is-and 6V is to-8V.
Similar to embodiment 1, in the present embodiment, because the described first positive voltage U1 that described word line 400 is applied is lower than the 5th voltage U 5 that in the prior art described word line 400 is applied, and the time that applies the described first positive voltage U1 account for 80%～90% of the whole erasing time; The described second positive voltage U2 that described word line 400 is applied is higher than described the 5th voltage U 5, and the time that applies the described second positive voltage U2 accounts for 10%～20% of the whole erasing time.Therefore, compared with prior art, flash memory is wiped in the whole process of processing, reduce in the electric field intensity that forms between described first floating boom 520 and the described word line 400 and between described second floating boom 620 and described word line 400, the voltage stress that described tunnel oxide 700 bears reduces, therefore, can slow down the catagen speed of described tunnel oxide 700, improve the permanance of flash memory.
In sum, the word line traffic control method of the flash memory that the use technical solution of the present invention provides and the method for deleting of flash memory are wiped flash memory, can reduce the catagen speed of tunnel oxide in the flash memory, improve the permanance of flash memory.
Though the present invention discloses as above, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (12)
1. the word line traffic control method of a flash memory is characterized in that, comprising:
Between first moment and second moment, apply first positive voltage to the word line, described second lags behind described first constantly constantly;
Between described second moment and the 3rd moment, apply second positive voltage to described word line, the described the 3rd lags behind described second constantly constantly, described second positive voltage is higher than described first positive voltage, described second constantly and the 3rd time between constantly accounted for described first constantly and the 3rd between constantly time 10% to 20%.
2. the method for deleting of a flash memory, described flash memory comprises: the first word line, the second word line, first drain region, second drain region and source region is characterized in that the method for deleting of described flash memory comprises:
Between first moment and second moment, apply first positive voltage to the described first word line and the second word line, described second lags behind described first constantly constantly;
Between described second moment and the 3rd moment, apply second positive voltage to the described first word line and the second word line, the described the 3rd lags behind described second constantly constantly, described second positive voltage is higher than described first positive voltage, described second constantly and the 3rd time between constantly accounted for described first constantly and the 3rd between constantly time 10% to 20%;
Between described first moment and the 3rd moment, apply 0V voltage extremely described first drain region, second drain region and source region.
3. the method for deleting of flash memory according to claim 2 is characterized in that, the span of the time between described first moment and the 3rd moment is 2ms to 20ms.
4. the method for deleting of flash memory according to claim 2 is characterized in that, the span of described first positive voltage is 9V to 11V.
5. the method for deleting of flash memory according to claim 2 is characterized in that, the span of described second positive voltage is 12V to 13V.
6. the method for deleting of flash memory according to claim 2, it is characterized in that, time between described second moment and described the 3rd moment is determined according to the size of described first positive voltage and described second positive voltage: when described first positive voltage was determined, the increase of the time between described second moment and described the 3rd moment with described second positive voltage reduced; When described second positive voltage was determined, the increase of the time between described second moment and described the 3rd moment with described first positive voltage reduced.
7. the method for deleting of a flash memory, described flash memory comprises: first control gate, second control gate, source region, drain region and word line is characterized in that the method for deleting of described flash memory comprises:
Between first moment and second moment, apply first positive voltage to described word line, described second lags behind described first constantly constantly;
Between described second moment and the 3rd moment, apply second positive voltage to described word line, the described the 3rd lags behind described second constantly constantly, described second positive voltage is higher than described first positive voltage, described second constantly and the 3rd time between constantly accounted for described first constantly and the 3rd between constantly time 10% to 20%;
Between described first moment and the 3rd moment, apply negative voltage to described first control gate and second control gate, apply 0V voltage to described source region and drain region.
8. the method for deleting of flash memory according to claim 7 is characterized in that, the span of described first positive voltage is 5V to 7V.
9. the method for deleting of flash memory according to claim 7 is characterized in that, the span of described second positive voltage is 8V to 9V.
10. the method for deleting of flash memory according to claim 7 is characterized in that, the span of the time between described first moment and the 3rd moment is 2ms to 20ms.
11. the method for deleting of flash memory according to claim 7 is characterized in that, and the span of described negative voltage is-and 6V is to-8V.
12. the method for deleting of flash memory according to claim 7, it is characterized in that, time between described second moment and described the 3rd moment is determined according to the size of described first positive voltage and described second positive voltage: when described first positive voltage was determined, the increase of the time between described second moment and described the 3rd moment with described second positive voltage reduced; When described second positive voltage was determined, the increase of the time between described second moment and described the 3rd moment with described first positive voltage reduced.
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| JPH01139887A (en) * | 1987-11-19 | 1989-06-01 | Agency Of Ind Science & Technol | Method and apparatus for producing high whiteness long fiber pulp by digesting bast under atmospheric pressure at high speed |
| CN1574085A (en) * | 2003-05-29 | 2005-02-02 | 海力士半导体有限公司 | Method and apparatus for rapidly storing data in memory cell without voltage loss |
| US20100238730A1 (en) * | 2009-03-17 | 2010-09-23 | Deepanshu Dutta | Controlling select gate voltage during erase to improve endurance in non-volatile memory |
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