CN103342332B - Integrated thermal electric based on CMOS technology piles IRDS and preparation method thereof - Google Patents
Integrated thermal electric based on CMOS technology piles IRDS and preparation method thereof Download PDFInfo
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Abstract
The present invention relates to a kind of integrated thermal electric based on CMOS technology heap IRDS and preparation method thereof, described IRDS is divided into thermopile IR detector and cmos signal treatment circuit two parts, improve the compatibility of MEMS thermopile sensor and cmos signal treatment circuit, adopt CMOS technology integrated thermal electric heap Infrared Detectors and cmos signal treatment circuit completely, by corrosion opening well-designed in sensor unit front, recycling dry etching technology is from front etch silicon substrate, release sensor three-dimensional device structures, achieve the single-chip integration of thermopile sensor and signal processing circuit, CMOS technology is adopted thermopile detector and signal processing circuit to be produced in the middle of same chip.
Description
Technical field
The present invention relates to a kind of integrated thermal electric based on CMOS technology heap IRDS and preparation method thereof, especially a kind of thermopile infrared detection system based on MEMS sensor and cmos signal treatment circuit and preparation method thereof, belongs to infrared detection technique field.
Background technology
Infrared Detectors is one of element of most critical in infrared system.Thermopile IR detector is a kind of non-refrigeration type Infrared Detectors of comparatively early development, and its operation principle is based on Seebeck effect, and namely the temperature contrast of two kinds of different electric conductors or semi-conducting material causes producing voltage difference between bi-material.Due to thermopile IR detector have volume little, can room temperature operation, the response of wide range infra-red radiation, constant radiant amount can be detected, and the advantage such as preparation cost is low, be widely used in security monitoring, therapeutic treatment, life detection etc.
Thermocouple deposition of material obtains by early stage thermopile IR temperature sensor on plastics or alumina substrate, and the device size that this method obtains is large, not easily produces in batches.Along with the application of MEMS technology, there is micro mechanical thermopile infrared temperature sensor.The micro mechanical thermopile infrared temperature sensor adopting MEMS technology to make is owing to effectively can reducing its heat transfer, improving integrated level, and Performance Ratio Conventional thermoelectric heap device has and promotes by a relatively large margin.Along with the development of MEMS technology, various MEMS infrared temperature sensor starts to show up prominently.But the many employings of its process corrosion technology dorsad, needs double-sided alignment photoetching, high to equipment requirement, method complicated and with standard CMOS process poor compatibility, be unfavorable for realizing sensor and signal processing circuit single-chip integration.
Due to the similitude of MEMS and CMOS technology, how thermopile sensor and signal processing circuit being realized single-chip integration is the other direction that researchers pay close attention to.Along with IC(integrated circuit) development of technique, technological level continues to improve, characteristic size constantly declines, a kind of method of low cost and high reliability is provided to the making of the integrated Infrared Detectors of thermoelectric pile, the thermopile detector ratio simultaneously made by standard CMOS process is easier to signal processing circuit integrated, be produced in the middle of same chip, improve detector output signal quality, realize sensing system microminiaturized and intelligent.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of integrated thermal electric based on CMOS technology is provided to pile IRDS and preparation method thereof, achieve the single-chip integration of thermopile sensor and signal processing circuit, adopt CMOS technology thermopile detector and signal processing circuit to be produced in the middle of same chip.
According to technical scheme provided by the invention, the described heap of the integrated thermal electric based on CMOS technology IRDS, comprise silicon base and be positioned at the structure sheaf in silicon base, it is characterized in that: described silicon base and structure sheaf are made up of signal processing circuit region and sensor unit;
In described signal processing circuit region, on described silicon base, photoetching forms N trap, structure sheaf in silicon base is upwards followed successively by field oxide, second dielectric layer, the 3rd dielectric layer and the 4th dielectric layer from bottom, first signal processing circuit metal level is set between second dielectric layer and the 3rd dielectric layer, secondary signal treatment circuit metal level is set between the 3rd dielectric layer and the 4th dielectric layer, the 3rd signal processing circuit metal level is set on the surface of the 4th dielectric layer; Described field oxide is provided with PMOS area and NMOS area, sets gradually gate oxide respectively in the bottom of PMOS area and NMOS area and signal processing circuit polysilicon layer arranges the first through hole and the second through hole respectively in described second dielectric layer and the 3rd dielectric layer;
In described sensor unit, structure sheaf in silicon base is upwards followed successively by first medium layer, second dielectric layer, the 3rd dielectric layer and the 4th dielectric layer from bottom, sensor polysilicon layer is set between first medium layer and second dielectric layer, between second dielectric layer and the 3rd dielectric layer, the first metal layer is set, arrange the second metal level between 3rd dielectric layer and the 4th dielectric layer, the surface of the 4th dielectric layer arranges the 3rd metal level; Third through-hole is set in described second dielectric layer, fourth hole is set in the 3rd dielectric layer; Structure sheaf in described silicon base arranges release aperture, and release aperture extends to the upper surface of silicon base by the 3rd metal level; In silicon base below described release aperture, etching forms cavity.
Described N trap is extended to the lower surface of silicon base by the upper surface of silicon base, and the degree of depth of N trap is less than the thickness of silicon base, and the width of N trap is less than the width of the silicon base in signal processing circuit region.
Described cavity is extended to the lower surface of silicon base by the upper surface of silicon base, and the degree of depth of cavity is less than the thickness of silicon base, and the width of cavity is less than the width of the silicon base of sensor unit.
Silica is filled in described PMOS area and NMOS area.
Tungsten plug is set in described first through hole and connects the first signal processing circuit metal level and signal processing circuit polysilicon layer, tungsten plug is set in the second through hole and connects the first signal processing circuit metal level and secondary signal treatment circuit metal level, tungsten plug connecting sensor polysilicon layer and the first metal layer are set in third through-hole, tungsten plug are set in fourth hole and connect the first metal layer and the second metal level.
Described first medium layer comprises silicon oxide layer and silicon nitride layer.
The preparation method of the described heap of the integrated thermal electric based on CMOS technology IRDS, is characterized in that, comprise following processing step:
(1) select the silicon chip in (100) crystal orientation as silicon base, oxidation growth a layer thickness is the silica of 0.5 μm on a silicon substrate, and photoetching forms N trap on a silicon substrate, and carries out ion implantation phosphorus at N trap;
(2) thermal oxide growth obtains silicon oxide layer on a silicon substrate, and dielectric material is SiO
2;
(3) adopt Low Pressure Chemical Vapor Deposition (LPCVD) deposit silicon nitride layer, material is Si
3n
4; At silicon nitride layer surface spin coating photoresist, photoresist opening figure is formed on a photoresist by photoetching process, then utilize reactive ion etching (RIE) technique to etch away silicon nitride layer below opening figure and silicon oxide layer, form etching cavity in signal processing circuit region;
(4) thermal oxide growth field oxide in the etching cavity formed in step (3);
(5) adopt reactive ion etching process etching to remove silicon nitride layer and the silicon oxide layer in signal processing circuit region, formation PMOS injects window and NMOS injects window;
(6) window and NMOS injection window thermal oxide growth gate oxide is injected at PMOS;
(7) using plasma strengthens chemical vapour deposition (CVD) (PECVD) technique depositing polysilicon, and carries out ion implantation phosphorus; Chemical wet etching is carried out to polysilicon, the gate oxide in signal processing circuit region is formed signal processing circuit polysilicon layer, and form sensor polysilicon layer on the silicon nitride layer of sensor unit;
(8) region except PMOS injection window is protected with photoresist, inject window to PMOS and inject boron ion, form PMOS area;
(9) region except NMOS injection window is protected with photoresist, inject window to NMOS and inject phosphonium ion, form NMOS area;
(10) adopt LPCVD technique deposition of second dielectric layer, dielectric material is SiO
2; And make to fill SiO in the cavity of PMOS area and NMOS area
2;
(11) at second dielectric layer surface spin coating photoresist, form photoresist opening on a photoresist by photoetching process, then utilize RIE technique to etch away SiO below opening figure
2, the second dielectric layer in signal processing circuit region is formed the first through hole, the second dielectric layer of sensor unit forms third through-hole, in the first through hole and third through-hole, fill tungsten plug;
(12) at second dielectric layer surface deposition metallic aluminium, and chemical wet etching is adopted to form the first signal processing circuit metal level in signal processing circuit region and the first metal layer of sensor unit;
(13) LPCVD technique deposit SiO is adopted
2, obtain the 3rd dielectric layer; At the 3rd dielectric layer surface spin coating photoresist, form photoresist opening on a photoresist by photoetching process, then utilize RIE technique to etch away SiO below opening figure
2, the 3rd dielectric layer in signal processing circuit region forms the second through hole, the 3rd dielectric layer of sensor unit forms fourth hole, in the second through hole and fourth hole, fills tungsten plug;
(14) at the 3rd dielectric layer surface depositing metal aluminium, and chemical wet etching is adopted to form the secondary signal treatment circuit metal level in signal processing circuit region and the second metal level of sensor unit;
(15) LPCVD technique deposit SiO is adopted
2, obtain the 4th layer of medium;
(16) at the 4th dielectric layer surface depositing metal aluminium, form the 3rd signal processing circuit metal level at the 4th dielectric layer surface in signal processing circuit region, form the 3rd metal level at the 4th dielectric layer surface of sensor unit; 3rd metal level of sensor unit adopt chemical wet etching form corrosion opening;
(17) adopt anisotropic rie except the SiO below corrosion removal opening
2and Si
3n
4, until arrive the upper surface of silicon base, thus structure sheaf on a silicon substrate forms the release aperture perpendicular to silicon base;
(18) adopt isotropic reactive ion etching by release aperture, the silicon base under release aperture forms cavity.
The present invention has the following advantages: (1) IRDS of the present invention can be divided into thermopile IR detector and cmos signal treatment circuit two parts, the present invention takes into full account and achieves the processing compatibility of thermopile sensor and signal processing circuit, from Material selec-tion, structural design, the aspects such as process sequences are improved; (2) present invention improves over the compatibility of MEMS thermopile sensor and cmos signal treatment circuit, adopt CMOS technology integrated thermal electric heap Infrared Detectors and cmos signal treatment circuit completely, by corrosion opening well-designed in sensor unit front, recycling dry etching technology, from front etch silicon substrate, discharges sensor three-dimensional device structures; Dry etching has well selective, selects XeF
2as working gas, can an etch silicon substrate and minimum to the material corrosion such as aluminium, polysilicon speed; (3) the present invention adopts material metal Al/ polysilicon the most frequently used in CMOS technology to form thermocouple.
Accompanying drawing explanation
Fig. 1 is the block diagram of integrated thermal electric of the present invention heap IRDS.
Fig. 2 is the profile of integrated thermal electric of the present invention heap IRDS.
Fig. 3 ~ Figure 20 is manufacturing process flow diagram of the present invention, wherein:
Fig. 3 is the schematic diagram obtaining N trap.
Fig. 4 is the schematic diagram obtaining silicon oxide layer.
Fig. 5 is the schematic diagram obtaining silicon nitride layer.
Fig. 6 is the schematic diagram obtaining field oxide.
Fig. 7 obtains the schematic diagram that PMOS injects window and NMOS injection window.
Fig. 8 is the schematic diagram obtaining gate oxide.
Fig. 9 is the schematic diagram obtaining signal processing circuit polysilicon layer and sensor polysilicon layer.
Figure 10 is the schematic diagram obtaining PMOS area.
Figure 11 is the schematic diagram obtaining NMOS area.
Figure 12 is the schematic diagram obtaining second dielectric layer.
Figure 13 is the schematic diagram obtaining the first through hole and third through-hole.
Figure 14 is the schematic diagram obtaining the first signal processing circuit metal level and the first metal layer.
Figure 15 is the schematic diagram obtaining the 3rd dielectric layer, the second through hole and fourth hole.
Figure 16 is the schematic diagram obtaining secondary signal treatment circuit metal level and the second metal level.
Figure 17 is the schematic diagram obtaining the 4th dielectric layer.
Figure 18 is the schematic diagram obtaining the 3rd signal processing circuit metal level, the 3rd metal level.
Figure 19 is the schematic diagram forming release aperture.
Figure 20 is the schematic diagram forming cavity.
Described signal processing circuit region A comprises silicon base 1, signal processing circuit polysilicon layer 4-1, the first signal processing circuit metal level 5-1, secondary signal treatment circuit metal level 5-2, the 3rd signal processing circuit metal level 5-3, second dielectric layer 3-2, the 3rd dielectric layer 3-3, the 4th dielectric layer 3-4, the first through hole 8-1, second through hole 8-2, N trap 13, PMOS area 13-1, NMOS area 13-2, field oxide 15, gate oxide 16;
Described sensor unit B comprises silicon base 1, cavity 2, first medium layer 3-1, second dielectric layer 3-2, the 3rd dielectric layer 3-3, the 4th dielectric layer 3-4, sensor polysilicon layer 4-1 ', the first metal layer 5-1 ', the second metal level 5-2 ', the 3rd metal level 5-3 ', third through-hole 8-3, fourth hole 8-4, release aperture 9.
Detailed description of the invention
Below in conjunction with concrete accompanying drawing, the invention will be further described.
As shown in Figure 2: the structure sheaf that the described heap of the integrated thermal electric based on CMOS technology IRDS comprises silicon base 1 and is positioned in silicon base 1, silicon base 1 and structure sheaf are made up of signal processing circuit region A and sensor unit B;
As shown in figure 20, in described signal processing circuit region A, structure sheaf in silicon base 1 is upwards followed successively by field oxide 15, second dielectric layer 3-2, the 3rd dielectric layer 3-3 and the 4th dielectric layer 3-4 from bottom, first signal processing circuit metal level 5-1 is set between second dielectric layer 3-2 and the 3rd dielectric layer 3-3, secondary signal treatment circuit metal level 5-2 is set between the 3rd dielectric layer 3-3 and the 4th dielectric layer 3-4, the 3rd signal processing circuit metal level 5-3 is set on the surface of the 4th dielectric layer 3-4; Described field oxide 15 is provided with PMOS area 13-1 and NMOS area 13-2, set gradually gate oxide 16 and signal processing circuit polysilicon layer 4-1 in the bottom of PMOS area 13-1 and NMOS area 13-2 respectively, in PMOS area 13-1 and NMOS area 13-2, fill silica; Described second dielectric layer 3-2 and the 3rd dielectric layer 3-3 arrange the first through hole 8-1 and the second through hole 8-2 respectively, tungsten plug is set in the first through hole 8-1 and connects the first signal processing circuit metal level 5-1 and signal processing circuit polysilicon layer 4-1, tungsten plug is set in the second through hole 8-2 and connects the first signal processing circuit metal level 5-1 and secondary signal treatment circuit metal level 5-2; On described silicon base 1, photoetching forms N trap 13, N trap 13 and is extended to the lower surface of silicon base 1 by the upper surface of silicon base 1, and the degree of depth of N trap 13 is less than the thickness of silicon base 1, and the width of N trap 13 is less than the width of the silicon base 1 of signal processing circuit region A;
As shown in figure 20, in described sensor unit B, structure sheaf in silicon base 1 is upwards followed successively by first medium layer 3-1, second dielectric layer 3-2, the 3rd dielectric layer 3-3 and the 4th dielectric layer 3-4 from bottom, sensor polysilicon layer 4-1 ' is set between first medium layer 3-1 and second dielectric layer 3-2, between second dielectric layer 3-2 and the 3rd dielectric layer 3-3, the first metal layer 5-1 ' is set, arrange the second metal level 5-2 ' between 3rd dielectric layer 3-3 and the 4th dielectric layer 3-4, the surface of the 4th dielectric layer 3-4 arranges the 3rd metal level 5-3 '; Third through-hole 8-3 is set in described second dielectric layer 3-2, in the 3rd dielectric layer 3-3, fourth hole 8-4 is set, tungsten plug connecting sensor polysilicon layer 4-1 ' and the first metal layer 5-1 ' is set in third through-hole 8-3, tungsten plug is set in fourth hole 8-4 and connects the first metal layer 5-1 ' and the second metal level 5-2 '; Structure sheaf in the silicon base 1 of described sensor unit B arranges release aperture 9, and release aperture 9 extends to the upper surface of silicon base 1 by the 3rd metal level 5-3 '; In silicon base 1 below described release aperture 9, etching forms cavity 2, cavity 2 is extended to the lower surface of silicon base 1 by the upper surface of silicon base 1, and the degree of depth of cavity 2 is less than the thickness of silicon base 1, the width of cavity 2 is less than the width of the silicon base 1 of sensor unit B;
The signal of telecommunication of described sensor unit B is drawn by the first metal layer 5-1 ', the second metal level 5-2 ' and is connected with signal processing circuit;
As shown in figure 20, described first medium layer 3-1 comprises silicon oxide layer 3-1-1 and silicon nitride layer 3-1-2.
Homogeneous radiation is when thermopile sensor surface, thermoelectric pile thermojunction district is different from cold junction district ascending temperature, formation temperature difference Δ T=T1-T2 between the temperature T1 in thermojunction district and the temperature T2 in cold junction district, be Vout=(T1-T2 from the output voltage of the first metal layer 5-1 ' and the second metal level 5-2 ') (S1-S2), wherein S1, S2 are respectively the Seebeck coefficient of polysilicon and metallic aluminium.
Integrated thermal electric based on CMOS technology heap IRDS of the present invention adopts standard CMOS process in preparation method, and thermopile detector and signal processing circuit make simultaneously, and main technological steps comprises:
(1) select the P+ silicon chip in (100) crystal orientation as silicon base 1, resistivity is 10 Ω cm, and oxidation growth thickness is the silica of 0.5 μm on a silicon substrate 1, and photoetching forms N trap 13 on a silicon substrate 1, and carries out ion implantation phosphorus at N trap 13, and dosage is 2E12cm
-2, energy is 70keV, and well region advances, and junction depth is 6 μm (as shown in Figure 3); The object of this step forms N trap 13 in cmos signal treatment circuit a-quadrant, do not affect sensor unit B region;
(2) as shown in Figure 4, thermal oxide growth obtains silicon oxide layer 3-1-1 on a silicon substrate 1, and dielectric material is SiO
2, thickness is 5000, and oxidizing temperature is 950 DEG C, and the content of oxygen is 60%;
(3) as shown in Figure 5, employing Low Pressure Chemical Vapor Deposition (LPCVD) deposition thickness is the silicon nitride layer 3-1-2 of 2000, and material is Si
3n
4; At silicon nitride layer 3-1-2 surface spin coating photoresist, photoresist opening figure is formed on a photoresist by photoetching process, then utilize reactive ion etching (RIE) technique to etch away silicon nitride layer 3-1-2 below opening figure and silicon oxide layer 3-1-1, form etching cavity at signal processing circuit region A; Radio-frequency power when described RIE etching is 150W, and pressure is 400mTorr, and etching gas is CHF
3, He and SF
6mist, flow is respectively 7sccm, 100sccm and 30sccm;
(4) as shown in Figure 6, in the etching cavity that step (3) is formed, thermal oxide growth thickness is the field oxide 15 of 0.7 μm, and oxidizing temperature is 950 DEG C, and the content of oxygen is 60%;
(5) as shown in Figure 7, adopt reactive ion etching process etching to remove silicon nitride layer 3-1-2 and the silicon oxide layer 3-1-1 of signal processing circuit region A, form PMOS injection window 13-1 ' and NMOS and inject window 13-2 '; Radio-frequency power during etching is 150W, and pressure is 400mTorr, and etching gas is CHF
3, He and SF
6mist, flow is respectively 7 sccm, 100 sccm and 30sccm;
(6) as shown in Figure 8, the PMOS formed after step (5) etching injects window 13-1 ' and NMOS and injects the gate oxide 16 that window 13-2 ' thermal oxide growth a layer thickness is 0.15 μm, and oxidizing temperature is 950 DEG C, and the content of oxygen is 60%;
(7) as shown in Figure 9, using plasma strengthens chemical vapour deposition (CVD) (PECVD) technique depositing polysilicon, and thickness is 0.9 μm, and carries out ion implantation phosphorus, and dosage is 6E15cm
-2, energy is 100keV; Chemical wet etching is carried out to polysilicon, the gate oxide 16 of signal processing circuit region A is formed signal processing circuit polysilicon layer 4-1, and form sensor polysilicon layer 4-1 ' on the silicon nitride layer 3-1-2 of sensor unit B;
(8) as shown in Figure 10, protected with photoresist in the region except injecting window 13-1 ' except PMOS, inject window 13-1 ' to PMOS and inject boron ion, dosage is 10E15cm
-2, energy is 70keV, forms PMOS area 13-1;
(9) as shown in figure 11, protected with photoresist in the region except injecting window 13-2 ' except NMOS, inject window 13-2 ' to NMOS and inject phosphonium ion, dosage is 8E15cm
-2, energy is 70keV, forms NMOS area 13-2;
(10) as shown in figure 12, adopt LPCVD technique deposition of second dielectric layer 3-2, dielectric material is SiO
2, thickness is 1 μm, and temperature during deposit is 620 DEG C, and pressure is 200mTorr(millitorr), SiH
4flow be 130sccm; And make to fill SiO in the cavity of PMOS area 13-1 and NMOS area 13-2
2;
(11) as shown in figure 13, at second dielectric layer 3-2 surface spin coating photoresist, form photoresist opening on a photoresist by photoetching process, then utilize RIE technique to etch away SiO below opening figure
2the second dielectric layer 3-2 of signal processing circuit region A is formed the first through hole 8-1, the second dielectric layer 3-2 of sensor unit B is formed third through-hole 8-3, in the first through hole 8-1 and third through-hole 8-3, fills tungsten plug, for realizing the electrical connection between upper and lower materials at two layers; Radio-frequency power during described RIE etching is 150W, and pressure is 400mTorr, and etching gas is CHF
3, He and SF
6mist, flow is respectively 7sccm, 100sccm and 30sccm;
(12) as shown in figure 14, at second dielectric layer 3-2 surface deposition metallic aluminium, thickness is 0.4 μm, and adopts chemical wet etching to form the first signal processing circuit metal level 5-1 of signal processing circuit region A and the first metal layer 5-1 ' of sensor unit B;
(13) LPCVD technique deposit SiO as shown in figure 15, is adopted
2, obtain the 3rd dielectric layer 3-3 that thickness is 0.8 μm; At the 3rd dielectric layer 3-3 surface spin coating photoresist, form photoresist opening on a photoresist by photoetching process, then utilize RIE technique to etch away SiO below opening figure
2the 3rd dielectric layer 3-3 of signal processing circuit region A forms the second through hole 8-2, the 3rd dielectric layer 3-3 of sensor unit B forms fourth hole 8-4, in the second through hole 8-2 and fourth hole 8-4, fills tungsten plug, for realizing the electrical connection between upper and lower materials at two layers; Radio-frequency power during described RIE etching is 150W, and pressure is 400mTorr, and etching gas is CHF
3, He and SF
6mist, flow is respectively 7sccm, 100sccm and 30sccm;
(14) as shown in figure 16, at the 3rd dielectric layer 3-3 surface deposition metallic aluminium, thickness is 0.4 μm, and adopts chemical wet etching to form the secondary signal treatment circuit metal level 5-2 of signal processing circuit region A and the second metal level 5-2 ' of sensor unit B;
(15) LPCVD technique deposit SiO as shown in figure 17, is adopted
2, obtain the 4th layer of medium 3-4 that thickness is 1 μm;
(16) as shown in figure 18, at the 4th dielectric layer 3-4 surface deposition 0.4 μm of metallic aluminium, form the 3rd signal processing circuit metal level 5-3 on the 4th dielectric layer 3-4 surface of signal processing circuit region A, form the 3rd metal level 5-3 ' on the 4th dielectric layer 3-4 surface of sensor unit B; Corrosion opening 6 is formed at the upper chemical wet etching that adopts of the 3rd metal level 5-3 ' of sensor unit B;
(17) as shown in figure 19, CHF is utilized
3anisotropic rie is carried out except the SiO below corrosion removal opening 6 with He mist
2and Si
3n
4, until arrive the upper surface of silicon base 1, thus structure sheaf on a silicon substrate 1 forms the release aperture 9 perpendicular to silicon base; Described etch rate is 1000 ~ 2000/min, and etch period is 10min, CHF
360sccm, 50sccm is respectively with the gas flow of He;
(18) as shown in figure 20, XeF is used by release aperture 9
2and O
2mist carries out isotropic reactive ion etching, and the silicon base 1 under release aperture 9 forms cavity 2; Wherein, the content of oxygen is 30%, and etching temperature is 550 DEG C, and power is 150W, and pressure is 400mTorr, XeF
2and O
2gas flow be respectively 100sccm, 30sccm.
As shown in Figure 1, integrated thermal electric heap IRDS of the present invention is by integrated to thermopile sensor 100 and signal processing circuit, and signal processing circuit comprises for the chopper amplifier 200 of pickup ultra-weak electronic signal, for analog-to-digital sigma-delta a/d converter 300, digital signal processing unit 400 and the local temperature sensing unit 500 for measuring silicon base absolute temperature.
Claims (6)
1. the heap of the integrated thermal electric based on a CMOS technology IRDS, the structure sheaf comprising silicon base (1) and be positioned in silicon base (1), is characterized in that: described silicon base (1) and structure sheaf are made up of signal processing circuit region (A) and sensor unit (B);
In described signal processing circuit region (A), the upper photoetching of described silicon base (1) forms N trap (13), structure sheaf in silicon base (1) is upwards followed successively by field oxide (15) from bottom, second dielectric layer (3-2), 3rd dielectric layer (3-3) and the 4th dielectric layer (3-4), first signal processing circuit metal level (5-1) is set between second dielectric layer (3-2) and the 3rd dielectric layer (3-3), between the 3rd dielectric layer (3-3) and the 4th dielectric layer (3-4), secondary signal treatment circuit metal level (5-2) is set, on the surface of the 4th dielectric layer (3-4), the 3rd signal processing circuit metal level (5-3) is set, described field oxide (15) is provided with PMOS area (13-1) and NMOS area (13-2), sets gradually gate oxide (16) and signal processing circuit polysilicon layer (4-1) respectively in the bottom of PMOS area (13-1) and NMOS area (13-2), described second dielectric layer (3-2) and the 3rd dielectric layer (3-3) arrange the first through hole (8-1) and the second through hole (8-2) respectively,
In described sensor unit (B), structure sheaf in silicon base (1) is upwards followed successively by first medium layer (3-1) from bottom, second dielectric layer (3-2), 3rd dielectric layer (3-3) and the 4th dielectric layer (3-4), sensor polysilicon layer (4-1 ') is set between first medium layer (3-1) and second dielectric layer (3-2), the first metal layer (5-1 ') is set between second dielectric layer (3-2) and the 3rd dielectric layer (3-3), second metal level (5-2 ') is set between the 3rd dielectric layer (3-3) and the 4th dielectric layer (3-4), the surface of the 4th dielectric layer (3-4) arranges the 3rd metal level (5-3 '), third through-hole (8-3) is set in described second dielectric layer (3-2), fourth hole (8-4) is set in the 3rd dielectric layer (3-3), structure sheaf in described silicon base (1) is arranged release aperture (9), release aperture (9) extends to the upper surface of silicon base (1) by the 3rd metal level (5-3 '), cavity (2) is formed in the upper etching of the silicon base (1) of described release aperture (9) below,
Tungsten plug is set in described first through hole (8-1) and connects the first signal processing circuit metal level (5-1) and signal processing circuit polysilicon layer (4-1), tungsten plug is set in the second through hole (8-2) and connects the first signal processing circuit metal level (5-1) and secondary signal treatment circuit metal level (5-2), tungsten plug connecting sensor polysilicon layer (4-1 ') and the first metal layer (5-1 ') are set in third through-hole (8-3), tungsten plug are set in fourth hole (8-4) and connect the first metal layer (5-1 ') and the second metal level (5-2 ').
2. as claimed in claim 1 based on the integrated thermal electric heap IRDS of CMOS technology, it is characterized in that: described N trap (13) is extended to the lower surface of silicon base (1) by the upper surface of silicon base (1), and the degree of depth of N trap (13) is less than the thickness of silicon base (1), the width of N trap (13) is less than the width of the silicon base (1) of signal processing circuit region (A).
3. as claimed in claim 1 based on the integrated thermal electric heap IRDS of CMOS technology, it is characterized in that: described cavity (2) is extended to the lower surface of silicon base (1) by the upper surface of silicon base (1), and the degree of depth of cavity (2) is less than the thickness of silicon base (1), the width of cavity (2) is less than the width of the silicon base (1) of sensor unit (B).
4., as claimed in claim 1 based on the integrated thermal electric heap IRDS of CMOS technology, it is characterized in that: in described PMOS area (13-1) and NMOS area (13-2), fill silica.
5., as claimed in claim 1 based on the integrated thermal electric heap IRDS of CMOS technology, it is characterized in that: described first medium layer (3-1) comprises silicon oxide layer (3-1-1) and silicon nitride layer (3-1-2).
6., based on a preparation method for the integrated thermal electric heap IRDS of CMOS technology, it is characterized in that, comprise following processing step:
(1) select the silicon chip in (100) crystal orientation as silicon base (1), be the silica of 0.5 μm in the upper oxidation growth a layer thickness of silicon base (1), form N trap (13) in the upper photoetching of silicon base (1), and carry out ion implantation phosphorus at N trap (13);
(2) obtain silicon oxide layer (3-1-1) at the upper thermal oxide growth of silicon base (1), dielectric material is SiO
2;
(3) adopt Low Pressure Chemical Vapor Deposition (LPCVD) deposit silicon nitride layer (3-1-2), material is Si
3n
4; At the surperficial spin coating photoresist of silicon nitride layer (3-1-2), photoresist opening figure is formed on a photoresist by photoetching process, then utilize reactive ion etching (RIE) technique to etch away silicon nitride layer (3-1-2) below opening figure and silicon oxide layer (3-1-1), in signal processing circuit region, (A) forms etching cavity;
(4) thermal oxide growth field oxide (15) in the etching cavity formed in step (3);
(5) employing reactive ion etching process etching removes silicon nitride layer (3-1-2) and the silicon oxide layer (3-1-1) in signal processing circuit region (A), formation PMOS injection window (13-1 ') and NMOS injection window (13-2 ');
(6) window (13-1 ') and NMOS injection window (13-2 ') thermal oxide growth gate oxide (16) is injected at PMOS;
(7) using plasma strengthens chemical vapour deposition (CVD) (PECVD) technique depositing polysilicon, and carries out ion implantation phosphorus; Chemical wet etching is carried out to polysilicon, form signal processing circuit polysilicon layer (4-1) the gate oxide (16) of signal processing circuit region (A) is upper, and form sensor polysilicon layer (4-1 ') the silicon nitride layer (3-1-2) of sensor unit (B) is upper;
(8) region except injecting window (13-1 ') except PMOS is protected with photoresist, inject window (13-1 ') to PMOS and inject boron ion, formation PMOS area (13-1);
(9) region except injecting window (13-2 ') except NMOS is protected with photoresist, inject window (13-2 ') to NMOS and inject phosphonium ion, formation NMOS area (13-2);
(10) adopt LPCVD technique deposition of second dielectric layer (3-2), dielectric material is SiO
2; And make to fill SiO in the cavity of PMOS area (13-1) and NMOS area (13-2)
2;
(11) at the surperficial spin coating photoresist of second dielectric layer (3-2), form photoresist opening on a photoresist by photoetching process, then utilize RIE technique to etch away SiO below opening figure
2at upper formation first through hole (8-1) of the second dielectric layer (3-2) of signal processing circuit region (A), the second dielectric layer (3-2) of sensor unit (B) forms third through-hole (8-3), in the first through hole (8-1) and third through-hole (8-3), fills tungsten plug;
(12) at second dielectric layer (3-2) surface deposition metallic aluminium, and chemical wet etching is adopted to form the first signal processing circuit metal level (5-1) in signal processing circuit region (A) and the first metal layer (5-1 ') of sensor unit (B);
(13) LPCVD technique deposit SiO is adopted
2, obtain the 3rd dielectric layer (3-3); At the surperficial spin coating photoresist of the 3rd dielectric layer (3-3), form photoresist opening on a photoresist by photoetching process, then utilize RIE technique to etch away SiO below opening figure
2at upper formation second through hole (8-2) of the 3rd dielectric layer (3-3) of signal processing circuit region (A), 3rd dielectric layer (3-3) of sensor unit (B) forms fourth hole (8-4), in the second through hole (8-2) and fourth hole (8-4), fills tungsten plug;
(14) at the 3rd dielectric layer (3-3) surface deposition metallic aluminium, and chemical wet etching is adopted to form the secondary signal treatment circuit metal level (5-2) in signal processing circuit region (A) and second metal level (5-2 ') of sensor unit (B);
(15) LPCVD technique deposit SiO is adopted
2, obtain the 4th layer of medium (3-4);
(16) at the 4th dielectric layer (3-4) surface deposition metallic aluminium, form the 3rd signal processing circuit metal level (5-3) on the 4th dielectric layer (3-4) surface of signal processing circuit region (A), form the 3rd metal level (5-3 ') on the 4th dielectric layer (3-4) surface of sensor unit (B); Corrosion opening (6) is formed at the upper chemical wet etching that adopts of the 3rd metal level (5-3 ') of sensor unit (B);
(17) adopt anisotropic rie except the SiO of corrosion removal opening (6) below
2and Si
3n
4, until arrive the upper surface of silicon base (1), thus the structure sheaf in silicon base (1) forms the release aperture (9) perpendicular to silicon base;
(18) adopt isotropic reactive ion etching by release aperture (9), the silicon base (1) under release aperture (9) forms cavity (2).
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