CN103342332A - Integrated thermopile infrared detection system based on CMOS process and manufacturing method thereof - Google Patents
Integrated thermopile infrared detection system based on CMOS process and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to an integrated thermopile infrared detection system based on the CMOS process and a manufacturing method of the integrated thermopile infrared detection system. The integrated thermopile infrared detection system is divided into the two parts including a thermopile infrared detector and a CMOS signal processing circuit, and the compatibility between an MEMS thermopile sensor and the CMOS signal processing circuit is improved. The thermopile infrared detector and the CMOS signal processing circuit are completely integrated through the CMOS process. A corrosion opening is well designed in the front face of a sensor unit, then a silicon substrate is etched in the front face through the dry etching technology, the three-dimensional device structure of a unit is released, and monolithic integration between the thermopile sensor and the signal processing circuit is achieved. According to the CMOS process, the thermopile detector and the signal processing circuit are integrated into one chip.
Description
Technical field
The present invention relates to a kind of integrated thermal electric based on CMOS technology and pile IRDS and preparation method thereof, especially a kind of thermopile infrared detection system based on MEMS sensor and cmos signal treatment circuit and preparation method thereof belongs to the infrared detection technique field.
Background technology
Infrared Detectors is one of element of most critical in the infrared system.Thermopile IR detector is a kind of non-refrigeration type Infrared Detectors of development early, and its operation principle is based on Seebeck effect, and namely the temperature contrast of two kinds of different electric conductors or semi-conducting material causes producing voltage difference between two kinds of materials.Since thermopile IR detector have volume little, can work under the room temperature, wide range infra-red radiation response, can detect constant amount of radiation, and advantage such as preparation cost is low is widely used at aspects such as security monitoring, therapeutic treatment, life detections.
Early stage thermoelectric pile infrared temperature sensor is deposited on the thermocouple material on plastics or the alumina substrate and obtains, and the device size that this method obtains is big, is difficult for producing in batches.Along with the MEMS The Application of Technology, the micro mechanical thermopile infrared temperature sensor has appearred.Adopt the micro mechanical thermopile infrared temperature sensor of MEMS technology making and conduct, improve integrated level owing to can effectively reduce its heat, performance has lifting by a relatively large margin than traditional hot pile device.Along with the development of MEMS technology, various MEMS infrared temperature sensors begin to show up prominently.But its process adopts corrosion technology dorsad more, needs the double-sided alignment photoetching, equipment is required high, method complicated and with the standard CMOS process poor compatibility, be unfavorable for realizing that sensor and signal processing circuit monolithic are integrated.
Because how the similitude of MEMS and CMOS technology realizes the other direction that the integrated researchers of being of monolithic pay close attention to thermopile sensor and signal processing circuit.Along with IC(integrated circuit) the continuous development of technology, technological level continues to improve, characteristic size constantly descends, the method of a kind of low cost and high reliability is provided to the making of the integrated Infrared Detectors of thermoelectric pile, the thermopile detector ratio of making by standard CMOS process is easier to signal processing circuit integrated simultaneously, be produced on in the middle of the chip piece, improve the detector output signal quality, realize that sensing system is microminiaturized and intelligent.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, provide a kind of integrated thermal electric based on CMOS technology to pile IRDS and preparation method thereof, the monolithic of having realized thermopile sensor and signal processing circuit is integrated, adopts CMOS technology that thermopile detector and signal processing circuit are produced on in the middle of the chip piece.
According to technical scheme provided by the invention, described integrated thermal electric heap IRDS based on CMOS technology, comprise silicon base and the structure sheaf that is positioned on the silicon base, it is characterized in that: described silicon base and structure sheaf are made up of signal processing circuit zone and sensor unit;
In described signal processing circuit zone, photoetching forms the N trap on described silicon base, structure sheaf on the silicon base upwards is followed successively by field oxide, second dielectric layer, the 3rd dielectric layer and the 4th dielectric layer from bottom, the first signal processing circuit metal level is set between second dielectric layer and the 3rd dielectric layer, secondary signal treatment circuit metal level is set between the 3rd dielectric layer and the 4th dielectric layer, the 3rd signal processing circuit metal level is set on the surface of the 4th dielectric layer; Described field oxide is provided with PMOS zone and nmos area territory, and bottom regional at PMOS and the nmos area territory sets gradually gate oxide respectively and the signal processing circuit polysilicon layer arranges first through hole and second through hole respectively on described second dielectric layer and the 3rd dielectric layer;
In described sensor unit, structure sheaf on the silicon base upwards is followed successively by first dielectric layer, second dielectric layer, the 3rd dielectric layer and the 4th dielectric layer from bottom, between first dielectric layer and second dielectric layer, the sensor polysilicon layer is set, between second dielectric layer and the 3rd dielectric layer, the first metal layer is set, between the 3rd dielectric layer and the 4th dielectric layer second metal level is set, the surface of the 4th dielectric layer arranges the 3rd metal level; In described second dielectric layer, third through-hole is set, in the 3rd dielectric layer, fourth hole is set; Structure sheaf on described silicon base arranges release aperture, and release aperture is extended to the upper surface of silicon base by the 3rd metal level; Etching forms cavity on the silicon base below the described release aperture.
Described N trap is extended by the upper surface of the silicon base lower surface to silicon base, and the degree of depth of N trap is less than the thickness of silicon base, and the width of N trap is less than the width of the silicon base in signal processing circuit zone.
Described cavity is extended by the upper surface of the silicon base lower surface to silicon base, and the degree of depth of cavity is less than the thickness of silicon base, and the width of cavity is less than the width of the silicon base of sensor unit.
In described PMOS zone and nmos area territory, fill silica.
The tungsten plug is set in described first through hole connects the first signal processing circuit metal level and signal processing circuit polysilicon layer, the tungsten plug is set in second through hole connects the first signal processing circuit metal level and secondary signal treatment circuit metal level, the tungsten plug is set in third through-hole connects sensor polysilicon layer and the first metal layer, the tungsten plug is set in fourth hole connects the first metal layer and second metal level.
Described first dielectric layer comprises silicon oxide layer and silicon nitride layer.
Described preparation method of piling IRDS based on the integrated thermal electric of CMOS technology is characterized in that, comprises following processing step:
(1) silicon chip of selecting (100) crystal orientation is as silicon base, and oxidation growth one layer thickness is the silica of 0.5 μ m on silicon base, and photoetching forms the N trap on silicon base, and carries out ion at the N trap and inject phosphorus;
(2) thermal oxide growth obtains silicon oxide layer on silicon base, and dielectric material is SiO
2
(3) adopt Low Pressure Chemical Vapor Deposition (LPCVD) deposit silicon nitride layer, material is Si
3N
4At silicon nitride layer surface spin coating photoresist, form the photoresist opening figure by photoetching process at photoresist, utilize reactive ion etching (RIE) technology to etch away silicon nitride layer and the silicon oxide layer of opening figure below then, form etching cavity in the signal processing circuit zone;
(4) thermal oxide growth field oxide in the etching cavity that step (3) forms;
(5) adopt the reactive ion etching process etching to remove silicon nitride layer and the silicon oxide layer in signal processing circuit zone, form PMOS and inject window and NMOS injection window;
(6) inject window and NMOS injection window thermal oxide growth gate oxide at PMOS;
(7) using plasma strengthens chemical vapour deposition (CVD) (PECVD) technology deposit polysilicon, and carries out ion and inject phosphorus; Polysilicon is carried out chemical wet etching, and the gate oxide in the signal processing circuit zone forms the signal processing circuit polysilicon layer, and forms the sensor polysilicon layer at the silicon nitride layer of sensor unit;
(8) zone except PMOS injects window is protected with photoresist, injected window to PMOS and inject the boron ion, form the PMOS zone;
(9) zone except NMOS injects window is protected with photoresist, injected window to NMOS and inject phosphonium ion, form the nmos area territory;
(10) adopt LPCVD technology deposit second dielectric layer, dielectric material is SiO
2And make in the cavity in PMOS zone and nmos area territory and fill SiO
2
(11) at second dielectric layer surface spin coating photoresist, form the photoresist opening by photoetching process at photoresist, utilize RIE technology to etch away the SiO of opening figure below then
2, form first through hole at second dielectric layer in signal processing circuit zone, form third through-hole at second dielectric layer of sensor unit, in first through hole and third through-hole, fill the tungsten plug;
(12) at the second dielectric layer surface deposition metallic aluminium, and adopt chemical wet etching to form the first signal processing circuit metal level in signal processing circuit zone and the first metal layer of sensor unit;
(13) adopt LPCVD technology deposit SiO
2, obtain the 3rd dielectric layer; At the 3rd dielectric layer surface spin coating photoresist, form the photoresist opening by photoetching process at photoresist, utilize RIE technology to etch away the SiO of opening figure below then
2, form second through hole at the 3rd dielectric layer in signal processing circuit zone, form fourth hole at the 3rd dielectric layer of sensor unit, in second through hole and fourth hole, fill the tungsten plug;
(14) at the 3rd dielectric layer surface deposition metallic aluminium, and adopt chemical wet etching to form the secondary signal treatment circuit metal level in signal processing circuit zone and second metal level of sensor unit;
(15) adopt LPCVD technology deposit SiO
2, obtain the 4th layer of medium;
(16) at the 4th dielectric layer surface deposition metallic aluminium, form the 3rd signal processing circuit metal level on the 4th dielectric layer surface in signal processing circuit zone, form the 3rd metal level on the 4th dielectric layer surface of sensor unit; The 3rd metal level at sensor unit adopts chemical wet etching to form the corrosion opening;
(17) adopt anisotropic rie except the SiO of corrosion removal opening below
2And Si
3N
4, up to the upper surface that arrives silicon base, thereby the structure sheaf on silicon base forms the release aperture perpendicular to silicon base;
(18) adopt the isotropic reactive ion etching by release aperture, the silicon base under release aperture forms cavity.
The present invention has the following advantages: (1) IRDS of the present invention can be divided into thermopile IR detector and cmos signal treatment circuit two parts, the present invention has taken into full account and has realized the processing compatibility of thermopile sensor and signal processing circuit, select from material, structural design, aspects such as process sequences are improved; (2) the present invention has improved the compatibility of MEMS thermopile sensor and cmos signal treatment circuit, adopt CMOS technology integrated thermal electric heap Infrared Detectors and cmos signal treatment circuit fully, by at the positive well-designed corrosion opening of sensor unit, the recycling dry etching technology discharges sensor three-dimension device structure from positive etch silicon substrate; Dry etching has well selective, selects XeF for use
2As working gas, can an etch silicon substrate and minimum to material corrosion speed such as aluminium, polysilicons; (3) the present invention adopts material metal Al/ polysilicon the most frequently used in the CMOS technology to constitute thermocouple.
Description of drawings
Fig. 1 is the block diagram of integrated thermal electric heap IRDS of the present invention.
Fig. 2 is the profile of integrated thermal electric heap IRDS of the present invention.
Fig. 3～Figure 20 is manufacturing process flow diagram of the present invention, wherein:
Fig. 3 is the schematic diagram that obtains the N trap.
Fig. 4 is the schematic diagram that obtains silicon oxide layer.
Fig. 5 is the schematic diagram that obtains silicon nitride layer.
Fig. 6 is the schematic diagram that obtains field oxide.
Fig. 7 obtains the schematic diagram that PMOS injects window and NMOS injection window.
Fig. 8 is the schematic diagram that obtains gate oxide.
Fig. 9 is the schematic diagram that obtains signal processing circuit polysilicon layer and sensor polysilicon layer.
Figure 10 is the schematic diagram that obtains the PMOS zone.
Figure 11 is the schematic diagram that obtains the nmos area territory.
Figure 12 is the schematic diagram that obtains second dielectric layer.
Figure 13 is the schematic diagram that obtains first through hole and third through-hole.
Figure 14 is the schematic diagram that obtains the first signal processing circuit metal level and the first metal layer.
Figure 15 is the schematic diagram that obtains the 3rd dielectric layer, second through hole and fourth hole.
Figure 16 is the schematic diagram that obtains secondary signal treatment circuit metal level and second metal level.
Figure 17 is the schematic diagram that obtains the 4th dielectric layer.
Figure 18 is the schematic diagram that obtains the 3rd signal processing circuit metal level, the 3rd metal level.
Figure 19 is for forming the schematic diagram of release aperture.
Figure 20 is for forming the schematic diagram of cavity.
Described signal processing circuit zone A comprises silicon base 1, signal processing circuit polysilicon layer 4-1, the first signal processing circuit metal level 5-1, secondary signal treatment circuit metal level 5-2, the 3rd signal processing circuit metal level 5-3, the second dielectric layer 3-2, the 3rd dielectric layer 3-3, the 4th dielectric layer 3-4, the first through hole 8-1, the second through hole 8-2, N trap 13, PMOS zone 13-1, nmos area territory 13-2, field oxide 15, gate oxide 16;
Described sensor unit B comprises silicon base 1, cavity 2, the first dielectric layer 3-1, the second dielectric layer 3-2, the 3rd dielectric layer 3-3, the 4th dielectric layer 3-4, sensor polysilicon layer 4-1 ', the first metal layer 5-1 ', the second metal level 5-2 ', the 3rd metal level 5-3 ', third through-hole 8-3, fourth hole 8-4, release aperture 9.
The specific embodiment
The invention will be further described below in conjunction with concrete accompanying drawing.
As shown in Figure 2: described integrated thermal electric heap IRDS based on CMOS technology comprises silicon base 1 and the structure sheaf that is positioned on the silicon base 1, and silicon base 1 and structure sheaf are made up of signal processing circuit zone A and sensor unit B;
As shown in figure 20, in described signal processing circuit zone A, structure sheaf on the silicon base 1 upwards is followed successively by field oxide 15, the second dielectric layer 3-2, the 3rd dielectric layer 3-3 and the 4th dielectric layer 3-4 from bottom, the first signal processing circuit metal level 5-1 is set between the second dielectric layer 3-2 and the 3rd dielectric layer 3-3, secondary signal treatment circuit metal level 5-2 is set between the 3rd dielectric layer 3-3 and the 4th dielectric layer 3-4, the 3rd signal processing circuit metal level 5-3 is set on the surface of the 4th dielectric layer 3-4; Described field oxide 15 is provided with PMOS zone 13-1 and nmos area territory 13-2, bottom at PMOS zone 13-1 and nmos area territory 13-2 sets gradually gate oxide 16 and signal processing circuit polysilicon layer 4-1 respectively, fills silica in PMOS zone 13-1 and nmos area territory 13-2; The first through hole 8-1 and the second through hole 8-2 are set respectively on the described second dielectric layer 3-2 and the 3rd dielectric layer 3-3, the tungsten plug is set among the first through hole 8-1 connects the first signal processing circuit metal level 5-1 and signal processing circuit polysilicon layer 4-1, the tungsten plug is set among the second through hole 8-2 connects the first signal processing circuit metal level 5-1 and secondary signal treatment circuit metal level 5-2; Photoetching forms N trap 13 on described silicon base 1, and N trap 13 is extended by the upper surface of silicon base 1 lower surface to silicon base 1, and the degree of depth of N trap 13 is less than the thickness of silicon base 1, and the width of N trap 13 is less than the width of the silicon base 1 of signal processing circuit zone A;
As shown in figure 20, in described sensor unit B, structure sheaf on the silicon base 1 upwards is followed successively by the first dielectric layer 3-1, the second dielectric layer 3-2, the 3rd dielectric layer 3-3 and the 4th dielectric layer 3-4 from bottom, between the first dielectric layer 3-1 and the second dielectric layer 3-2, sensor polysilicon layer 4-1 ' is set, between the second dielectric layer 3-2 and the 3rd dielectric layer 3-3, the first metal layer 5-1 ' is set, between the 3rd dielectric layer 3-3 and the 4th dielectric layer 3-4 the second metal level 5-2 ' is set, the surface of the 4th dielectric layer 3-4 arranges the 3rd metal level 5-3 '; In the described second dielectric layer 3-2, third through-hole 8-3 is set, in the 3rd dielectric layer 3-3, fourth hole 8-4 is set, the tungsten plug is set among the third through-hole 8-3 connects sensor polysilicon layer 4-1 ' and the first metal layer 5-1 ', the tungsten plug is set among the fourth hole 8-4 connects the first metal layer 5-1 ' and the second metal level 5-2 '; Structure sheaf on the silicon base 1 of described sensor unit B arranges release aperture 9, and release aperture 9 is extended to the upper surface of silicon base 1 by the 3rd metal level 5-3 '; Etching forms cavity 2 on the silicon base 1 below the described release aperture 9, cavity 2 is extended by the upper surface of silicon base 1 lower surface to silicon base 1, and the degree of depth of cavity 2 is less than the thickness of silicon base 1, and the width of cavity 2 is less than the width of the silicon base 1 of sensor unit B;
The signal of telecommunication of described sensor unit B is drawn by the first metal layer 5-1 ', the second metal level 5-2 ' and is connected with signal processing circuit;
As shown in figure 20, the described first dielectric layer 3-1 comprises silicon oxide layer 3-1-1 and silicon nitride layer 3-1-2.
Homogeneous radiation is when the thermopile sensor surface, thermoelectric pile thermojunction district is different with cold junction district ascending temperature, formation temperature difference Δ T=T1-T2 between the temperature T 1 in thermojunction district and the temperature T 2 in cold junction district, be Vout=(T1-T2 from the output voltage of the first metal layer 5-1 ' and the second metal level 5-2 ') (S1-S2), wherein S1, S2 are respectively the Seebeck coefficient of polysilicon and metallic aluminium.
Integrated thermal electric heap IRDS based on CMOS technology of the present invention adopts standard CMOS process in preparation method, and thermopile detector and signal processing circuit are made simultaneously, and the main technique step comprises:
(1) the P+ silicon chip of selecting (100) crystal orientation is as silicon base 1, and resistivity is 10 Ω cm, and oxidation growth thickness is the silica of 0.5 μ m on silicon base 1, and photoetching forms N trap 13 on silicon base 1, and carries out ion at N trap 13 and inject phosphorus, and dosage is 2E12cm
-2, energy is 70keV, well region advances, junction depth be 6 μ m(as shown in Figure 3); The purpose of this step is to form N trap 13 in cmos signal treatment circuit a-quadrant, to the not influence of sensor unit B zone;
(2) as shown in Figure 4, thermal oxide growth obtains silicon oxide layer 3-1-1 on silicon base 1, and dielectric material is SiO
2, thickness is 5000, and oxidizing temperature is 950 ℃, and the content of oxygen is 60%;
(3) as shown in Figure 5, employing Low Pressure Chemical Vapor Deposition (LPCVD) deposition thickness is 2000 silicon nitride layer 3-1-2, and material is Si
3N
4At silicon nitride layer 3-1-2 surface spin coating photoresist, form the photoresist opening figure by photoetching process at photoresist, utilize reactive ion etching (RIE) technology to etch away silicon nitride layer 3-1-2 and the silicon oxide layer 3-1-1 of opening figure below then, A forms etching cavity in the signal processing circuit zone; Radio-frequency power when described RIE etching is 150W, and pressure is 400mTorr, and etching gas is CHF
3, He and SF
6Mist, flow are respectively 7sccm, 100sccm and 30sccm;
(4) as shown in Figure 6, thermal oxide growth thickness is the field oxide 15 of 0.7 μ m in the etching cavity that step (3) forms, and oxidizing temperature is 950 ℃, and the content of oxygen is 60%;
(5) as shown in Figure 7, adopt the reactive ion etching process etching to remove silicon nitride layer 3-1-2 and the silicon oxide layer 3-1-1 of signal processing circuit zone A, form PMOS injection window 13-1 ' and NMOS and inject window 13-2 '; Radio-frequency power during etching is 150W, and pressure is 400mTorr, and etching gas is CHF
3, He and SF
6Mist, flow are respectively 7 sccm, 100 sccm and 30sccm;
(6) as shown in Figure 8, the PMOS that forms after step (5) etching injects window 13-1 ' and NMOS injection window 13-2 ' thermal oxide growth one layer thickness is the gate oxide 16 of 0.15 μ m, and oxidizing temperature is 950 ℃, and the content of oxygen is 60%;
(7) as shown in Figure 9, using plasma strengthens chemical vapour deposition (CVD) (PECVD) technology deposit polysilicon, and thickness is 0.9 μ m, and carries out ion and inject phosphorus, and dosage is 6E15cm
-2, energy is 100keV; Polysilicon is carried out chemical wet etching, at the gate oxide 16 formation signal processing circuit polysilicon layer 4-1 of signal processing circuit zone A, and at the silicon nitride layer 3-1-2 of sensor unit B formation sensor polysilicon layer 4-1 ';
(8) as shown in figure 10, the zone except PMOS injects window 13-1 ' is protected with photoresist, injected window 13-1 ' to PMOS and inject the boron ion, dosage is 10E15cm
-2, energy is 70keV, forms PMOS zone 13-1;
(9) as shown in figure 11, the zone except NMOS injects window 13-2 ' is protected with photoresist, injected window 13-2 ' to NMOS and inject phosphonium ion, dosage is 8E15cm
-2, energy is 70keV, forms nmos area territory 13-2;
(10) as shown in figure 12, adopt the LPCVD technology deposit second dielectric layer 3-2, dielectric material is SiO
2, thickness is 1 μ m, the temperature during deposit is 620 ℃, pressure is the 200mTorr(millitorr), SiH
4Flow be 130sccm; And make in the cavity of PMOS zone 13-1 and nmos area territory 13-2 and fill SiO
2
(11) as shown in figure 13, at second dielectric layer 3-2 surface spin coating photoresist, form the photoresist opening by photoetching process at photoresist, utilize RIE technology to etch away the SiO of opening figure below then
2The second dielectric layer 3-2 at signal processing circuit zone A forms the first through hole 8-1, the second dielectric layer 3-2 at sensor unit B forms third through-hole 8-3, fills the tungsten plug in the first through hole 8-1 and third through-hole 8-3, is used for realizing the electrical connection between materials at two layers up and down; Radio-frequency power during described RIE etching is 150W, and pressure is 400mTorr, and etching gas is CHF
3, He and SF
6Mist, flow are respectively 7sccm, 100sccm and 30sccm;
(12) as shown in figure 14, at the second dielectric layer 3-2 surface deposition metallic aluminium, thickness is 0.4 μ m, and adopts chemical wet etching to form the first signal processing circuit metal level 5-1 of signal processing circuit zone A and the first metal layer 5-1 ' of sensor unit B;
(13) as shown in figure 15, adopt LPCVD technology deposit SiO
2, obtaining thickness is the 3rd dielectric layer 3-3 of 0.8 μ m; At the 3rd dielectric layer 3-3 surface spin coating photoresist, form the photoresist opening by photoetching process at photoresist, utilize RIE technology to etch away the SiO of opening figure below then
2The 3rd dielectric layer 3-3 at signal processing circuit zone A forms the second through hole 8-2, the 3rd dielectric layer 3-3 at sensor unit B forms fourth hole 8-4, fills the tungsten plug in the second through hole 8-2 and fourth hole 8-4, is used for realizing the electrical connection between materials at two layers up and down; Radio-frequency power during described RIE etching is 150W, and pressure is 400mTorr, and etching gas is CHF
3, He and SF
6Mist, flow are respectively 7sccm, 100sccm and 30sccm;
(14) as shown in figure 16, at the 3rd dielectric layer 3-3 surface deposition metallic aluminium, thickness is 0.4 μ m, and adopts chemical wet etching to form the secondary signal treatment circuit metal level 5-2 of signal processing circuit zone A and the second metal level 5-2 ' of sensor unit B;
(15) as shown in figure 17, adopt LPCVD technology deposit SiO
2, obtaining thickness is the 4th layer of medium 3-4 of 1 μ m;
(16) as shown in figure 18, at the 4th dielectric layer 3-4 surface deposition 0.4 μ m metallic aluminium, the 4th dielectric layer 3-4 surface at signal processing circuit zone A forms the 3rd signal processing circuit metal level 5-3, forms the 3rd metal level 5-3 ' on the 4th dielectric layer 3-4 surface of sensor unit B; Adopt chemical wet etching to form corrosion opening 6 at the 3rd metal level 5-3 ' of sensor unit B;
(17) as shown in figure 19, utilize CHF
3Carry out anisotropic rie except the SiO of corrosion removal opening 6 belows with the He mist
2And Si
3N
4, up to the upper surface that arrives silicon base 1, thereby the structure sheaf on silicon base 1 forms the release aperture 9 perpendicular to silicon base; Described etch rate is 1000 ~ 2000/min, and etch period is 10min, CHF
3Be respectively 60sccm, 50sccm with the gas flow of He;
(18) as shown in figure 20, use XeF by release aperture 9
2And O
2Mist carries out the isotropic reactive ion etching, and the silicon base 1 under release aperture 9 forms cavity 2; Wherein, the content of oxygen is 30%, and etching temperature is 550 ℃, and power is 150W, and pressure is 400mTorr, XeF
2And O
2Gas flow be respectively 100sccm, 30sccm.
As shown in Figure 1, integrated thermal electric heap IRDS of the present invention is integrated with thermopile sensor 100 and signal processing circuit, and signal processing circuit comprises the chopper amplifier 200 for the pickup ultra-weak electronic signal, the local temperature sensing unit 500 that is used for analog-to-digital sigma-delta AD converter 300, digital signal processing unit 400 and is used for measuring silicon base absolute temperature.
Claims (7)
1. the integrated thermal electric based on CMOS technology is piled IRDS, comprise silicon base (1) and be positioned at structure sheaf on the silicon base (1), it is characterized in that: described silicon base (1) and structure sheaf are made up of signal processing circuit zone (A) and sensor unit (B);
In described signal processing circuit zone (A), described silicon base (1) is gone up photoetching and is formed N trap (13), structure sheaf on the silicon base (1) upwards is followed successively by field oxide (15) from bottom, second dielectric layer (3-2), the 3rd dielectric layer (3-3) and the 4th dielectric layer (3-4), the first signal processing circuit metal level (5-1) is set between second dielectric layer (3-2) and the 3rd dielectric layer (3-3), between the 3rd dielectric layer (3-3) and the 4th dielectric layer (3-4), secondary signal treatment circuit metal level (5-2) is set, the 3rd signal processing circuit metal level (5-3) is set on the surface of the 4th dielectric layer (3-4); Described field oxide (15) is provided with PMOS zone (13-1) and nmos area territory (13-2), sets gradually gate oxide (16) and signal processing circuit polysilicon layer (4-1) respectively in the bottom of PMOS zone (13-1) and nmos area territory (13-2); First through hole (8-1) and second through hole (8-2) are set respectively on described second dielectric layer (3-2) and the 3rd dielectric layer (3-3);
In described sensor unit (B), structure sheaf on the silicon base (1) upwards is followed successively by first dielectric layer (3-1) from bottom, second dielectric layer (3-2), the 3rd dielectric layer (3-3) and the 4th dielectric layer (3-4), sensor polysilicon layer (4-1 ') is set between first dielectric layer (3-1) and second dielectric layer (3-2), the first metal layer (5-1 ') is set between second dielectric layer (3-2) and the 3rd dielectric layer (3-3), second metal level (5-2 ') is set between the 3rd dielectric layer (3-3) and the 4th dielectric layer (3-4), and the surface of the 4th dielectric layer (3-4) arranges the 3rd metal level (5-3 '); Third through-hole (8-3) is set in described second dielectric layer (3-2), fourth hole (8-4) is set in the 3rd dielectric layer (3-3); Structure sheaf on described silicon base (1) arranges release aperture (9), and release aperture (9) is extended to the upper surface of silicon base (1) by the 3rd metal level (5-3 '); Silicon base (1) in described release aperture (9) below goes up etching and forms cavity (2).
2. the integrated thermal electric based on CMOS technology as claimed in claim 1 is piled IRDS, it is characterized in that: described N trap (13) is extended by the upper surface of silicon base (1) lower surface to silicon base (1), and the degree of depth of N trap (13) is less than the thickness of silicon base (1), and the width of N trap (13) is less than the width of the silicon base (1) of signal processing circuit zone (A).
3. the integrated thermal electric based on CMOS technology as claimed in claim 1 is piled IRDS, it is characterized in that: described cavity (2) is extended by the upper surface of silicon base (1) lower surface to silicon base (1), and the degree of depth of cavity (2) is less than the thickness of silicon base (1), and the width of cavity (2) is less than the width of the silicon base (1) of sensor unit (B).
4. the integrated thermal electric heap IRDS based on CMOS technology as claimed in claim 1 is characterized in that: fill silica in described PMOS zone (13-1) and nmos area territory (13-2).
5. the integrated thermal electric based on CMOS technology as claimed in claim 1 is piled IRDS, it is characterized in that: the tungsten plug is set in described first through hole (8-1) connects the first signal processing circuit metal level (5-1) and signal processing circuit polysilicon layer (4-1), the tungsten plug is set in second through hole (8-2) connects the first signal processing circuit metal level (5-1) and secondary signal treatment circuit metal level (5-2), the tungsten plug is set in third through-hole (8-3) connects sensor polysilicon layer (4-1 ') and the first metal layer (5-1 '), tungsten plug connection the first metal layer (5-1 ') and second metal level (5-2 ') are set in fourth hole (8-4).
6. the integrated thermal electric based on CMOS technology as claimed in claim 1 is piled IRDS, and it is characterized in that: described first dielectric layer (3-1) comprises silicon oxide layer (3-1-1) and silicon nitride layer (3-1-2).
7. the preparation method based on the integrated thermal electric heap IRDS of CMOS technology is characterized in that, comprises following processing step:
(1) silicon chip of selecting (100) crystal orientation is as silicon base (1), and going up oxidation growth one layer thickness in silicon base (1) is the silica of 0.5 μ m, goes up photoetching in silicon base (1) and forms N trap (13), and carry out ion at N trap (13) and inject phosphorus;
(2) go up thermal oxide growth in silicon base (1) and obtain silicon oxide layer (3-1-1), dielectric material is SiO
2
(3) adopt Low Pressure Chemical Vapor Deposition (LPCVD) deposit silicon nitride layer (3-1-2), material is Si
3N
4At the surperficial spin coating photoresist of silicon nitride layer (3-1-2), form the photoresist opening figure by photoetching process at photoresist, utilize reactive ion etching (RIE) technology to etch away silicon nitride layer (3-1-2) and the silicon oxide layer (3-1-1) of opening figure below then, form etching cavity at signal processing circuit zone (A);
(4) thermal oxide growth field oxide (15) in the etching cavity that step (3) forms;
(5) adopt the reactive ion etching process etching to remove silicon nitride layer (3-1-2) and the silicon oxide layer (3-1-1) in signal processing circuit zone (A), formation PMOS injection window (13-1 ') and NMOS injection window (13-2 ');
(6) inject window (13-1 ') and NMOS injection window (13-2 ') thermal oxide growth gate oxide (16) at PMOS;
(7) using plasma strengthens chemical vapour deposition (CVD) (PECVD) technology deposit polysilicon, and carries out ion and inject phosphorus; Polysilicon is carried out chemical wet etching, form signal processing circuit polysilicon layer (4-1) at the gate oxide (16) of signal processing circuit zone (A), and at silicon nitride layer (3-1-2) the formation sensor polysilicon layer of sensor unit (B) (4-1 ');
(8) zone except PMOS injects window (13-1 ') is protected with photoresist, injected window (13-1 ') to PMOS and inject boron ion, formation PMOS zone (13-1);
(9) zone except NMOS injects window (13-2 ') is protected with photoresist, injected window (13-2 ') to NMOS and inject phosphonium ion, formation nmos area territory (13-2);
(10) adopt LPCVD technology deposit second dielectric layer (3-2), dielectric material is SiO
2And make in the cavity of PMOS zone (13-1) and nmos area territory (13-2) and fill SiO
2
(11) at the surperficial spin coating photoresist of second dielectric layer (3-2), form the photoresist opening by photoetching process at photoresist, utilize RIE technology to etch away the SiO of opening figure below then
2Second dielectric layer (3-2) at signal processing circuit zone (A) forms first through hole (8-1), second dielectric layer (3-2) at sensor unit (B) forms third through-hole (8-3), fills the tungsten plug in first through hole (8-1) and third through-hole (8-3);
(12) at second dielectric layer (3-2) surface deposition metallic aluminium, and the first metal layer of the first signal processing circuit metal level (5-1) in employing chemical wet etching formation signal processing circuit zone (A) and sensor unit (B) (5-1 ');
(13) adopt LPCVD technology deposit SiO
2, obtain the 3rd dielectric layer (3-3); At the surperficial spin coating photoresist of the 3rd dielectric layer (3-3), form the photoresist opening by photoetching process at photoresist, utilize RIE technology to etch away the SiO of opening figure below then
2The 3rd dielectric layer (3-3) at signal processing circuit zone (A) forms second through hole (8-2), the 3rd dielectric layer (3-3) at sensor unit (B) forms fourth hole (8-4), fills the tungsten plug in second through hole (8-2) and fourth hole (8-4);
(14) at the 3rd dielectric layer (3-3) surface deposition metallic aluminium, and second metal level of the secondary signal treatment circuit metal level (5-2) in employing chemical wet etching formation signal processing circuit zone (A) and sensor unit (B) (5-2 ');
(15) adopt LPCVD technology deposit SiO
2, obtain the 4th layer of medium (3-4);
(16) at the 4th dielectric layer (3-4) surface deposition metallic aluminium, form the 3rd signal processing circuit metal level (5-3) on the 4th dielectric layer (3-4) of signal processing circuit zone (A) surface, form the 3rd metal level (5-3 ') on the 4th dielectric layer (3-4) surface of sensor unit (B); Adopt chemical wet etching to form corrosion opening (6) at the 3rd metal level of sensor unit (B) (5-3 ');
(17) adopt anisotropic rie except the SiO of corrosion removal opening (6) below
2And Si
3N
4, up to the upper surface that arrives silicon base (1), thereby the structure sheaf on silicon base (1) forms the release aperture (9) perpendicular to silicon base;
(18) adopt the isotropic reactive ion etching by release aperture (9), the silicon base (1) under release aperture (9) forms cavity (2).
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