CN1033329A - Computer device for fail-safe - Google Patents
Computer device for fail-safe Download PDFInfo
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- CN1033329A CN1033329A CN 87107219 CN87107219A CN1033329A CN 1033329 A CN1033329 A CN 1033329A CN 87107219 CN87107219 CN 87107219 CN 87107219 A CN87107219 A CN 87107219A CN 1033329 A CN1033329 A CN 1033329A
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Abstract
The invention relates to the computer device for fail-safe that is applicable in the safety guard, wherein two computer circuits are separate, and the logical and of output signal of getting each computer circuit is as final output signal.Carry out in the process of calculation process at each computer circuit, their operation result is compared, when the two is inconsistent, just output safety signal, thus can reach fault-secure purpose.
Description
The invention relates to the computer device for fail-safe in the safety guard that is applicable to rolling stock for example.
Fig. 4 be have earlier, for example at the block diagram of the computer device for fail-safe of " JREA " 1985 the 28th volume the 10th phase the 16287th page～the 16291st page of record.Among the figure, (1) is microprocessor (hereinafter to be referred as CPU); (2) be input port; (3) be the memory of depositing program and data; (4) be output port; (5) be the computer circuits that constitute by (1)～(4); (6) be simultaneously with two CPU(1 on the bus (12)) the bus data comparator circuit that compares of instruction; (7) be first signal of output port (4) output; (8) be the secondary signal of bus data comparator circuit (6) output; (9) be AND circuit, obtain the logical and signal of first signal (7) and secondary signal (8) by it; (10) be the 3rd signal of AND circuit output; (11) be input signal; (12) be to transmit the bus that signal is used.
The device of said structure is used for detecting the mistake in each step instruction in the process of carrying out the logical operation processing.That is to say, earlier identical program is deposited in two computer circuits, and carry out same instruction simultaneously, constantly the instruction of execution and the data of processing are compared then.When the two takes place then to be judged as fault when inconsistent, and output signal.
When need read in CPU(1 to the input signal of input port (2) (11)) time, director data is just preserved storage (3) and is sent CPU(1 to).CPU(1) then by instructing, input signal (11) is read in CPU(1 by bus (12) from input port (2) reading of data) in.In above-mentioned a series of actions, director data and input data (input signal) are all passed through bus (12) and are transmitted.At this moment, if two counter circuits (5) are carried out same action under same input signal (11) state, the data on the bus (12) are always identical usually.Bus data comparator circuit (6) compares the data on the above-mentioned bus (12), is output as " 1 " when consistent, is output as " 0 " when inconsistent.And first signal (7) of output port (4) output is exported as the 3rd signal by AND circuit (9) with the logical and of the secondary signal (8) of bus data comparator circuit (6) output and is gone.Because the computer device for fail-safe that has earlier constitutes by above-mentioned form, so the processing procedure journey of two computer circuits must be fully synchronously, control is with regard to more complicated like this.
The present invention puts forward in order to address the above problem, and its purpose aims to provide the computer device for fail-safe that a kind of processing procedure that makes two computer circuits is non-synchronously carried out.
Computer device for fail-safe of the present invention makes two computer circuits independently of one another, and compare at last output terminal, rely among the result of each computer circuit computing necessary data in the Min. relatively simultaneously and come inconsistent situation in the detection calculations process.
Computer device for fail-safe of the present invention is made of two computer circuits independent of each other, and the logical and of output signal of getting each computer circuit is as final output signal.At this moment, the operation result that obtains in the calculation process process of each computer circuit is compared, when taking place when inconsistent, just output safety signal, thus reach fault-secure purpose.
Fig. 1 is a structured flowchart of the present invention, and Fig. 2 is the key diagram of presentation graphs 1 on the function, and Fig. 3 is the process flow diagram of the action of presentation graphs 2, and Fig. 4 is the block diagram of the computer installation that has earlier.Among the figure, (5) are computer circuits, and (7) are first signal (consistent signal or inconsistent signals), and (10) are the 3rd signal (inconsistent judgement signals).
In addition, the identical identical or suitable part of symbolic representation among each figure.
The following describes one embodiment of the present of invention.In Fig. 1, (1)～(5), (7), (9)～(12) are identical with the device that has earlier.(13) be input/outbound port, be used for the intermediate operations result of each computer circuit (5) being sent to another computer circuit (5) mutually or transmitting in order to carry out signal from another computer circuit (5) reception information; (14) be data line.
In said structure, each computer circuit (5) carries out asynchronous processing according to input signal (11), exports first signal (7) then.At this moment, each computer circuit (5) compares by the operation result of each I/O port (13) with operation result in the middle of it and another computer circuit (5).And, if unanimity is as a result relatively then exported first signal (7) by common calculation process.
In addition, if result relatively is inconsistent, the earthworm terrified awake loess hills of Su Nian Qu that probably frequently faints smokes footpath between fields, the third constellations and steps on show off lotus root ox all of a sudden).
Utilize Fig. 2 and Fig. 3 that these actions are described below.Among the figure, if at S
1Stage is input into input signal (11), and control arithmetic processor (15) just carries out calculation process, and operation result is gone as the 4th signal (16) output.In the process of above-mentioned calculation process, promptly at S
2In the stage, just obtain data A or data A '.At S
3In the stage, each computer circuit (5) is swap data A and A ' mutually, at S
4Stage is compared two sets of data A and A ' by consistent measurement processor (17), exports the 5th signal (18) then.If comparative result is A=A ', then at S
5And S
6Stage makes first signal (7) of computer circuit (5) output identical with the 4th signal (16).If comparative result is A ≠ A ', so as first signal (7) of computer circuit (5) output, just with the 4th signal (16) irrespectively, output safety signal " 0 " unconditionally.These logical process are finished by logical and processor (19).
As mentioned above, the failure of removal that takes place in the calculation process process carries out the computer circuit consistent measurement processor (17) on one side that normal operation handles in by Fig. 2 and detects, and make first signal (7) for " 0 " by logical and processor (19), make output signal deflection safety.As final output, the output signal of AND circuit (9) i.e. the 3rd signal (10) just is output as safety signal.
As mentioned above, according to the present invention, by the operation result that obtains in the calculation process process of two separate computer circuits is compared, just can be when the two be inconsistent, the output safety signal.
Claims (2)
1, a computer device for fail-safe, it is characterized in that: the data that obtain in the calculating process of two computer circuits that carry out calculation process are exchanged between above-mentioned each computer circuit mutually according to instruction, when above-mentioned two sets of data are consistent, export consistent signal by above-mentioned each computer circuit, export inconsistent signal when inconsistent, and above-mentioned consistent signal and above-mentioned inconsistent signal are judged by decision circuitry, when at least one side's output signal is above-mentioned inconsistent signal in above-mentioned two computer circuits, just export inconsistent judgement signal.
2, the feature by the described computer device for fail-safe of claim 1 is: decision circuitry is an AND circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 87107219 CN1033329A (en) | 1987-10-30 | 1987-10-30 | Computer device for fail-safe |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 87107219 CN1033329A (en) | 1987-10-30 | 1987-10-30 | Computer device for fail-safe |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1033329A true CN1033329A (en) | 1989-06-07 |
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ID=4816014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 87107219 Pending CN1033329A (en) | 1987-10-30 | 1987-10-30 | Computer device for fail-safe |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1033329A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694641A (en) * | 2012-05-10 | 2012-09-26 | 四川电力科学研究院 | Real-time synchronization method of mirrored MCUs |
-
1987
- 1987-10-30 CN CN 87107219 patent/CN1033329A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694641A (en) * | 2012-05-10 | 2012-09-26 | 四川电力科学研究院 | Real-time synchronization method of mirrored MCUs |
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| WD01 | Invention patent application deemed withdrawn after publication |