CN103326375A - Direct-hanging type reactive power compensation device and method based on 10kV power grid - Google Patents

Abstract

A direct-mounted reactive power compensation device and method based on a 10kV power grid, the device includes a current transformer, a voltage transformer, an AD sampling board, a main control device, a voltage zero-crossing detection circuit, a communication control device, a pulse generator, Pulse distribution board, SPWM signal transmission circuit, 2H bridge cascaded inverter circuit, filter, PLC, touch screen and IO board; the direct-mounted reactive power compensation device based on 10kV power grid of the present invention, its direct-mounted type is embodied in this The AC side of this topology can be directly connected to the grid through the reactor in the grid system, without the need for a transformer to achieve grid connection. The compensation instruction current detection algorithm of the improved i _p -i _q method is used, and the phase angle value φ when the system voltage jumps is added to the reactive current detection process, so that the system voltage in any state can be detected. At the same time, the structure of DSP + double FPGA is adopted to make the device achieve the purpose of fast dynamic compensation in terms of performance.

Description

A kind of direct hanging type reactive power compensation device and method based on the 10kV electrical network

Technical field

The invention belongs to static reacance generator device technique field, particularly a kind of direct hanging type reactive power compensation device and method based on the 10kV electrical network.

Background technology

The compensation of reactive power plays conclusive effect to the assessment of power system voltage quality, voltage is an important indicator weighing the quality of power supply, up-to-standard voltage should be offset at supply power voltage, voltage fluctuation and flickering, these four aspects of the asymmetric degree of mains by harmonics and three-phase can both satisfy the requirement of the countries concerned's standard code, so the working voltage in the electric power system depends on the balance of reactive power.Good reactive power compensator can improve static state and the transient stability limit of system, has improved voltage stability, and then improves the quality of power supply, and can realize the large capacity of Mvar level fast, reliably, the requirement of dynamic compensation.

The raising of reactive power compensation device can be set about from two aspects, and the one, control algolithm, the 2nd, controller's design.The restriction of large capacity SVG (Static Var Generator static reacance generator) device; accomplish that under present technology large capacity, high voltage SVG device exist many restraining factors, the simultaneously design of SVG Setup Controller and protective device exists difficult point.Aspect the SVG control method, accurately real-time detection computations goes out reactive current, obtain idle command signal and produce switching device in the corresponding SPWM pulse signal cascaded 2H bridge inverter by control method, so the accurate real-time detection of reactive current plays critical effect in the design of SVG device.When selecting the detection algorithm of reactive current, must guarantee its rapidity, accuracy and flexibility.

Summary of the invention

Problem for prior art exists the invention provides a kind of direct hanging type reactive power compensation device and method based on the 10kV electrical network.

Technical scheme of the present invention is:

A kind of direct hanging type reactive power compensation device based on the 10kV electrical network comprises current transformer, voltage transformer, AD sampling plate, master control set, voltage zero-crossing detection circuit, communication control unit, pulse generator, pulse distribution plate, SPWM signal circuit, 2H bridge cascade inverter circuit, filter, PLC, touch-screen and IO plate;

Described AD sampling plate comprises current regulating circuit, voltage modulate circuit and AD sampling A/D chip;

The input of described current transformer, the input of voltage transformer all is connected to the 10kV electrical network, the output of current transformer connects the input of current regulating circuit, the output of voltage transformer connects the input of voltage modulate circuit, the output of current regulating circuit, the output of voltage modulate circuit all is connected to the input of AD sampling A/D chip, the output of AD sampling A/D chip is connected to the input of master control set, master control set respectively with communication control unit, pulse generator, voltage zero-crossing detection circuit, 2H bridge cascade inverter circuit connects, communication control unit connects PLC, PLC connects touch-screen, the output of pulse generator connects the input of pulse distribution plate, the output of pulse distribution plate connects the input of SPWM signal circuit, the output of SPWM signal circuit connects the input of 2H bridge cascade inverter circuit, the output of 2H bridge cascade inverter circuit connects the input of filter, the output of filter is connected to the 10kV electrical network, another input of 2H bridge cascade inverter circuit connects the output of IO plate, and another output of IO plate is connected to communication control unit.

Described communication control unit and pulse generator all adopt FPGA.

Described communication control unit is for the reactive power compensation status data that receives the 10kV electrical network that feeds back through the IO plate and with the device of this transfer of data to the touch-screen demonstration.

Adopt described method of carrying out reactive power compensation based on the direct hanging type reactive power compensation device of 10kV electrical network, may further comprise the steps:

Step 1: current transformer and voltage transformer be transient current and the instantaneous voltage of the three-phase inverter side of Real-time Collection 10kV electrical network respectively, and transient current and instantaneous voltage are transferred to master control set through the AD sampling plate;

Step 2: master control set carries out Detecting Reactive Current according to transient current and instantaneous voltage to the 10kV electrical network, obtains the reactive power compensation electric current;

Step 2.1: transient current and the instantaneous voltage that collects carried out the d-q coordinate transform, be about to d-q coordinate system and three-dimensional cartesian coordinate system and carry out synchronous rotary with the first-harmonic angular frequency, obtain instantaneous active current i _p, instantaneous reactive current i _q, the d axle component of voltage and the q axle component of voltage;

Step 2.2: according to instantaneous active current i _p, instantaneous reactive current i _q, the d axle component of voltage and voltage q axle component obtain amplitude and the phase place of fundamental voltage;

Step 2.3: adopt the phase place of phase-locked loop locking A phase instantaneous voltage, produce synchronizing signal sin θ and the cos θ of instantaneous voltage, and then produce the transition matrix between d-q coordinate system and the clarke conversion;

Step 2.4: with the synchronizing signal of instantaneous voltage and the Phase Stacking of fundamental voltage, the d-q coordinate system that step of updating 2.3 produces and the transition matrix between the clarke conversion, and then obtain the reactive power compensation electric current;

Step 3: the difference of calculating the transient current of reactive power compensation electric current and three-phase inverter side, this difference is carried out the PI adjusting and current signal is converted to voltage signal, and the voltage triangular carrier in this voltage signal and the pulse generator is compared output SPWM pulse;

Step 4: pulse generator adopts the SPWM control method of triangular carrier homophase stacked switch frequency optimization to produce the SPWM pulse of optimizing to the SPWM pulse of more afterwards output, and the SPWM pulse of optimizing is added a zero-sequence component u _Z, the SPWM pulse of optimizing is revised, obtain the SPWM pulse of reactive power compensation;

$u_Z=\frac{1}{2}[{(u_A,u_B,u_C)}_{\max }+{(u_A,u_B,u_C)}_{\min }]$

Wherein, u _A, u _B, u _CBe respectively A phase, the B phase of 10kV electrical network, the instantaneous voltage of C phase;

Step 5: the SPWM pulse signal of reactive power compensation distributes through the pulse distribution plate, and when voltage zero-cross detects zero point, trigger 2H bridge cascade inverter circuit, when 2H bridge cascade inverter circuit produces fault, fault-signal is fed back to master control set, and quitting work, otherwise execution in step 6;

The signal of step 6:2H bridge cascade inverter circuit output carries out reactive power compensation to the 10kV electrical network behind filter filtering;

The reactive power compensation status data of step 7:10kV electrical network transfers to communication control unit by the IO plate, and communication control unit is passed to PLC with data again, and PLC crosses touch-screen with data communication device again and shows.

Beneficial effect:

The present invention is based on the direct hanging type reactive power compensation device of 10kV electrical network, and the AC that its direct hanging type is embodied in this topological structure gets final product by the reactor direct grid-connected in the network system, and does not need to realize being incorporated into the power networks by transformer.This device adopts and improves i _p-i _qThe compensating instruction Current Detection Algorithm of method, the angle values φ during with the system voltage saltus step is added in the Detecting Reactive Current process, can detect the free position system voltage like this.Simultaneously, because this device has adopted the DSP+ double FPGA to form structure, make device reach the purpose of quick dynamic compensation in performance.

Description of drawings

Fig. 1 is the direct hanging type reactive power compensation device structured flowchart based on the 10kV electrical network of the specific embodiment of the invention;

Fig. 2 is the current transformer of the specific embodiment of the invention and the circuit catenation principle figure of current regulating circuit;

Fig. 3 is the voltage transformer of the specific embodiment of the invention and the circuit catenation principle figure of voltage modulate circuit;

Fig. 4 is the circuit theory diagrams of the AD sampling A/D chip AD7266BSU of the specific embodiment of the invention;

Fig. 5 is the circuit theory diagrams that the EP3C25Q240C8 of the specific embodiment of the invention extends out SRAM;

Fig. 6 is the DSP of the specific embodiment of the invention and the Principle of Communication figure between the FPGA;

Fig. 7 is the zero cross detection circuit schematic diagram of the specific embodiment of the invention;

Fig. 8 is the circuit topological structure figure based on the direct hanging type reactive power compensation device of 10kV electrical network of the specific embodiment of the invention;

Fig. 9 is the Optical Fiber Transmission schematic diagram of the SPWM signal of the specific embodiment of the invention;

Figure 10 is the IGBT2H bridge inversion unit structural representation of the specific embodiment of the invention;

Figure 11 is the pulse generator building-block of logic of the specific embodiment of the invention;

Figure 12 is the improvement i of the specific embodiment of the invention _p-i _qReactive power current detecting schematic diagram;

Figure 13 is that the triangular carrier of the specific embodiment of the invention compares control principle drawing;

Figure 14 is the direct hanging type Non Power Compensation Process flow chart based on the 10kV electrical network of the specific embodiment of the invention.

Embodiment

Below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated.

As shown in Figure 1, the direct hanging type reactive power compensation device based on the 10kV electrical network of present embodiment comprises current transformer, voltage transformer, AD sampling plate, master control set, voltage zero-crossing detection circuit, communication control unit, pulse generator, pulse distribution plate, SPWM signal circuit, 2H bridge cascade inverter circuit, filter, PLC, touch-screen and IO plate;

The input of current transformer, the input of voltage transformer all is connected to the 10kV electrical network, the output of current transformer connects the input of current regulating circuit, the output of voltage transformer connects the input of voltage modulate circuit, the output of current regulating circuit, the output of voltage modulate circuit all is connected to the input of AD sampling A/D chip, the output of AD sampling A/D chip is connected to the input of master control set, master control set respectively with communication control unit, pulse generator, voltage zero-crossing detection circuit, 2H bridge cascade inverter circuit connects, communication control unit connects PLC, PLC connects touch-screen, the output of pulse generator connects the input of pulse distribution plate, the output of pulse distribution plate connects the input of SPWM signal circuit, the output of SPWM signal circuit connects the input of 2H bridge cascade inverter circuit, the output of 2H bridge cascade inverter circuit connects the input of filter, the output of filter is connected to the 10kV electrical network, another input of 2H bridge cascade inverter circuit connects the output of IO plate, and another output of IO plate is connected to communication control unit.

Communication control unit is for the reactive power compensation status data that receives the 10kV electrical network that feeds back through the IO plate and with the device of this transfer of data to the touch-screen demonstration.

The type of current transformer is and is that CSM300B, the model of voltage transformer are VSM025A, and A D sampling plate comprises current regulating circuit, voltage modulate circuit and AD sampling A/D chip, and wherein, the model of AD sampling A/D chip is AD7266BSU.

A D sampling plate mainly to sampling by the signal of voltage transformer summation current transformer collection, has gathered the three-phase voltage u of system _S, the three-phase current i of system _s, load current i _h, inversion side output current i _g, inversion side dc capacitor voltage u _Dc, 9 analog inputs altogether.Model is inner integrated 16 ALT-CH alternate channel 12 bit A/D converters of the DSP of TMS320F28335, has 2 sampling holders, therefore in synchronization 2 tunnel analog signals of can only sampling.This device will be sampled 13 road signals simultaneously when considering preserved signal, needs 16 road AD ALT-CH alternate channels, so the dsp controller use extends out AD sampling A/D chip, i.e. AD sampling A/D chip AD7266BSU in the AD sampling plate.AD7266 is a Analog Device 12-bit of company, at a high speed, low-power consumption, the binary channels of approaching the one by one AD chip of sampling simultaneously, because it is that 100mV is to 2.5V, so the voltage before entering the AD sampling A/D chip, current signal will be nursed one's health just and can sample that AD7266 allows signal voltage range.

Because the modulate circuit principle of every road signal is the same, here only A phase current modulate circuit and AD sampling A/D chip are described, as shown in Figure 2, the current regulating circuit is connected as shown in Figure 2 with current transformer CSM300B's, the current regulating circuit adopts the two-stage amplifying circuit, wherein, signal HV_IA is the output signal of current regulating circuit, the pin 1 of current transformer CSM300B links to each other with power supply+15V, the pin 2 of CSM300B links to each other with power supply-15V, the pin 3 of CSM300B respectively with R20, R22, C31 links to each other, the pin 4 of CSM300B respectively with ground, R20, R21, C31 links to each other, the pin 2 of amplifier U1A (LM2904DR2) respectively with R21, C32, R23 links to each other, the pin 3 of amplifier U1A respectively with R22, R24, C33 links to each other, the pin 4 of amplifier U1A respectively with VCC-5V, the end of C37 links to each other, the pin 8 of amplifier U1A respectively with VCC+5, the end of C36 links to each other, the other end of C36, the other end ground connection of C37, the pin 1 of amplifier U1A respectively with R23, the end of R25, C32 links to each other, the R25 other end respectively with C35, R26 links to each other, the other end of R26 links to each other with R27, the pin 6 of amplifier U1B (LM2904DR2) respectively with R27, R31 links to each other, detection signal XADVREFA meets R28, meeting R29 links to each other with the pin 5 of LM2904DR2 again, the pin 5 of amplifier U1B respectively with R29, R30 links to each other, R30 other end ground connection, the pin 7 of amplifier U1B respectively with R31, R32 links to each other, C34 other end ground connection.

Second level operational amplifier among Fig. 2 has consisted of subtraction circuit, and external signal HV_IA can find out by formula (1) from the measuring-signal of current transformer to 2H bridge cascade inverter circuit, and this signal is superimposed upon signal V _AOn, play and reduce second level computing output voltage V _EThe effect of level.External voltage signal V _REFBe the external reference voltage from AD sampling A/D chip 4 pins output, the external reference voltage scope determined by analog input, and the output voltage that can obtain second level operational amplifier is:

$V_E=V_B-R_{31}(\frac{V_A-{\mathrm{<figure-callout\; id="25"\; label="V\; B\; R"\; filenames="HDA00003341420600022.png"\; state="\{\{state\}\}">V</figure-callout>}}_B}{R_{}}+H_V\_I_A)---\left(1\right)$

Wherein:

$V_B=V_C=\frac{R_{30}}{R_{28}+{\mathrm{<figure-callout\; id="29"\; label="R"\; filenames="HDA00003341420600022.png"\; state="\{\{state\}\}">R</figure-callout>}}_{29}+{\mathrm{<figure-callout\; id="30"\; label="R"\; filenames="HDA00003341420600022.png"\; state="\{\{state\}\}">R</figure-callout>}}_{30}}\&CenterDot;V_{\mathrm{REF}}---\left(2\right)$

Resistance value at the present embodiment is chosen, and is then got by formula (2)

And V _REFScope is at 0～5V.Therefore the conditioning of through type (1) subtraction circuit is adjusted to unipolar signal with bipolar signal.And voltage signal V _EBetween 0～1.25V, satisfy the sample range of AD sampling A/D chip.Then the AD sampling A/D chip as shown in Figure 4.The result of AD sampling is transferred to dsp processor by output pin DOUTA, DOUTB and is further processed calculating.

Direct voltage modulate circuit schematic diagram as shown in Figure 6, Hall voltage instrument transformer VSM025A is all used in direct voltage and alternating voltage sampling, direct voltage sampling output that different is be direct current signal, through the conditioning output sampled signal of two-stage voltage follower, so do not need variation.

The voltage modulate circuit is connected as shown in Figure 3 with voltage transformer VSM025A's, the voltage modulate circuit adopts the two-stage amplifying circuit, in the voltage modulate circuit, the pin 1 of voltage transformer VSM025A meets VCC+15V, the pin 2 of VSM025A meets VCC-15V, the pin 3 of VSM025A respectively with R33, R34, C48 links to each other, the pin 4 of VSM025A meets AGND, and the pin 3 of amplifier U3A (LM2904DR2) meets R34, pin 2 pins 1 of amplifier U3A, the pin 4 of U3A meets VCC-5V and C49, the pin 8 of U3A meets VCC5V and C50, C49 and C50 ground connection, and the pin 1 of U3A connects respectively its pin 2, R38, R38 meets R35, extraneous signal inversion side dc capacitor voltage u _DcMeet R35, R38, the pin 5 of U3B meets R35, pin 6 pins 7, and the pin 7 of U3A links to each other with R36, and R36 links to each other with the pin 18 of AD7266BSU, the pin 3 of rectifier DAN217U respectively, and the pin 1 of DAN217U links to each other with VCC3V3, and the pin 2 of DAN217U links to each other with AGND.

The circuit of AD sampling A/D chip AD7266BSU as shown in Figure 4, detection signal XADVREFA connects 6 pin and 7 pin of U2B (LM2904DR2), 5 pin of U2B (LM2904DR2) and the pin 4 of AD7266, capacitor C 40 links to each other, C40 other end ground connection, 4 pin one tunnel of U2B (LM2904DR2) connect-the 5V power supply, and another road connects again ground connection of capacitor C 39,8 pin of U2B (LM2904DR2) meet power supply+5V, and through capacitor C 38 ground connection, detection signal XADVREFB connects U2A (LM2904DR2) pin 1, pin 2, the pin 3 of U2A (LM2904DR2) connects the pin 20 and capacitor C 41 of AD7266, C41 other end ground connection, pin 3 and the power supply+5V of AD7266, C45, C44 links to each other, the pin 5 of AD7266, pin 6, pin 19 ground connection, capacitor C 44, C45 ground connection, the pin 31 of AD7266 connects VCC3V3 and capacitor C 47 1 ends, capacitor C 47 other end ground connection, pin 32 and the power supply+5V of AD7266, capacitor C 46 1 ends link to each other, capacitor C 46 other end ground connection, the pin 1 of AD7266, pin 29 is connected to the ground, the pin A0 of AD7266, A1, A2 meets respectively DSP_AO, DSP_A1, DSP_A2, pin DOUTA, DOUTB meets respectively DSP_DA, DSP_DB, SCLK and CS meet respectively DSP_SK, DSP_CS, the pin 7 of AD7266 meets resistance R 32 and the C34 of current regulating circuit, signal XAD_VREFA, the XAD_VREFB effect is with the reference of the reference voltage on the chip as external system, in-phase voltage input as voltage modulate circuit secondary amplifier mainly plays the control voltage range.

It is the FPGA of EP3C25Q240C8 that communication control unit and pulse generator all adopt model, and it is the DSP of TMS320F28335 that master control set adopts model.

EP3C25Q240C8 and extend out SRAM as shown in Figure 5, it is the chip of EPCS4S18N that SRAM adopts model, the pin 12 of FPGA2 links to each other with the pin 5 of EPCS4S18N, the pin 14 of FPGA2 links to each other with the pin 1 of EPCS4S18N, the pin 23 of FPGA2 links to each other with the pin 6 of EPCS4S18N, the pin 24 of FPGA2 links to each other with resistance R 9, R10, link to each other with the pin 2 of EPCS4S18N after R9, the R10 parallel connection, be connected capacitor C 27 between the pin 6 of EPCS4S18N and its pin 4, its pin 4 ground connection, the pin 3 of EPCS4S18N, pin 7, pin 8 connect power supply, connect capacitor C 28 between the pin 8 of EPCS4S18N and the ground.

The control core based on the direct hanging type reactive power compensation device of 10kV electrical network of present embodiment is comprised of DSP+ double FPGA controller.Adopt this mixture control to be because when only using DSP processing controls algorithm and producing the SPWM pulse, can only adopt fairly simple control algolithm to realize, yet need to adopt complicated and advanced control algolithm for high-voltage large-capacity reactive power compensation (SVG) device, single DSP can not satisfy the requirement of device control, so adopt DSP+ double FPGA control mode.

Based on the controller of the SVG reactive power compensator of DSP+ dual FPGA architecture, DSP mainly is responsible for sampled signal is processed, and the protection control command is sent in finishing of control algolithm; The reactive power compensation instruction that FPGA1 then produces according to DSP produces the SPWM pulse signal of 2H bridge circuit; FPGA2 mainly finish with touch-screen between communicate by letter.Adopt the superiority of DSP+ double FPGA control structure to be: flexible structure is reliable; Versatility is stronger; Can revise different algorithms by software programming, be applicable to modularized design; High and its construction cycle of processing speed efficient is shorter is convenient to maintenance and expansion, is applicable to computing and the processing of live signal.

Principle of Communication between DSP and the FPGA as shown in Figure 6, in this DSP+ dual FPGA architecture, the DSP model is TMS320F28335, the protection control command is processed and sent to main being responsible for to sampled signal; The reactive power compensation instruction that FPGA1 (EPCS4S18N) then produces according to DSP produces the SPWM pulse signal of 2H bridge cascade inverter circuit, and pulse generator FPGA1 logical construction as shown in figure 11; FPGA2 (EP3C25Q240C8) mainly finish with touch-screen between communicate by letter.Communication between them is that the pin SPISIMOA of DSP links to each other with the pin DIFFIO_L13p of FPGA1, the pin SPISOMIA of DSP links to each other with the pin DIFFIO_L13n of FPGA1, the pin SPICLKA of DSP links to each other with the pin RUP1 of FPGA1, the pin SPISTEA of DSP links to each other with the pin RDN1 of FPGA1, the pin SCITXDA of DSP links to each other with the pin DIFFIO_R9n of FPGA1, the pin SCIRXDA of DSP links to each other with the pin DIFFIO_R9p of FPGA1, the pin 214 (XA0) of FPGA2 and the pin XA[0 of DSP] link to each other, the pin 216 (XA1) of FPGA2 and the XA[1 of DSP] link to each other, the like FPGA2 IO mouth to 239 and DSP to pin XA[18] link to each other, pin 181 (XRD) links to each other with the pin XRD of DSP, pin 182 (XWR) links to each other with the pin XWE of DSP, the pin XD[0 of pin 183 (XD0) and DSP] link to each other, the pin XD[1 of pin 184 (XD1) and DSP] link to each other, same the like, the IO mouth of FPGA2 links to each other with the pin XD15 of DSP, and pin 240 (FPGASEL) links to each other with the pin XZCS2 of DSP.

Can find out such as Fig. 6, communicating by letter between DSP and the FPGA1 adopts asynchronous serial SPI to communicate by letter with SCI.The SPI of DSP is the serial input-output interface (SIO) of a high-speed synchronous, allow the long serial bit stream (1-16 position) of programmable bit to move into or shift out equipment with programmable bit transfer rate, SPI supports the multi-computer communication of master/slave pattern simultaneously, here adopt master controller operator scheme (master/slave=1 is MASTER/SLAVE=1), SPI provides serial clock by SPICLKA (clock) pin for whole serial communication network.The control command that calculates the pulse duration of SPWM is exported from the SPISIMOA pin, and latched from the feedback data of the FPGA1 pulse generator of SPISOMIA pin input.The sheet selected control signal processed of SPI controller is finished by the SPISTEA pin, when dsp processor send data to pulse generator FPGA1 with the SPISTEA pin to low, again that the SPISTEA pin is paramount after pending data is sent.The SCI of master controller is a two-wire asynchronous serial port, the digital communication between the asynchronous peripherals of its support CPU and other Application standards zero form (NRZ).For guarantee that the SPWM signal occurs pulse generator accurately and when the fault effective locking pulse will protect control signal to be input to pulse generator by the SCITXDA pin, SCIRXDA receives the feedback signal of FPGA1 transmission simultaneously.

Slow for fear of communication transfer speeds between DSP and the FPGA, avoid simultaneously in the situation that mass data deal with data time-delay is long, real-time is poor, even the data congestion phenomenon occurs, master controller DSP with adopt the dual port RAM communication mode between FPGA2 communicates by letter.The dual port RAM chip adopts the high-speed asynchronous CMOSSRAM IS61LV51216 in 512K * 16.It is the highly reliable coupling circuit design high-performance of being combined with innovative technology, the equipment of low-power consumption.It is being connected of controller to realize by multiplexed asynchronous bus interface XINTF, when FPGA2 wants reading out data, then by enabling the FPGASEL pin, external data bus is transformed into 16 bit data bus when FPGASEL=1, DSP is processed after the demonstration data preparation well obtain by the dual port RAM FPGA2 that communicates by letter, through further processing, send to display screen and supervisory control system by RS485 at last.Read and to have gained outside data/address bus by FPGASEL=0 after the data and carry out the computing of other programs.

The TMS320F28335 on-chip memory contains the Flash memory of 256K and the SRAM of 34K, for a dsp system, the Flash memory of 256K can satisfy the memory requirement of program, the SRAM of 34K is probably not enough, because in the research and development debug phase, generally all be program to be loaded in the SRAM move, need consider that then expansion RAM is used for load module, all can be improved program speed and efficient greatly.It is larger that system moves needed data volume, needs enough memory spaces, therefore also needs to consider to carry out peripheral expansion.Present embodiment is carried out the RAM expansion to DSP, comprises resistance, electric capacity and chip EPCS4S18N.The communication of TMS320F28335 is that the pin 12 of FPGA2 links to each other with the pin 5 of EPCS4S18N, the pin 14 of FPGA2 links to each other with the pin 1 of EPCS4S18N, the pin 23 of FPGA2 links to each other with the pin 6 of EPCS4S18N, the pin 24 of FPGA2 links to each other with resistance R 9, R10, link to each other with the pin 2 of EPCS4S18N after R9, the R10 parallel connection, be connected capacitor C 27, its pin 4 ground connection between the pin 6 of EPCS4S18N and its pin 4, the pin 3 of EPCS4S18N, pin 7, pin 8 connect power supply, connect capacitor C 28 between pin 8 and the ground.

In order to guarantee alternating voltage and the line voltage same frequency of the output of this device, just need a detection synchronous signal circuit to realize SPWM pulse and synchronized.By voltage zero-crossing detection circuit produce one with electrical network same frequency, its rising edge square-wave signal corresponding to the power network signal positive going zeror crossing, utilize the TMS320F28335 capturing unit to its zero passage detection, utilize the enhancing seizure eCAP1 pin of DSP.While is as the sync break source of DSP.When the CPU interrupt, sampling transient current value in interrupt service routine, thus detect voltage, the current phase relation calculates power-factor angle and sends to touch-screen.Simultaneously this signal is also as the synchronizing signal of pulse generator.

The principle of voltage zero-crossing detection circuit comprises that resistance, electric capacity, voltage comparator LM311, optical-electrical converter TLP1A, not gate HD74HC14 form as shown in Figure 7.Wherein, the pin 1 of voltage transformer VSMO25A links to each other with VCC+15, the pin 2 of VSMO25A links to each other with VCC-15V, the pin 3 of VSMO25A respectively with R37 one end, R39 one end links to each other, the pin 4 of VSMO25A respectively with the R37 other end, R38 one end, the pin 3 of LM311, ground links to each other, the R38 other end respectively with the R39 other end, R40 one end links to each other, the R40 other end links to each other with the pin 2 of LM311, the pin 4 of LM311 meets VCC-12V, pin 1 ground connection of LM311, pin 7 and R41 one end of LM311, R43 one end links to each other, the pin 8 of LM311 respectively with VCC+12V, the R43 other end links to each other, the pin 1 of TLP1A respectively with the R41 other end, C51 one end links to each other, TLP1A pin 2 respectively with the C51 other end, ground link to each other, TLP1A pin 16 links to each other with VCC+3.3, pin 15 respectively with C52 one end, C53 one end, R42 one end, the pin 1 of HD74HC14 links to each other, the C52 other end, the R42 other end, the C53 other end is connected with each other and ground connection, and the pin 2 of HD74HC14 links to each other with DSP FPGA_CAP.

Synchronizing signal is taken from the A phase voltage of electrical network, voltage measuring transformer goes out the A phase voltage signal, this voltage signal is given voltage comparator LM311 through resistance R 37, R39 dividing potential drop after resistance R 40 current limlitings, and the signal of 7 pins output is and the square-wave signal of electrical network with the frequency homophase.When if this signal directly passes into DSP and FPGA driving force a little less than, therefore added the TLP521 optocoupler, on the one hand in order to strengthen driving force, strengthen on the other hand antijamming capability.Make the rising edge of 50Hz square-wave signal and trailing edge is steeper, slope is larger with TLL device HD74HC14, can be identified by controller through the square-wave signal that this detection obtains.

The SPWM pulse generation adopts the method for total digitalization to realize, its control principle is that triangular carrier and sinusoidal modulation wave are relatively exported the SPWM pulse, and triangular carrier is designed to the amplitude frequency and fixes, and the Sine Modulated wave frequency is constant, and amplitude is adjustable.Therefore can obtain the adjustable SPWM pulse of pulse duration through relatively exporting.It is the fpga chip of the field-programmable of EP3C40Q240C8 that pulse generating circuit adopts model.Utilize FPGA to produce driving pulse more reliable than adopting DSP generation pulse.Because adopt microprocessor to produce pulse, in case microprocessor crashes, need to reset and could work, the time is longer, and SVG must shut down.And adopt the FPGA programming to produce driving pulse, and FPGA can not restart, and also may be that an instruction makes mistakes even make mistakes, and can not cause whole FPGA work undesired, thus can not make SVG overcurrent, overvoltage occur yet, thereby need not to make SVG to shut down.Another major reason that adopts fpga chip is that the main circuit of SVG adopts 2H bridge cascade inverter circuit, and is difficult to realize the SPWM wave modulation for dsp chip, therefore adopts fpga chip.

Dsp processor is responsible for finishing the AD controlling of sampling and is calculated, go out index of modulation k according to compensate for reference instruction current i ' in the Direct Current Control algorithm and inverter output current i through the PI regulating and controlling, by serial communication index of modulation k is sent into FPGA, FPGA produces corresponding SPWM waveform.

The Optical Fiber Transmission schematic diagram of SPWM signal because master control borad easily is subjected to the strong electromagnetic of cascade 2H bridge inverter main circuit, for fear of this impact and isolated high-voltage signal and driving signal, adopts optical fiber to be used for the transmission of SPWM signal in design as shown in Figure 9.Formed by resistance, electric capacity, SN75451BD, HFRB1521.Wherein, SPWM_1A_L respectively with the pin 2 of SN75451BD, pin 1, pin 8, C54 one end, C55 one end, R43 one end, R45 one end links to each other, SPWM_1A_R respectively with R44 one end, the pin 7 of SN75451BD links to each other, VCC3V3 respectively with the R43 other end, the R44 other end links to each other, the pin 4 of SN75451BD is connected to the ground, the pin 3 of SN75451BD respectively with the R45 other end, the R46 other end, the pin 1 of U14 (HFRB1521) links to each other, the pin 5 of SN75451BD respectively with the R46 other end, the pin 1 of U15 (HFRB1521) links to each other, and the pin 2 of U14 (HFRB1521) is connected to the ground.

The major loop of native system adopts 2H bridge cascade inverter circuit, this main circuit is applied to the broad sense soft switch technique in the 2H bridge cascaded inverter, high efficiency and the energy saving of whole device have been improved, 2H bridge cascade multilevel inverter adopts the voltage-source type structure as the topological structure of major loop, with the triangle connected mode, in order to realize adjusting reactive power level and smooth from the perception to the capacitive, the effect of FC filter wherein is to suppress harmonic wave, prevents that circuit from producing resonance phenomena.Its main circuit topological structure as shown in Figure 8.

This reactive power compensation device is applied to the high-power occasion, adopts optical fiber to be used for the transmission of SPWM signal.Its operation principle converts pulse signal to light signal and drives IGBT as shown in Figure 9 in transmission course.The SPWM pulse signal that the FPGA1 controller produces, signal enters optical fiber through fiber optic transmitter HFBR-1521, and along Optical Fiber Transmission to optical receiver HFBR-2521, the principle of its optical receiver HFBR-2521 is similar to optical transmitter.

In this device, therefore the asymmetric condition of voltage non-sine and load improves i _p-i _qEtection theory, principle are as shown in figure 12.Angle values φ during with the system voltage saltus step is added in the Detecting Reactive Current process this theory in conjunction with the d-q etection theory, can detect voltage arbitrarily like this, can detect when system and break down or phase hit during the oscillating voltage rapid drawdown, add traditional i _p-i _qTo the real-time detection of harmonic wave and reactive current, eliminated the impact of fractional harmonic.Simultaneously in order to guarantee that the SVG device effectively carries out full remuneration to idle and harmonic wave, in testing process, add again the detection of dc capacitor voltage, kept improved i under the stable prerequisite at the inverter direct-flow side capacitance voltage _p-i _qMethod can accurately detect.

Adopt described method of carrying out reactive power compensation based on the direct hanging type reactive power compensation device of 10kV electrical network, flow process such as Figure 14 may further comprise the steps:

Step 1: current transformer and voltage transformer be transient current and the instantaneous voltage of the three-phase inverter side of Real-time Collection 10kV electrical network respectively, and transient current and instantaneous voltage are transferred to master control set through the AD sampling plate;

Step 2: master control set is according to transient current i _A, i _B, i _CWith instantaneous voltage u _A, u _B, u _CThe 10kV electrical network is carried out Detecting Reactive Current, obtain the reactive power compensation electric current;

Step 2.1: transient current and the instantaneous voltage that collects carried out the d-q coordinate transform, be about to d-q coordinate system and three-dimensional cartesian coordinate system and carry out synchronous rotary with the first-harmonic angular frequency, obtain instantaneous active current i _p, instantaneous reactive current i _q, the d axle component of voltage and the q axle component of voltage;

The instantaneous voltage u of three-phase _A, u _B, u _CD-q coordinate transform formula as follows

$\left[\begin{array}{c}{u}_d\\ u_q\end{array}\right]=T_{\mathrm{ABC}/\mathrm{dq}}\left[\begin{array}{c}{u}_A\\ u_B\\ u_C\end{array}\right]---\left(3\right)$

$\left[\begin{array}{c}{i}_d\\ i_q\end{array}\right]=T_{\mathrm{dq}/\mathrm{ABC}}\left[\begin{array}{c}{i}_A\\ i_B\\ i_C\end{array}\right]---\left(4\right)$

$T_{\mathrm{ABC}/\mathrm{dq}}=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}\cos \mathrm{\&theta;}& \cos (\mathrm{\&theta;}-\frac{2}{3}\mathrm{\&pi;})& \cos (\mathrm{\&theta;}+\frac{2}{3}\mathrm{\&pi;})\\ \sin \mathrm{\&theta;}& \sin (\mathrm{\&theta;}-\frac{2}{3}\mathrm{\&pi;})& \sin (\mathrm{\&theta;}+\frac{2}{3}\mathrm{\&pi;})\end{array}\right]---\left(5\right)$

Wherein, respective corners θ=ω t, T _ABC/dqConversion coefficient for d-q coordinate system and three-dimensional cartesian coordinate system;

Obtain voltage d axle component u according to the voltage d-q coordinate transform formula of formula (3) _dWith q axle component u _q, isolate DC component through low pass filter LPF again

,

Can obtain:

${\stackrel{\&OverBar;}{u}}_d=\sqrt{\frac{3}{2}}U\sin \mathrm{\&phi;}---\left(6\right)$

${\stackrel{\&OverBar;}{u}}_q=\sqrt{\frac{3}{2}}U\cos \mathrm{\&phi;}---\left(7\right)$

Step 2.2: according to instantaneous active current i _p, instantaneous reactive current i _q, the d axle component of voltage and voltage q axle component obtain amplitude and the phase place of fundamental voltage;

The amplitude U of fundamental voltage is expressed as follows:

$U=\sqrt{\frac{2}{3}}\sqrt{{\stackrel{\&OverBar;}{u}}_{\mathrm{<figure-callout\; id="2"\; label="d"\; filenames="HDA00003341420600012.png,HDA00003341420600021.png"\; state="\{\{state\}\}">d</figure-callout>}}^2+{\stackrel{\&OverBar;}{u}}_q^2}---\left(8\right)$

The phase of fundamental voltage is expressed as follows:

$\mathrm{\&phi;}=\arcsin \frac{\sqrt{2}{\stackrel{\&OverBar;}{u}}_d}{\sqrt{3U}}=\arcsin =\frac{{\stackrel{\&OverBar;}{u}}_d}{\sqrt{{\stackrel{\&OverBar;}{u}}_{\mathrm{<figure-callout\; id="2"\; label="d"\; filenames="HDA00003341420600012.png,HDA00003341420600021.png"\; state="\{\{state\}\}">d</figure-callout>}}^2+{\stackrel{\&OverBar;}{u}}_q^2}}---\left(9\right)$

Step 2.3: adopt the phase place of phase-locked loop (PLL) locking A phase instantaneous voltage, produce synchronizing signal sin θ and the cos θ of instantaneous voltage, and then produce the transition matrix C between d-q coordinate system and the clarke conversion ₂

$\left[\begin{array}{c}{i}_{\mathrm{\&alpha;}}\\ i_{\mathrm{\&beta;}}\end{array}\right]=C_1\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right]$ $\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right]=C_1^{-1}\left[\begin{array}{c}{i}_{\mathrm{\&alpha;}}\\ i_{\mathrm{\&beta;}}\end{array}\right]---\left(10\right)$

Wherein, C ₁Be the transition matrix of clarke conversion and three-dimensional cartesian coordinate system, ${\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="HDA00003341420600012.png,HDA00003341420600021.png"\; state="\{\{state\}\}">C</figure-callout>}}_1=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}1& -\frac{1}{2}& -\frac{1}{2}\\ 0& \frac{\sqrt{3}}{2}& -\frac{\sqrt{3}}{2}\end{array}\right]$

$C_1^{-1}=C_1^T=\sqrt{\frac{2}{3}}\left[\begin{array}{cc}1& 0\\ -\frac{1}{2}& \frac{\sqrt{3}}{2}\\ -\frac{1}{2}& -\frac{\sqrt{3}}{2}\end{array}\right]$

$\left[\begin{array}{c}{i}_p\\ i_q\end{array}\right]=C_2\left[\begin{array}{c}{i}_{\mathrm{\&alpha;}}\\ i_{\mathrm{\&beta;}}\end{array}\right]---\left(11\right)$

Then, the transition matrix between d-q coordinate system and the clarke conversion $C_{}$ ${}_2=\left[\begin{array}{cc}\sin \mathrm{\&theta;}& -\cos \mathrm{\&theta;}\\ -\cos \mathrm{\&theta;}& -\sin \mathrm{\&theta;}\end{array}\right];$

Step 2.4: with the synchronizing signal of instantaneous voltage and the Phase Stacking of fundamental voltage, the d-q coordinate system that step of updating 2.3 produces and the transition matrix between the clarke conversion, and then obtain the reactive power compensation electric current;

With C ₂In θ be improved to θ ^*=θ+φ, soon synchronizing signal and the Phase Stacking of fundamental voltage, the then C of instantaneous voltage ₂Be updated to C ' ₂

${\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA00003341420600012.png,HDA00003341420600021.png"\; state="\{\{state\}\}">C</figure-callout>}}_2^{\&prime;}=\left[\begin{array}{cc}\sin {\mathrm{\&theta;}}^{*}& -\cos {\mathrm{\&theta;}}^{*}\\ -\cos {\mathrm{\&theta;}}^{*}& -\sin {\mathrm{\&theta;}}^{*}\end{array}\right]---\left(12\right)$

Conversion formula between d-q coordinate system and the clarke conversion is

$\left[\begin{array}{c}{i}_p^{\&prime;}\\ i_q^{\&prime;}\end{array}\right]={\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA00003341420600012.png,HDA00003341420600021.png"\; state="\{\{state\}\}">C</figure-callout>}}_2^{\&prime;}\left[\begin{array}{c}{i}_{\mathrm{\&alpha;}}\\ i_{\mathrm{\&beta;}}\end{array}\right]---\left(13\right)$

Instantaneous active power component i ' _pWith instantaneous reactive power component i ' _qObtain DC component through low pass filter

Disconnect the reactive power component Isolating the fundamental active current component is:

$\left[\begin{array}{c}{i}_{\mathrm{Af}}^{\&prime;}\\ i_{\mathrm{Bf}}^{\&prime;}\\ i_{\mathrm{Cf}}^{\&prime;}\end{array}\right]=C_1^{-1}\left[\begin{array}{c}{i}_{\mathrm{\&alpha;f}}\\ i_{\mathrm{\&beta;f}}\end{array}\right]=C_1^{-1}{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="HDA00003341420600012.png,HDA00003341420600021.png"\; state="\{\{state\}\}">C</figure-callout>}}_2^{\&prime;}\left[\begin{array}{c}{\stackrel{\&OverBar;}{i}}_p^{\&prime;}\\ 0\end{array}\right]---\left(14\right)$

Then the reactive power compensation electric current is:

$\left[\begin{array}{c}{i}_A^{\&prime;}\\ i_B^{\&prime;}\\ i_C^{\&prime;}\end{array}\right]=\left[\begin{array}{c}{i}_A\\ i_B\\ i_C\end{array}\right]-\left[\begin{array}{c}{i}_{\mathrm{Af}}^{\&prime;}\\ i_{\mathrm{Bf}}^{\&prime;}\\ i_{\mathrm{Cf}}^{\&prime;}\end{array}\right]---\left(15\right)$

Step 3: the difference DELTA i that calculates the transient current of reactive power compensation electric current and three-phase inverter side, this difference is carried out the PI adjusting and current signal is converted to voltage signal, and the voltage triangular carrier in this voltage signal and the pulse generator is compared output SPWM pulse;

Triangular carrier compares control principle as shown in figure 13, compare with triangular carrier again after the difference DELTA i of the transient current of reactive power compensation electric current and three-phase inverter side regulated through PI, by pi regulator current signal is converted to voltage signal, and then compares output SPWM impulse wave with the voltage triangular wave.After the chain rate that stagnates, add d type flip flop, realize timing clock signal, guarantee a triangular carrier in the cycle IGBT on off state on the same brachium pontis remain unchanged so that the switching frequency of IGBT is constantly equal to the period frequency of triangular carrier.Wherein, PI gets through calculating:

$\left\{\begin{array}{c}{k}_p=\frac{L_o{\mathrm{\&omega;}}_{\mathrm{\&Delta;}}}{{2u}_{\mathrm{dc}}}\\ k_I={\mathrm{\&omega;}}_{\mathrm{\&Delta;}}\&CenterDot;k_p\end{array}\right.---\left(13\right)$

Wherein, k _pBe the proportionality coefficient of pi regulator, k _IBe the integral coefficient of pi regulator, L _oBe load, ω _ΔBe triangular carrier angular frequency, u _DcBe inversion side dc capacitor voltage.

Step 4: pulse generator adopts the SPWM control method of triangular carrier homophase stacked switch frequency optimization to produce the SPWM pulse of optimizing to the SPWM pulse of more afterwards output, and the SPWM pulse of optimizing is added a zero-sequence component u _Z, the SPWM pulse of optimizing is revised, obtain the SPWM pulse of reactive power compensation, the pulse generator logic diagram is as shown in figure 11;

With 2 amplitudes and frequency all identical triangular carrier be layered in transverse axis upside and downside, add zero-sequence component u with one again _ZSinusoidal modulation wave compare, thereby produce the SPWM impulse waveform

$u_Z=\frac{1}{2}[{(u_A,u_B,u_C)}_{\max }+{(u_A,u_B,u_C)}_{\min }]---\left(14\right)$

Wherein, u _A, u _B, u _CBe respectively A phase, the B phase of 10kV electrical network, the instantaneous voltage of C phase;

Step 5: the SPWM pulse signal of reactive power compensation distributes through the pulse distribution plate, and when detecting zero point, triggers voltage zero-cross as shown in figure 10 2H bridge cascade inverter circuit, when 2H bridge cascade inverter circuit produces fault, fault-signal is fed back to master control set, and quitting work, otherwise execution in step 6;

The signal of step 6:2H bridge cascade inverter circuit output carries out reactive power compensation to the 10kV electrical network behind the FC filter filtering;

The reactive power compensation status data of step 7:10kV electrical network transfers to communication control unit by the IO plate, and communication control unit is passed to PLC with data again, and PLC crosses touch-screen with data communication device again and shows.

Claims (4)

1. A direct-mounted reactive power compensation device based on a 10kV power grid, characterized in that it includes a current transformer, a voltage transformer, an AD sampling board, a main control device, a voltage zero-crossing detection circuit, a communication control device, and a pulse generator Device, pulse distribution board, SPWM signal transmission circuit, 2H bridge cascaded inverter circuit, filter, PLC, touch screen and IO board; The AD sampling board includes a current conditioning circuit, a voltage conditioning circuit and an AD sampling chip; The input end of the current transformer and the input end of the voltage transformer are all connected to the 10kV power grid, the output end of the current transformer is connected to the input end of the current conditioning circuit, and the output end of the voltage transformer is connected to the input end of the voltage conditioning circuit. The output terminal of the conditioning circuit and the output terminal of the voltage conditioning circuit are connected to the input terminal of the AD sampling chip, and the output terminal of the AD sampling chip is connected to the input terminal of the main control device, and the main control device is respectively connected with the communication control device, the pulse generator, the The voltage zero-crossing detection circuit is connected to the 2H bridge cascaded inverter circuit, the communication control device is connected to the PLC, the PLC is connected to the touch screen, the output end of the pulse generator is connected to the input end of the pulse distribution board, and the output end of the pulse distribution board is connected to the SPWM signal transmission circuit The input end of the SPWM signal transmission circuit is connected to the input end of the 2H bridge cascaded inverter circuit, the output end of the 2H bridge cascaded inverter circuit is connected to the input end of the filter, and the output end of the filter is connected to the 10kV grid. The other input end of the 2H bridge cascaded inverter circuit is connected to the output end of the IO board, and the other output end of the IO board is connected to the communication control device. 2. The direct-mounted reactive power compensation device based on 10kV power grid according to claim 1, characterized in that: the communication control device and the pulse generator both use FPGA. 3. The direct-mounted reactive power compensation device based on 10kV power grid according to claim 1, characterized in that: the communication control device is used to receive the reactive power compensation status data of the 10kV power grid fed back by the IO board and This data is transmitted to the touch screen display device. 4. adopting the method for reactive power compensation based on the direct-mounted reactive power compensation device of 10kV power grid according to claim 1, it is characterized in that: comprising the following steps: Step 1: The current transformer and the voltage transformer respectively collect the instantaneous current and instantaneous voltage of the three-phase inverter side of the 10kV power grid in real time, and transmit the instantaneous current and instantaneous voltage to the main control device through the AD sampling board; Step 2: The main control device detects the reactive current of the 10kV power grid according to the instantaneous current and instantaneous voltage, and obtains the reactive power compensation current; Step 2.1: Perform dq coordinate transformation on the collected instantaneous current and instantaneous voltage, that is, the dq coordinate system and the three-dimensional Cartesian coordinate system are rotated synchronously at the fundamental angular frequency ω to obtain the instantaneous active current i _p , instantaneous reactive current i _q , The d-axis component of the voltage and the q-axis component of the voltage; Step 2.2: Obtain the amplitude and phase of the fundamental voltage according to the instantaneous active current i _p , the instantaneous reactive current i _q , the d-axis component of the voltage, and the q-axis component of the voltage; Step 2.3: Use a phase-locked loop to lock the phase of the instantaneous voltage of phase A, generate synchronous signals sinθ and cosθ of the instantaneous voltage, and then generate a conversion matrix between the d-q coordinate system and the Clarke transformation; Step 2.4: superimpose the synchronous signal of the instantaneous voltage and the phase of the fundamental voltage, update the conversion matrix between the d-q coordinate system and the Clarke transformation generated in step 2.3, and then obtain the reactive power compensation current; Step 3: Calculate the difference between the reactive power compensation current and the instantaneous current on the three-phase inverter side, perform PI adjustment on the difference and convert the current signal into a voltage signal, and compare the voltage signal with the The voltage triangular carrier is compared to output the SPWM pulse; Step 4: The pulse generator uses the SPWM control method optimized by the triangular carrier in-phase stacked switching frequency to generate the optimized SPWM pulse for the SPWM pulse output after the comparison, and adds a zero-sequence component u _Z to the optimized SPWM pulse, and performs the optimization on the optimized SPWM pulse Amended to obtain SPWM pulses for reactive power compensation; ${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; Z</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; [</span>{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; max</span>}}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; A</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; min</span>}}<span\; class="notranslate">\; ]</span>$ Step 5: The SPWM pulse signal for reactive power compensation is distributed through the pulse distribution board, and the 2H bridge cascaded inverter circuit is triggered when the voltage crosses zero to detect the zero point. When the 2H bridge cascaded inverter circuit fails, the fault signal is fed back to the main control device and stop working, otherwise go to step 6; Step 6: After the signal output by the 2H bridge cascaded inverter circuit is filtered by the filter, reactive power compensation is performed on the 10kV power grid; Step 7: The reactive power compensation status data of the 10kV power grid is transmitted to the communication control device through the IO board, and the communication control device transmits the data to the PLC, and the PLC displays the data through the touch screen.

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