CN103324581A - Programming storage unit, data reading method, memorizer controller and storage device - Google Patents
Programming storage unit, data reading method, memorizer controller and storage device Download PDFInfo
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- CN103324581A CN103324581A CN2012100797151A CN201210079715A CN103324581A CN 103324581 A CN103324581 A CN 103324581A CN 2012100797151 A CN2012100797151 A CN 2012100797151A CN 201210079715 A CN201210079715 A CN 201210079715A CN 103324581 A CN103324581 A CN 103324581A
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Abstract
The invention provides a programming storage unit, a data reading method, a memorizer controller and a storage device. The method for a programming storage unit is applicable in a rewritable nonvolatile memorizer module, and includes the following steps: receiving a command for indicating the alternation for a logical page; recognizing an invalid logical access address and a valid logical access address in the logical page as per the command; as well as the steps of selecting a physical page; setting the mark corresponding to the valid logical access address as a valid state and the mark corresponding to the invalid logical access address as an invalid state; programming marks and data belonging to the valid logical access address to the selected physical page as per the alternation operation; mapping the physical page to the logical page. Therefore, the method can effectively increase the speed of the programming storage unit.
Description
Technical field
The present invention relates to a kind of method and method for reading data of memory cells, particularly relate to a kind of method, the method for reading data that indicates the memory cells that increases execution speed and memorizer memory devices and Memory Controller that uses these methods of utilizing.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that the consumer is to the also rapidly increase of demand of Storage Media.Because can rewrite formula nonvolatile memory (for example, flash memory) and have that data are non-volatile, power saving, volume be little, and the characteristic such as machinery-free structure is so be built in the above-mentioned various portable multimedia devices of giving an example in being fit to very much.
In general, can rewrite the formula nonvolatile memory and comprise a plurality of physical blocks, each physical blocks comprises a plurality of physical pages.And when writing to data can rewrite the formula nonvolatile memory time, physical page is the minimum unit of writing.Therefore, when data that will write during less than physical page big or small, the wiring method that prior art proposes is to insert preset value in physical page, to fill up a physical page.When will from can rewrite formula nonvolatile memory reading out data the time, also reading in the lump these preset values.Yet, in above-mentioned situation, be used for controller that control can rewrite the formula nonvolatile memory these preset values of must encoding, and with these preset values programmings (program) to physical page.Yet it is deleted for the data that were not used or were stored in these logical addresses that host computer system is logically identified these logical addresses that store preset value.So, these preset values are programmed to can to rewrite the formula nonvolatile memory be insignificant and can extra increase system burden.
So, data of the discontented physical page of access in can rewriteeing the formula nonvolatile memory effectively how, the subject under discussion of being concerned about for those skilled in the art.
Summary of the invention
Exemplary embodiment of the present invention proposes a kind of method, method for reading data, Memory Controller and memorizer memory devices of memory cells, can increase the execution speed when reading and writing data.
Propose a kind of method of memory cells in the present invention's one exemplary embodiment, be used for one and can rewrite the formula non-volatile memory module.This can rewrite the formula non-volatile memory module and comprise a plurality of physical pages, and each physical page comprises a data bit district and a redundant digit district.Wherein, the data bit district also comprises a plurality of physics access address, and the redundant digit district then records a plurality of signs of corresponding these physics access addresses respectively.Wherein, a plurality of logical page (LPAGE)s can be configured to shine upon the physical page of part, and each logical page (LPAGE) has a plurality of logics access address.The method of this memory cells comprises: receive an instruction, this instruction is in order to indication the first logical page (LPAGE) among the above-mentioned logical page (LPAGE) to be carried out an alter operation; Identify invalid logic access address and effective logic access address among the logic access address of the first logical page (LPAGE) according to the instruction that receives; From above-mentioned a plurality of physical pages, select first physical page.The method of this memory cells also comprises: the sign of effective logic access address of corresponding the first logical page (LPAGE) is set as effective status, the sign of the invalid logic access address of corresponding the first logical page (LPAGE) is set as a disarmed state; According to the data bit district of above-mentioned alter operation with data programing to the first physical page of effective logic access address of corresponding the first logical page (LPAGE), and the sign of effective logic access address of corresponding the first logical page (LPAGE) and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) are programmed to the redundant digit district of the first physical page; And, the first physical page is mapped to the first logical page (LPAGE).
In an exemplary embodiment, the first above-mentioned logical page (LPAGE) is original mappings to the second physical page, and the second physical page stores the data of the logic access address that belongs to the first logical page (LPAGE).Wherein, above-mentioned instruction is that a housekeeping instruction (trim command) and above-mentioned alter operation are to indicate at least one first logic access address among the logic access address of the first logical page (LPAGE) for deleting the logic access address.Wherein, the invalid logic access address of identifying among the logic access address of the first logical page (LPAGE) according to instruction comprises with the effective step of logic access address: according to above-mentioned housekeeping instruction the first logic access address of the first logical page (LPAGE) is identified as invalid logic access address.Wherein, also comprise according to the step of alter operation with the data bit district of data programing to the first physical page of effective logic access address of corresponding the first logical page (LPAGE): the data that from the second physical page, read the effective logic access address that belongs to the first logical page (LPAGE); And, the data that will belong to effective logic access address of the first logical page (LPAGE) write to the first physics access address among the physics access address in data bit district of the first physical page, and wherein the sign of effective logic access address of corresponding the first logical page (LPAGE) is to correspond to the first physics access address.
In an exemplary embodiment, the method of above-mentioned memory cells also comprises: set up an idle logical address table, the logic access address that belongs to a kind of idle state in order to record wherein belongs to the logic access address of idle state for not write the logic access address of data or the stored deleted logic access address of data.
In an exemplary embodiment, above-mentioned instruction be one write instruction and above-mentioned alter operation for indication with one more new data write to more new logic access address among the logic access address of the first logical page (LPAGE).Wherein, the invalid logic access address of identifying among the logic access address of the first logical page (LPAGE) according to instruction comprises with the effective step of logic access address: judge whether in other logic access addresses except new logic access address more among the logic access address of the first logical page (LPAGE) be logic access address or the deleted logic access address of not write; And, if above-mentioned other logic access addresses when not write the logic access address or having deleted the logic access address, are identified as invalid logic access address with these other logic access addresses.
In an exemplary embodiment, above-mentionedly comprise according to the step of alter operation with the data bit district of data programing to the first physical page of effective logic access address of corresponding the first logical page (LPAGE): above-mentioned more new data is write at least one the second physics access address among the physics access address in data bit district of the first physical page, wherein the sign of effective logic access address of corresponding the first logical page (LPAGE) is to correspond to the second above-mentioned physics access address.
In an exemplary embodiment, the method for above-mentioned memory cells comprises that also encrypting more new data has encrypted more new data to produce one.Wherein, comprise according to the step of alter operation with the data bit district of data programing to the first physical page of effective logic access address of corresponding the first logical page (LPAGE): will encrypt new data more and write to the second physics access address among the physics access address in data bit district of the first physical page.
With the another one angle, a kind of method for reading data is proposed in the present invention's one exemplary embodiment, be used for above-mentioned rewritten formula non-volatile memory module.The notebook data read method comprises: receive a reading command from a host computer system, this reading command is to read the data that belong to the second logic access address among the above-mentioned logic access address in order to indication; Read data the 3rd physics access address in the data bit district of the first physical page among above-mentioned physical page, and the data that belong to the second logic access address are to be stored in the 3rd physics access address in data bit district of the first physical page.The notebook data read method also comprises: whether the sign of judging corresponding the 3rd physics access address in the redundant digit district that is recorded in the first physical page is disarmed state; If it is non-during for disarmed state to be recorded in the sign of corresponding the 3rd physics access address in the redundant digit district of the first physical page, the data that will read from the 3rd physics access address in the data bit district of the first physical page send host computer system to; And, if be recorded in corresponding the 3rd physics access address in the redundant digit district of the first physical page be masked as disarmed state the time, then send a preset value to host computer system.
In an exemplary embodiment, above-mentioned method for reading data also comprises: the data that deciphering is read from the 3rd physics access address in the data bit district of the first physical page are to obtain a data decryption; And, this data decryption is sent to host computer system to respond above-mentioned reading command.
With the another one angle, a kind of memorizer memory devices proposed in the present invention's one exemplary embodiment, comprised connector, above-mentioned rewritten formula non-volatile memory module and Memory Controller.Wherein, connector is to be electrically connected to a host computer system.Memory Controller then is to be electrically connected to above-mentioned connector and can to rewrite the formula non-volatile memory module.And Memory Controller is in order to receive an instruction, and this instruction is in order to indication the first logical page (LPAGE) among the above-mentioned logical page (LPAGE) to be carried out an alter operation.Memory Controller also can be identified invalid logic access address and effective logic access address among the logic access address of the first logical page (LPAGE) according to this instruction, and selects the first physical page from physical page.Memory Controller also can be set as an effective status with the sign of effective logic access address of corresponding the first logical page (LPAGE), and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) is set as a disarmed state.In addition, Memory Controller also can be according to the data bit district of above-mentioned alter operation with data programing to the first physical page of effective logic access address of corresponding the first logical page (LPAGE), sign and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) of effective logic access address of corresponding the first logical page (LPAGE) is programmed to the redundant digit district of the first physical page.At last, Memory Controller can map to the first logical page (LPAGE) with the first physical page.
In an exemplary embodiment, the first above-mentioned logical page (LPAGE) is original mappings to the second physical page, and the second physical page then stores the data of the logic access address that belongs to the first logical page (LPAGE).Above-mentioned instruction is that housekeeping instruction (trim command) and above-mentioned alter operation are to indicate at least one first logic access address among the logic access address of the first logical page (LPAGE) for deleting the logic access address.Wherein, Memory Controller can be identified as invalid logic access address with the first logic access address of the first logical page (LPAGE) according to housekeeping instruction, and reads the data of the effective logic access address that belongs to the first logical page (LPAGE) from the second physical page.In according to the process of alter operation with the data bit district of data programing to the first physical page of effective logic access address of corresponding the first logical page (LPAGE), Memory Controller also can write to the data that belong to effective logic access address of the first logical page (LPAGE) the first physics access address among the physics access address in data bit district of the first physical page, and wherein the sign of effective logic access address of corresponding the first logical page (LPAGE) is to correspond to the first physics access address.
In an exemplary embodiment, above-mentioned Memory Controller also in order to set up an idle logical address table, belongs to a kind of logic access address of idle state in order to record.Wherein, belong to the logic access address of idle state for not write the logic access address of data or the stored deleted logic access address of data.
In an exemplary embodiment, above-mentioned instruction writes instruction for indication with one, and above-mentioned alter operation be in order to one more new data write to more new logic access address among the logic access address of the first logical page (LPAGE).Wherein, whether Memory Controller is also in order to judge in other logic access addresses except new logic access address more among the logic access address of the first logical page (LPAGE) for not write the logic access address or having deleted the logic access address.If above-mentioned other logic access addresses were not when being write the logic access address or having deleted the logic access address, Memory Controller can be identified as invalid logic access address with these other logic access addresses.
In an exemplary embodiment, Memory Controller also can write to new data more the second physics access address among the physics access address in data bit district of the first physical page, and wherein the sign of effective logic access address of corresponding the first logical page (LPAGE) is to correspond to described the second physics access address.
In an exemplary embodiment, above-mentioned Memory Controller has also been encrypted more new data in order to encrypt more new data to produce one.Memory Controller also can be with the second physics access address of encrypting new data more and write among the physics access address in data bit district of the first physical page, and wherein the sign of effective logic access address of corresponding the first logical page (LPAGE) is to correspond to described the second physics access address.
In an exemplary embodiment, also in order to receive a reading command from host computer system, this reading command is to read the data that belong to the second logic access address in order to indication to above-mentioned Memory Controller.Memory Controller is also in order to reading out data from the 3rd physics access address in the data bit district of the first physical page, and the data that belong to the second logic access address are to be stored in the 3rd physics access address in data bit district of the first physical page.Whether Memory Controller is disarmed state in order to the sign that judgement is recorded in corresponding the 3rd physics access address in the redundant digit district of the first physical page also.If it is non-during for disarmed state to be recorded in the sign of corresponding the 3rd physics access address in the redundant digit district of the first physical page, Memory Controller can send the data that read to host computer system from the 3rd physics access address in the data bit district of the first physical page.If be recorded in corresponding the 3rd physics access address in the redundant digit district of the first physical page be masked as disarmed state the time, Memory Controller can send a preset value to host computer system.
In an exemplary embodiment, the data that above-mentioned Memory Controller also reads from the 3rd physics access address in the data bit district of the first physical page in order to deciphering to be obtaining a data decryption, and this data decryption is sent to host computer system to respond reading command.
With the another one angle, a kind of Memory Controller is proposed in the present invention's one exemplary embodiment, be used for controlling above-mentioned rewritten formula non-volatile memory module.This Memory Controller comprises host interface, memory interface and memory management circuitry.Wherein, host interface is to be electrically connected to a host computer system.Memory interface is to be electrically connected to rewrite the formula non-volatile memory module.Memory management circuitry then is electrically connected to host interface and memory interface, and receives an instruction from host computer system, and this instruction is in order to indication the first logical page (LPAGE) among the above-mentioned logical page (LPAGE) to be carried out an alter operation.Wherein, memory management circuitry can be identified invalid logic access address and effective logic access address among the logic access address of the first logical page (LPAGE) according to this instruction, and can select the first physical page from above-mentioned physical page.Memory management circuitry also is set as effective status with the sign of effective logic access address of corresponding the first logical page (LPAGE), and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) is set as disarmed state.Memory management circuitry is also in order to according to the data bit district of above-mentioned alter operation with data programing to the first physical page of effective logic access address of corresponding the first logical page (LPAGE), sign and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) of effective logic access address of corresponding the first logical page (LPAGE) is programmed to the redundant digit district of the first physical page.At last, memory management circuitry can map to the first logical page (LPAGE) with the first physical page.
In an exemplary embodiment, the first above-mentioned logical page (LPAGE) is original mappings to the second physical page, and the second physical page then stores the data of the logic access address that belongs to the first logical page (LPAGE).To indicate at least one first logic access address among the logic access address of the first logical page (LPAGE) for deleting the logic access address and above-mentioned instruction is a housekeeping instruction (trim command) and above-mentioned alter operation.Wherein, memory management circuitry can be identified as an invalid logic access address with the first logic access address of the first logical page (LPAGE) according to this housekeeping instruction, and reads the data of the effective logic access address that belongs to the first logical page (LPAGE) from the second physical page.Memory management circuitry also writes to the first physics access address among the physics access address in data bit district of the first physical page in order to the data of effective logic access address that will belong to the first logical page (LPAGE), and the sign of effective logic access address of corresponding the first logical page (LPAGE) is to correspond to described the first physics access address.
In an exemplary embodiment, above-mentioned memory management circuitry also in order to set up an idle logical address table, belongs to the logic access address of kind of an idle state in order to record.Wherein, belong to the logic access address of idle state for not write the logic access address of data or the stored deleted logic access address of data.
In an exemplary embodiment, above-mentioned instruction is one and writes instruction, and above-mentioned alter operation be in order to indication with one more new data write to more new logic access address among the logic access address of the first logical page (LPAGE).Wherein, whether memory management circuitry is also in order to judge in other logic access addresses except new logic access address more among the logic access address of the first logical page (LPAGE) for not write the logic access address or having deleted the logic access address.If above-mentioned other logic access addresses were not when being write the logic access address or having deleted the logic access address, memory management circuitry can be identified as invalid logic access address with these other logic access addresses.
In an exemplary embodiment, memory management circuitry also in order to will be more new data write in the second physics access address among the physics access address in data bit district of the first physical page.Wherein, the sign of effective logic access address of corresponding the first logical page (LPAGE) is to correspond to described the second physics access address.
In an exemplary embodiment, above-mentioned Memory Controller also comprises an encrypting and decrypting circuit, has encrypted more new data in order to encrypt more new data to produce one.Memory management circuitry can be with the second physics access address of encrypting new data more and write among the physics access address in data bit district of the first physical page.And the sign of effective logic access address of corresponding the first logical page (LPAGE) is to correspond to described the second physics access address.
In an exemplary embodiment, also in order to receive a reading command from host computer system, this reading command is to read to belong to the data of the second logic access address in order to indication to above-mentioned memory management circuitry.Wherein memory management circuitry is also in order to reading out data from the 3rd physics access address in the data bit district of the first physical page.The data that wherein belong to the second logic access address are to be stored in the 3rd physics access address in data bit district of the first physical page.And whether memory management circuitry is disarmed state in order to the sign that judgement is recorded in corresponding the 3rd physics access address in the redundant digit district of the first physical page also.If it is non-during for disarmed state to be recorded in the sign of corresponding the 3rd physics access address in the redundant digit district of the first physical page, memory management circuitry can send the data that read to host computer system from the 3rd physics access address in the data bit district of the first physical page.If be recorded in corresponding the 3rd physics access address in the redundant digit district of the first physical page be masked as disarmed state the time, memory management circuitry can send a preset value to host computer system.
In an exemplary embodiment, above-mentioned Memory Controller also comprises an encrypting and decrypting circuit, and the data that read from the 3rd physics access address in the data bit district of the first physical page in order to deciphering are to obtain a data decryption.And memory management circuitry is also in order to be sent to this data decryption host computer system to respond reading command.
Based on above-mentioned, Memory Controller and the memorizer memory devices of the method for the memory cells that the present invention's one exemplary embodiment proposes and use the method, be sign corresponding to record in the redundant digit district, avoid thus the meaningless speed that writes running and lifting data writing.In addition, Memory Controller and the memorizer memory devices of the method for reading data that the present invention's one exemplary embodiment proposes and use the method, can avoid the meaningless running of reading by the sign in the identification redundant digit district, promote thus the speed of reading out data.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Figure 1A is host computer system and the memorizer memory devices that illustrates according to the first exemplary embodiment.
Figure 1B is the schematic diagram of the computing machine, input/output device and the memorizer memory devices that illustrate according to the first exemplary embodiment.
Fig. 1 C is the host computer system that illustrates according to the first exemplary embodiment and the schematic diagram of memorizer memory devices.
Fig. 2 is the summary calcspar that illustrates the memorizer memory devices shown in Figure 1A.
Fig. 3 is the summary calcspar of the Memory Controller that illustrates according to the first exemplary embodiment.
Fig. 4 and Fig. 5 are the example schematic that can rewrite the formula non-volatile memory module according to the management that the first exemplary embodiment illustrates.
Fig. 6 is the logical blocks that illustrates according to the first exemplary embodiment and the mapping schematic diagram of physical blocks.
Fig. 7 is the logical page (LPAGE) that illustrates according to the first exemplary embodiment and the mapping schematic diagram of physical page.
Fig. 8 is the process flow diagram of the method for reading data that illustrates according to the first exemplary embodiment.
Fig. 9 is the process flow diagram of the method for the memory cells that illustrates according to the first exemplary embodiment.
Figure 10 illustrates the process flow diagram of carrying out housekeeping instruction according to the first exemplary embodiment.
Figure 11 illustrates the example schematic of carrying out housekeeping instruction according to the first exemplary embodiment.
Figure 12 illustrates according to the first exemplary embodiment to carry out the process flow diagram that writes instruction.
Figure 13 illustrates according to the first exemplary embodiment to carry out the example schematic that writes instruction.
Figure 14 is the calcspar of the Memory Controller that illustrates according to the second exemplary embodiment.
Figure 15 is the schematic diagram that explanation will be upgraded data encryption and write according to the second exemplary embodiment.
Figure 16 is that the also schematic diagram of data decryption is read in explanation according to the second exemplary embodiment.
The reference numeral explanation
1000: host computer system
1100: computing machine
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1252: printer
1256: portable disk
1214: storage card
1216: solid state hard disc
1310: digital camera
The 1312:SD card
The 1314:MMC card
1316: memory stick
The 1318:CF card
1320: embedded storage device
100: memorizer memory devices
102: connector
104: Memory Controller
106: can rewrite the formula non-volatile memory module
304 (0)～304 (R): physical blocks
202: memory management circuitry
206: memory interface
254: electric power management circuit
252: memory buffer
256: bug check and correcting circuit
402: the data field
404: idle district
406: system region
408: replace the district
LBA (0)～LBA (N): logical blocks
502 (0)～502 (A): logical page (LPAGE)
522 (0)～522 (A): physical page
540 (0)～540 (3): the logic access address
562: the data bit district
582: the redundant digit district
560 (0)～560 (3): the physics access address
580 (0)～580 (3): sign
622 (0): physical page
662: the data bit district
682: the redundant digit district
S802, S804, S806, S808, S810: the step of method for reading data
S902, S904, S906, S908, S910, S912: the step of the method for memory cells
S1002, S1004, S1006, S1008, S1010, S1012, S1014: the step of carrying out housekeeping instruction
660 (0)～660 (3): the physics access address
680 (0)～680 (3): sign
S1202, S1204, S1206, S1208, S1210, S1212, S1214, S1216, S1218, S1220: carry out the step that writes instruction
602: new data more
1402: memory management circuitry
1404: the encrypting and decrypting circuit
900: encrypted more new data
1602: the first data
1604: data decryption
1606: preset value
Embodiment
[the first exemplary embodiment]
Generally speaking, memorizer memory devices (also claim, memory storage system) comprises and can rewrite formula non-volatile memory module and controller (also title, control circuit).Usually memorizer memory devices is to use with host computer system, so that host computer system can write to data memorizer memory devices or reading out data from memorizer memory devices.
Figure 1A is host computer system and the memorizer memory devices that illustrates according to the first exemplary embodiment.
Please refer to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1252 such as Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memorizer memory devices 100 is to be electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memorizer memory devices 100 or reading out data from memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106.For example, memorizer memory devices 100 can be the rewritten formula non-volatile memory storage device of portable disk 1256, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 1B.
Generally speaking, host computer system 1000 is any system that can cooperate with memorizer memory devices 100 substantially with storage data.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be the systems such as digital camera, video camera, communicator, reproducing apparatus for phonotape or video signal player in another exemplary embodiment of the present invention.For example, be digital camera (video camera) 1310 o'clock in host computer system, can rewrite formula non-volatile memory storage device and then be its employed SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (shown in Fig. 1 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is directly to be electrically connected on the substrate of host computer system.
Fig. 2 is the summary calcspar that illustrates the memorizer memory devices shown in Figure 1A.
Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and can rewrite formula non-volatile memory module 106.
In this exemplary embodiment, connector 102 is to be compatible to advanced annex (Serial AdvancedTechnology Attachment, the SATA) standard of sequence.Yet, it must be appreciated, the invention is not restricted to this, connector 102 can also be to meet advanced annex arranged side by side (Parallel Advanced TechnologyAttachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical andElectronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (PeripheralComponent Interconnect Express, PCI Express) standard, universal serial bus (UniversalSerial Bus, USB) standard, secure digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (IntegratedDevice Electronics, IDE) standard or other standards that is fit to.
Can rewrite formula non-volatile memory module 106 is to be electrically connected to Memory Controller 104, and the data that write in order to store host computer system 1000.Can rewrite formula non-volatile memory module 106 and have physical blocks 304 (0)～304 (R).For example, physical blocks 304 (0)～304 (R) can belong to same memory chip (die) or belong to different memory chips.Each physical blocks has respectively a plurality of physical pages, and each physical page has at least one physical sector, and the physical page that wherein belongs to same physical blocks can be write independently and side by side be wiped.For example, each physical blocks is comprised of 128 physical pages, and each physical page has 8 physical sectors (sector).That is to say, be in the example of 512 hytes (byte) at each physical sector, and the capacity of each physical page is 4 kilobit groups (Kilobyte, K).Yet, it must be appreciated, the invention is not restricted to this, each physical blocks can be comprised of 64 physical pages, 256 physical pages or other arbitrarily individual physical pages.
In more detail, physical blocks is the least unit of wiping.That is each physical blocks contains the storage unit that is wiped free of in the lump of minimal amount.Physical page is the minimum unit of programming.That is, physical page is the minimum unit of data writing.Yet, it must be appreciated, in another exemplary embodiment of the present invention, the least unit of data writing can also be physical sector or other sizes.Each physical page generally includes data bit district and redundant digit district.The data bit district is in order to storing user's data, and the redundant digit district is in order to the data (for example, bug check and correcting code) of stocking system.
In this exemplary embodiment, can rewrite formula non-volatile memory module 106 and be multi-level cell memory (Multi Level Cell, MLC) NAND flash memory module, namely can store at least 2 bit data in a storage unit.Yet, the invention is not restricted to this, also single-order storage unit (Single Level Cell, SLC) NAND flash memory module, other flash memory module or other have the memory module of identical characteristics can to rewrite formula non-volatile memory module 106.
Fig. 3 is the summary calcspar of the Memory Controller that illustrates according to the first exemplary embodiment.
Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
In this exemplary embodiment, the steering order of memory management circuitry 202 is to come implementation with the firmware pattern.For example, memory management circuitry 202 has microprocessor unit (not illustrating) and ROM (read-only memory) (not illustrating), and these steering orders are to be burned onto in this ROM (read-only memory).When memorizer memory devices 100 running, these steering orders can be carried out to carry out by microprocessor unit the runnings such as writing, read and wipe of data.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also the procedure code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the memory module) that can rewrite formula non-volatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Particularly, this ROM (read-only memory) has the code of driving, and when Memory Controller 104 was enabled, microprocessor unit can be carried out first this and drive the code section and will be stored in the random access memory that the steering order that can rewrite in the formula non-volatile memory module 106 is loaded into memory management circuitry 202.Afterwards, microprocessor unit can turn round these steering orders to carry out the runnings such as writing, read and wipe of data.
In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also a hardware pattern be come implementation.For example, memory management circuitry 202 comprises that microcontroller, Memory Management Unit, storer write unit, storer reading unit, memory erase unit and data processing unit.It is to be electrically connected to microcontroller that Memory Management Unit, storer write unit, storer reading unit, memory erase unit and data processing unit.Wherein, Memory Management Unit can rewrite the physical blocks of formula non-volatile memory module 106 in order to management; Storer writes the unit in order to assign and write instruction and can rewrite in the formula non-volatile memory module 106 so that data are write to rewriteeing formula non-volatile memory module 106; The storer reading unit is in order to assign reading command with reading out data from can rewrite formula non-volatile memory module 106 to rewriteeing formula non-volatile memory module 106; The memory erase unit is in order to assign erasing instruction so that data are wiped to rewriteeing formula non-volatile memory module 106 from can rewrite formula non-volatile memory module 106; And data processing unit wants to write to the data that can rewrite formula non-volatile memory module 106 and the data that read in order to processing from can rewrite formula non-volatile memory module 106.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.
Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and in order to the power supply of control store storage device 100.
Bug check and correcting circuit 256 be electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives from host computer system 1000 when writing instruction, bug check can produce corresponding bug check and correcting code (Error Checking andCorrecting Code for the corresponding data that this writes instruction with correcting circuit 256, ECC Code), and memory management circuitry 202 the corresponding data that this writes instruction can be write to corresponding bug check and correcting code and can rewrite in the formula non-volatile memory module 106.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code during reading out data simultaneously from can rewrite formula non-volatile memory module 106, and bug check and correcting circuit 256 can be according to this bug check and correcting code data execution error inspection and the correction program to reading.
Fig. 4 and Fig. 5 are the example schematic that can rewrite the formula non-volatile memory module according to the management that the first exemplary embodiment illustrates.
It must be appreciated, when this description can rewrite the running of physical blocks of formula non-volatile memory module 106, coming the operating physical block with words such as " extraction ", " exchange ", " grouping ", " rotating " was in logic concept.That is to say, the physical location that can rewrite the physical blocks of formula non-volatile memory module is not changed, but in logic the physical blocks that can rewrite the formula non-volatile memory module is operated.
Please refer to Fig. 4, the physical blocks 304 (0)～304 (R) that Memory Controller 104 can be able to rewrite the formula non-volatile memory module logically is grouped into data field 402, idle district 404, system region 406 and replaces district 408.
The physical blocks that belongs in logic system region 406 is in order to the register system data, and wherein this system data comprises about the manufacturer of memory chips and model, the physical blocks number of memory chips, physical page number of each physical blocks etc.
Belonging in logic the physical blocks that replaces in the district 408 is the alternate physical block.For example, can rewrite the formula non-volatile memory module can reserve 4% physical blocks and use as changing when dispatching from the factory.That is to say, when damaged with the physical blocks in the system region 406 in data field 402, idle district 404, the physical blocks of reserving in replacing district 408 was in order to replacing damaged physical blocks (that is, bad physical blocks (badblock)).Therefore, if replace when still having normal physical blocks in the district 408 and the physical blocks damage occuring, Memory Controller 104 can extract the physical blocks that normal physical blocks is changed damage from replace district 408.If replace in the district 408 without normal physical blocks and when the physical blocks damage occured, then Memory Controller 104 can be declared as write protection (writeprotect) state with whole memorizer memory devices 100, and data writing again.
Particularly, the quantity of the physical blocks in data field 402, idle district 404, system region 406 and replacement district 408 can be different according to different storer specifications.In addition, it must be appreciated, in the running of memorizer memory devices 100, the grouping relation that physical blocks is associated to data field 402, idle district 404, system region 406 and replacement district 408 can dynamically change.For example, when being substituted the physical blocks replacement in district when the physical blocks damage in the idle district, the physical blocks that then originally replaces the district can be associated to leave unused and distinguish.
Please refer to Fig. 5, as mentioned above, data field 402 is that the mode of rotating stores the data that host computer system 1000 writes with the physical blocks in idle district 404.In this exemplary embodiment, Memory Controller 104 can be beneficial to carry out data access in the physical blocks of coming storage data in the above-mentioned mode of rotating for host computer system 1000 by configuration logic block LBA (0)～LBA (N).Specifically, when memorizer memory devices 100 by document system (for example is operated system 1110, FAT 32) when formaing, logical blocks LBA (0)～LBA (N) maps to the physical blocks 304 (0)～304 (D) of data field 402 respectively.That is to say logical blocks physical blocks in can mapping (enum) data district 402.At this, memory management circuitry 202 can be set up logical blocks-physical blocks mapping table (logical block-physical blockmapping table), with the mapping relations between record logical blocks and the physical blocks.
Fig. 6 is the logical blocks that illustrates according to the first exemplary embodiment and the mapping schematic diagram of physical blocks.
Please refer to Fig. 6, a logical blocks can comprise a plurality of logical page (LPAGE)s, and these logical page (LPAGE)s can be mapped to the physical page of physical blocks in the data field 402.For instance, the logical page (LPAGE) 502 (0)～502 (A) of logical blocks LBA (0) is the physical page 522 (0)～522 (A) that maps to physical blocks 304 (0).
In this exemplary embodiment, each physical page can comprise a data bit district and a redundant digit district.The data bit district is the data that store the user, and the redundant digit district then is in order to stocking system data (for example, error correcting code).In this exemplary embodiment, can comprise a plurality of physics access address in the data bit district.On the other hand, a logical page (LPAGE) can comprise a plurality of logics access address, and these logic access addresses can be mapped to the physics access address in the data bit district.That is to say, the number of logic access address can equal the number of physics access address in the physical page in logical page (LPAGE).In this exemplary embodiment, can comprise 4 physics access addresses in the data bit district of each physical page, and the size of a physics access address is the size of a physical sector.Yet, in other exemplary embodiment, also can comprise the more or less physics access address of number in the data bit district, the present invention does not limit size and the number of physics access address.
Fig. 7 is the logical page (LPAGE) that illustrates according to the first exemplary embodiment and the mapping schematic diagram of physical page.The mapping mode of each physical page and logical page (LPAGE) is similarly, describes as an example of physical page 522 (0) and logical page (LPAGE) 502 (0) example at this, and the mapping of other physical pages and logical page (LPAGE) can be by that analogy.
Please refer to Fig. 7, physical page 522 (0) comprises data bit district 562 and redundant digit district 582.Data bit district 562 comprises physics access address 560 (0)～560 (3), logical page (LPAGE) 502 (0) comprises logic access address 540 (0)～540 (3), and logic access address 540 (0)～540 (3) is the physics access address 560 (0)～560 (3) that maps to respectively physical page 522 (0).
It should be noted that in this exemplary embodiment, the redundant digit district in each physical page can record a plurality of signs, and these signs are the physics access addresses that correspond to the data bit district.For instance, recorded sign 580 (0)～580 (3) in the redundant digit district 582, and be respectively to correspond to physics access address 560 (0)～560 (3).For example, sign 580 (0) is corresponding 560 (0); Sign 580 (1) is corresponding 560 (1); Sign 580 (2) is corresponding 560 (2); And indicate that 580 (3) is corresponding 560 (3).
In this exemplary embodiment, the sign that is recorded in the redundant digit district can be set to effective status or disarmed state, whether is in idle state in order to identify the logic access address of shining upon corresponding physics access address.For example, in this exemplary embodiment, if indicate that 580 (3) is when being set to disarmed state, represent that then the logic access address 540 (3) of shining upon physics access address 560 (3) is to belong to idle state.At this, the logic access address that what is called belongs to idle state refers to do not write the logic access address of data, or the deleted logic access address of its stored data.Do not write the stored data in data or logic access address 540 (3) when deleted when logic access address 540 (3), expression host computer system 1000 does not logically store any data in recognition logic access address 540 (3).That is to say, logically for host computer system 1000, the idle logic access address of logic access address 540 (3) for not being used, and when idle logic access address was read, should receive was the preset value of a particular aspect.For example, this preset value is full character string for " 0 ", or is the character string of " 1 " entirely, yet the present invention does not limit the content of this preset value.
In other words, 540 (3) belong in the example of idle state in the logic access address, when host computer system 1000 will read logic access address 540 (3), host computer system 1000 can be read preset value, is not to read the stored data in physics access address 560 (3) that map to logic access address 540 (3).Specifically, when host computer system 1000 will read a logic access address when (also claiming the second logic access address), host computer system 1000 can transmit a reading command to memorizer memory devices 100.For example, it is to read the second logic access address 540 (3) that host computer system 1000 is set this reading command, and host computer system 1000 can send this reading command to memory management circuitry 202.Then, after receiving this reading command, memory management circuitry 202 can obtain the mapping relations (that is, logic access address 540 (3) is the physics access address 560 (3) that maps in the physical page 522 (0)) of the second logic access address 540 (3).Afterwards, memory management circuitry 202 can read stored data from physics access address 560 (3) (also claiming the 3rd physics access address).Specifically, memory management circuitry 202 can judge that the sign 580 (3) of corresponding physics access address 560 (3) is to belong to disarmed state or effective status.If indicate that 580 (3) is to belong to effective status, then memory management circuitry 202 can will read from the physics access address 560 (3) data and send host computer system 1000 to.On the other hand, if indicate that 580 (3) is to belong to disarmed state, memory management circuitry 202 can send preset value to host computer system 1000.In other words, in the situation that sign 580 (3) is to belong to disarmed state, host computer system 1000 can not write data or the stored deleted address of data in recognition logic access address 540 (3), therefore, memory management circuitry 202 directly returns preset value to host computer system 1000, to respond this reading command.
It is worth mentioning that, the reading command that host computer system 1000 is assigned also can be indicated and be read a plurality of logical page (LPAGE)s, or reads a plurality of logics access address in the logical page (LPAGE).In this example, memory management circuitry 202 can be according to received reading command, check corresponding a plurality of sign, and be masked as effective status or disarmed state according to these correspondences, the data that decide the passback preset value maybe will read from the physics access address of correspondence are passed to host computer system 1000, to respond this reading command.The present invention does not limit the number of the indicated logic access address that will read of reading command.
In this exemplary embodiment, each sign is to represent with a position, represents to be masked as disarmed state when this position is " 1 ", and represents to be masked as effective status when this position is " 0 ".Perhaps, " 0 " also can represent disarmed state, and " 1 " can represent effective status.Yet each sign also can represent with the position of other numbers.The present invention does not limit to represent the position number that indicates and the expression mode of effective status and disarmed state.
Fig. 8 is the process flow diagram of the method for reading data that illustrates according to the first exemplary embodiment.
Please refer to Fig. 8, in step S802, memory management circuitry 202 receives a reading command from host computer system, wherein this reading command indication is read and (is for example belonged to the first logical page (LPAGE), the data of the second logic access address logical page (LPAGE) 502 (0)) (for example, the logic access address 540 (3)).
In step S804, memory management circuitry 202 from the first physical page of shining upon the first logical page (LPAGE) (for example, the 3rd physics access address in data bit district physical page 522 (0)) (for example, physics access address 560 (3)) reading out data in, the data that wherein belong to the second logic access address are to be stored in the 3rd physics access address.
Afterwards, in step S806, memory management circuitry 202 can judge whether the sign of corresponding the 3rd physics access address in the redundant digit district that is recorded in the first physical page is disarmed state.If the sign of corresponding the 3rd physics access address is not disarmed state, then in step S808, the data that memory management circuitry 202 can will read from the 3rd physics access address send host computer system to.If corresponding the 3rd physics access address be masked as disarmed state, then in step S810, memory management circuitry 202 can send preset value to host computer system.
It is worth mentioning that, as mentioned above, when carrying out reading command, the sign that the redundant digit district records can be used to identify the logic access address of shining upon the physics access address and whether be in idle state.Therefore, when 1000 pairs of logical page (LPAGE)s of host computer system operated, memory management circuitry 202 can be according to the sign corresponding to setting state of the logic access address in the logical page (LPAGE).Specifically, receive the indication first logical page (LPAGE) (is for example carried out alter operation, write running) instruction (S902) time, memory management circuitry 202 can be identified invalid logic access address and effective logic access address (S904) among this first logical page (LPAGE) according to this instruction.At this, the invalid logic access address of indication is the logic access address that represents not to be written into data, or the deleted logic access address of stored data.Relative, other logic access addresses that do not belong to invalid logic access address are effective logic access addresses.Particularly, then, memory management circuitry 202 can be selected first physical page (S906), the sign of effective logic access address of corresponding the first logical page (LPAGE) is set as effective status, and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) is set as disarmed state (S908).Then, memory management circuitry 202 can be according to the data bit district of above-mentioned alter operation with data programing to the first physical page of effective logic access address of corresponding the first logical page (LPAGE), and the sign of effective logic access address of corresponding the first logical page (LPAGE) and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) are programmed to the redundant digit district (S910) of the first physical page, can be written into data in the physics access address that wherein invalid logic access address is shone upon.At last, memory management circuitry 202 can map to the first logical page (LPAGE) (S912) with the first physical page.That is to say, memory management circuitry 202 is to be programmed in the redundant digit district of physical page by the sign with disarmed state, saves by this unnecessary write activity.
In order more to clearly demonstrate the running of the sign of setting corresponding invalid logic access address, below will be respectively to receive housekeeping instruction (trim command) and to write the example that is operating as that instruction carried out and be described in more detail.
When receiving housekeeping instruction, memory management circuitry 202 can will be deleted the logic access address according to this housekeeping instruction and is identified as invalid logic access address and the sign of correspondence is set as disarmed state.Specifically, operating system is to manage the data that are stored in the memorizer memory devices by the document configuration table in the document management mechanism of the operating system of host computer system 1000.Particularly, in the example of the deletion of operating system executing data running, operating system only can be in the document configuration table data in the logic access address of annotation wish deletion be invalid, namely finish the running of deleting data, and can practically stored data not deleted.Afterwards, when operating system 1000 was wanted in these logic access addresses data writing, operating system 1000 can be write direct data.Particularly, in this exemplary embodiment, host computer system 1000 can transmit housekeeping instruction and inform that the data in memorizer memory devices 100 which logic access address are deleted information.At this, for the operating system of host computer system 1000, the deleted logic access address of stored data is called as deletes the logic access address.That is to say, the indicated alter operation of housekeeping instruction is which logic access address of indication is to have deleted the logic access address.As mentioned above, when host computer system 1000 will read when running to deleting the logic access address, host computer system 1000 can receive the preset value (for example, entirely being the bit string of " 0 ") of a particular aspect.
Figure 10 illustrates the process flow diagram of carrying out housekeeping instruction according to the first exemplary embodiment, and Figure 11 illustrates the example schematic of carrying out housekeeping instruction according to the first exemplary embodiment.In example shown in Figure 11, logical page (LPAGE) 502 (0) is original to be to map to physical page 622 (0), and physical page 622 (0) includes data bit district 662 and redundant digit district 682, wherein data bit district 662 comprises physics access address 660 (0)～660 (3), and redundant digit district 682 records sign 680 (0)～680 (3).That is to say, before memory management circuitry 202 received housekeeping instruction, the data that belong to logical page (LPAGE) 502 (0) were to be stored in the physical page 622 (0) originally.
Please be simultaneously with reference to Figure 10 and Figure 11, in step S1002, memory management circuitry 202 can receive a housekeeping instruction, the indicated alter operation of this housekeeping instruction is that the indication logical page (LPAGE) is (hereinafter referred to as the first logical page (LPAGE), for example, the logical page (LPAGE) 502 (0) of Figure 11) at least one the first logic access address in (for example, the logic access address 540 (2) and 540 (3) of Figure 11) is for deleting the logic access address.
In step S1004, the deletion logic access address that memory management circuitry 202 is identified among the first logical page (LPAGE) according to this housekeeping instruction is invalid logic access address, and other logic access addresses (for example, the logic access address 540 (0) and 540 (1) of Figure 11) is identified as effective logic access address.
In step S1006, memory management circuitry 202 can be selected a physical page (hereinafter referred to as the first physical page, for example, such as the physical page 522 (0) of Figure 11) from can rewrite formula non-volatile memory module 106.
In step S1008, memory management circuitry 202 can be set as effective status with the sign of effective logic access address of corresponding the first logical page (LPAGE), and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) is set as disarmed state.For example, as shown in figure 11, the sign of counterlogic access address 540 (0), 540 (1) can be set to effective status, and the sign of counterlogic access address 540 (2), 540 (3) can be set to disarmed state.Wherein each sign is to represent with a position, and is temporarily to be stored in the memory buffer 252.
In step S1010, memory management circuitry 202 can be from the physical page of original mappings the first logical page (LPAGE) (hereinafter referred to as the second physical page, for example, read the data of the effective logic access address that belongs to the first logical page (LPAGE) the physical page 622 (0) of Figure 11).For example, as shown in figure 11, memory management circuitry 202 can read from the physics access address 660 (0) and 660 (1) of physical page 622 (0) the logic access address 540 (0) that belongs to logical page (LPAGE) 502 (0) and 540 (1) data.
Then in step S1012, the first physics access address that the data that memory management circuitry 202 can will belong to effective logic access address of the first logical page (LPAGE) write to the first physical page (for example, and the sign of effective logic access address of corresponding the first logical page (LPAGE) and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) are programmed to the redundant digit district of the first physical page the physics access address 560 (0), 560 (1) of Figure 11).
For example, as shown in figure 11, memory management circuitry 202 effective logic access address 540 (0) that can will belong to logical page (LPAGE) 502 (0) writes in the physics access address 560 (0) and 560 (1) of physical page 522 (0) with 540 (1) data.In other words, memory management circuitry 202 is to be stored in the data Replica of physics access address 660 (0) and 660 (1) in physics access address 560 (0) and 560 (1).And, with physics access address 660 (0) and 660 (1) data Replica in the physics access address 560 (0) and 560 (1), the value that memory management circuitry 202 is understood from memory buffer 252 four signs of counterlogic access address 540 (0)～540 (3) is programmed in the sign 580 (0)～580 (3) in redundant digit district 582.Specifically, because logic access address 540 (2) is to belong to invalid logic access address with 540 (3), and logic access address 540 (2) and 540 (3) is the physics access address 560 (2) and 560 (3) that maps to respectively physical page 522 (0), therefore corresponding physics access address 560 (2) can be programmed to disarmed state with 560 (3) sign 580 (2) with 580 (3), is invalid logic access address in order to presentation logic access address 540 (2) with 540 (3).Base this, memory management circuitry 202 need not be practically writes to physics access address 560 (2) and 560 (3) with the preset data of a particular aspect, promotes by this execution speed.On the other hand, because logic access address 540 (0) is to belong to effective logic access address with 540 (1), and logic access address 540 (0) and 540 (1) is to correspond to physics access address 560 (0) and 560 (1), so the sign 580 (0) of corresponding physics access address 560 (0) and 560 (1) then can be programmed to effective status with 580 (1).
In step S1014, memory management circuitry 202 can map to the first logical page (LPAGE) (for example, the logical page (LPAGE) 502 (0) of Figure 11) with the first physical page (for example, the physical page 522 (0) of Figure 11).
Execution sequence that it should be noted that the described step of Figure 10 is not limited to this.For example, the transposing that step S1004 and step S1006 can be mutual, or, the transposing that S1006, S1008 and step S1010 can be mutual.
In the present invention's one exemplary embodiment, when receiving when writing instruction (write command), memory management circuitry 202 can write according to this state of the logic access address that instruction identification is not updated.Particularly, when the state of the logic access address that is not updated be idle state (namely, do not write the logic access address of data, or deleted the logic access address) time, memory management circuitry 202 can these logic access addresses that are not updated of identification be invalid logic access address and the sign of its correspondence is set as disarmed state.For example, in the present invention's one exemplary embodiment, memory management circuitry 202 can be set up idle logical address table, records the logic access address that belongs to idle state.For example, idle logical address table can be stored in the system region 406 and when memorizer memory devices 100 starts and can be loaded in the memory buffer 252 to upgrade.
Figure 12 illustrates according to the first exemplary embodiment to carry out the process flow diagram that writes instruction, and Figure 13 illustrates according to the first exemplary embodiment to carry out the example schematic that writes instruction.Suppose in example shown in Figure 13, belong to the logic access address 540 (0), 540 (1) of logical page (LPAGE) 502 (0) and 540 (2) data and be stored in the physics access address 660 (0), 660 (1) and 660 (2) of physical page 622 (0) (also being called the second physical page), and the logic access address 540 (3) of logical page (LPAGE) 502 (0) is for being in idle state.
Please be simultaneously with reference to Figure 12 and Figure 13, in step S1202, memory management circuitry 202 can receive one from host computer system 1000 and write instruction.This writes the indicated alter operation of instruction be indication with one more new data write to more new logic access address in the first logical page (LPAGE).Receive write instruction in, memory management electricity can 202 can identification original mappings to the first logical page (LPAGE)s physical page.For example, as shown in figure 13, corresponding this alter operation that writes instruction be in order to indication more new data 602 write to logic access address 540 (0) and 540 (1) (also claiming more new logic access address) in the first logical page (LPAGE) 502 (0).And the first logical page (LPAGE) 502 (0) is that original mappings is to physical page 622 (0) (also claiming the second physical page).
In step S1204, memory management circuitry 202 can judge in the first logical page (LPAGE) except other logic access addresses (that is, logic access address 540 (2) and 540 (3)) the new logic access address more whether be idle state.For example, memory management circuitry 202 can be identified the logic access address that is in idle state according to above-mentioned idle logical address table.
If these other logic access addresses are idle states, then in step S1206, other logic access addresses that memory management circuitry 202 can will belong to idle state are identified as invalid logic access address.For example, as shown in figure 13, memory management circuitry 202 can be identified as invalid logic access address with logic access address 540 (3).
If these other logic access addresses are not idle states, then at step S1208, other logic access addresses (for example, the logic access address 540 (2) of Figure 13) that memory management circuitry 202 can will not belong to idle state are identified as effective logic access address.
In step S1210, memory management circuitry 202 more new logic access address (for example, the logic access address 540 (0), 540 (1) of Figure 13) is identified as effective logic access address.That is to say, as shown in figure 13, after through step S1204, S1206, S1208 and S1210, logic access address 540 (0)～540 (2) can be identified as effective logic access address, and logic access address 540 (3) is invalid logic access address.Yet, it should be noted that step S1210 also can be before step S1204, the present invention does not limit the order of execution in step S1204 and step S1210.
Next, in step S1212, a physical page of memory management circuitry 202 meetings physical blocks of selection from can rewrite formula non-volatile memory module 106 (hereinafter referred to as the first physical page, for example, physical page 522 (0)).
In step S1214, memory management circuitry 202 can be set as effective status with the sign of effective logic access address of corresponding the first logical page (LPAGE), and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) is set as disarmed state.For example, as shown in figure 13, the corresponding effectively sign of logic access address 540 (0)～540 (2) can be set to effective status, and the sign of corresponding invalid logic access address 540 (3) can be set to disarmed state.Wherein each sign is to represent with a position, is temporary transient being stored in the memory buffer 252.
In step S1216, memory management circuitry 202 can read the data of other logic access addresses that belong to non-idle state from the second physical page.For example, as shown in figure 13, memory management circuitry 202 can read the data of logic access address 540 (2).More particularly and since logic access address 540 (2) be original mappings to the physics access address 660 (2), memory management circuitry 202 can read the stored data in physics access address 660 (2) from physical page 622 (0).
In step S1218, memory management circuitry 202 more new data writes at least one physics access address (hereinafter referred to as the second physics access address) among the physics access address in data bit district of the first physical page, to write to from the data that the second physical page reads the data bit district of the first physical page, and the sign of effective logic access address of corresponding the first logical page (LPAGE) and the sign of the invalid logic access address of corresponding the first logical page (LPAGE) will be programmed to the redundant digit district of the first physical page
For example, as shown in figure 13, memory management circuitry 202 is more in the new data 602 physics access address 560 (0) that writes to physical page 522 (0) and 560 (1) (also being called the second physics access address).And the data that memory management circuitry 202 can read physics access address 660 (2) write in the physics access address 560 (2).In addition, because logic access address 540 (3) is invalid logic access address, therefore, memory management circuitry 202 can not write to data in the physics access address 560 (3) of physical page 522 (0).In addition, memory management circuitry 202 can with data programing in the data bit district 562, the value of four signs of counterlogic access address 540 (0)～540 (3) can be programmed to the sign 580 (0)～580 (3) in redundant digit district 582 from memory buffer 252.Specifically, because logic access address 540 (0)～540 (2) is effective logic access address, and logic access address 540 (0)～540 (2) is newly to map to physics access address 560 (0)～560 (2), and therefore the sign 580 (0)～580 (2) of corresponding physics access address 560 (0)～560 (2) can be programmed to effective status.On the other hand, because logic access address 540 (3) is invalid logic access address, and logic access address 540 (3) is newly to map to physics access address 560 (3), and the sign 580 (3) that therefore corresponds to physics access address 560 (3) can be programmed to disarmed state.
[the second exemplary embodiment]
The second exemplary embodiment and the first exemplary embodiment are similar, difference is Memory Controller 104 data are write to can rewrite formula non-volatile memory module 106 time can be first with data encryption, and can be with data deciphering from can rewrite formula non-volatile memory module 106 reading out data the time.
Figure 14 is the calcspar of the Memory Controller that illustrates according to the second exemplary embodiment.
Please refer to Figure 14, Memory Controller 104 has comprised host interface 204, memory management circuitry 1402, memory interface 206, encrypting and decrypting circuit 1404, electric power management circuit 254, memory buffer 252 and bug check and correcting circuit 256, wherein the function of host interface 204, memory interface 206, electric power management circuit 254, memory buffer 252 and bug check and correcting circuit 256 describes in detail in the first exemplary embodiment with running, just no longer is repeated in this description at this.
Specifically, Memory Controller 104 can be avoided unnecessary encrypting and decrypting action according to the sign in the redundant digit district in this exemplary embodiment, increases by this speed that writes with reading out data.
Figure 15 is the schematic diagram that explanation will be upgraded data encryption and write according to the second exemplary embodiment.
Please refer to Figure 15, when host computer system 1000 will be when more new data 602 upgrades the data that belong to logical page (LPAGE) 502 (0), host computer system 1000 can transmit write instruction and more new data 602 to memory management circuitry 1402.For instance, more new data 602 is the data that belong to logic access address 540 (0) and 540 (1) in order to renewal.And in this example, logic access address 540 (3) is idle state, and can be stored management circuit 1402 and be identified as invalid logic access address.Yet, new data 602 writes to physical page 522 (0) before inciting somebody to action more, memory management circuitry 1402 more new data 602 is sent to encrypting and decrypting circuit 1404, and encrypting and decrypting circuit 1404 more new data 602 encrypt to produce and encrypted more new data 900.Afterwards, memory management circuitry 1402 can will encrypt more that new data 900 writes to physics access address 560 (0) and 560 (1) (also claiming the second physics access address).And the data that belong to logic access address 540 (2) also can be copied to physics access address 560 (2) from the physical page of original mappings logical page (LPAGE) 502 (0).In addition, with data programing in the physical page 522 (0), four signs that memory management circuitry 1402 can will belong to logic access address 540 (0)～540 (3) are programmed to redundant digit district 582, to become sign 580 (0)～580 (3).Specifically, sign 580 (0)～580 (2) can be programmed to effective status, and indicates that 580 (3) can be programmed to disarmed state.That is to say, memory management circuitry 1402 can't with data programing to the physics access address 560 (3), be saved the programming required time of physical page thus.
Figure 16 is that the also schematic diagram of data decryption is read in explanation according to the second exemplary embodiment.
Please refer to Figure 16, when receiving indication from host computer system 1000 and will read the reading command of the logic access address 502 (0) that maps to physical page 522 (0), memory management circuitry 1402 can be from physical page 522 (0) reading out datas.Particularly, memory management circuitry 1402 can judge whether that data are sent to encrypting and decrypting circuit 1404 to be decrypted according to the sign 580 (0)～580 (3) in the redundant digit district 582.Specifically, when memory management circuitry 1402 reads stored data from physics access address 560 (0)～560 (2), memory management circuitry 1402 can read the sign 580 (0)～580 (2) in the redundant digit district 582, according to the sign 580 (0)～580 (2) of effective status the first data 1602 that read are sent to encrypting and decrypting circuit 1404 and are decrypted, to produce data decryption 1604.In addition, when memory management circuitry 1402 reads stored data from physics access address 560 (3), memory management circuitry 1402 can read the sign 580 (3) in the redundant digit district 582, and according to the sign 580 (3) of disarmed state and send preset value 1606 to host computer system 1000.
In sum, the method of the memorizer memory devices that exemplary embodiment of the present invention proposes, Memory Controller and employed memory cells thereof is by in the redundant digit district of physical page the sign of the invalid logic of correspondence access address being programmed for disarmed state, significantly shortening thus programming data to the required time of physical page.In addition, the memorizer memory devices that exemplary embodiment of the present invention proposes, Memory Controller and employed method for reading data thereof are to identify invalid logic access address according to the sign in the redundant digit district of physical page, send preset data to host computer system rapidly thus.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do some changes and retouching, therefore protection scope of the present invention is to be as the criterion with claim of the present invention.
Claims (24)
1. the method for a memory cells, be used for one and can rewrite the formula non-volatile memory module, this can rewrite the formula non-volatile memory module and comprise a plurality of physical pages, each described physical page comprises a data bit district and a redundant digit district, this data bit district comprises a plurality of physics access address, this redundant digit district records a plurality of signs of corresponding described physics access address respectively, a plurality of logical page (LPAGE)s are configured to shine upon the described physical page of part, and each described logical page (LPAGE) has a plurality of logics access address, and the method for this memory cells comprises:
Receive an instruction, wherein this instruction indication is carried out an alter operation to one first logical page (LPAGE) among the described logical page (LPAGE);
Identify at least one invalid logic access address and at least one effective logic access address among the described logic access address of this first logical page (LPAGE) according to this instruction;
From described physical page, select one first physical page;
To be set as an effective status at least one sign of this at least one effective logic access address that should the first logical page (LPAGE), will be set as a disarmed state at least one sign of this at least one invalid logic access address that should the first logical page (LPAGE);
Will be to the data programing of this at least one effective logic access address that should the first logical page (LPAGE) data bit district to this first physical page according to this alter operation, will be programmed to at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) and at least one sign to this at least one invalid logic access address that should the first logical page (LPAGE) the redundant digit district of this first physical page; And
This first physical page is mapped to this first logical page (LPAGE).
2. the method for memory cells as claimed in claim 1, this the first logical page (LPAGE) original mappings to one second physical page wherein, this second physical page stores the data of the described logic access address that belongs to this first logical page (LPAGE), this instruction be a housekeeping instruction and this alter operation at least one the first logic access address among the described logic access address of this first logical page (LPAGE) of indication be one to have deleted the logic access address
The step of wherein identifying this at least one invalid logic access address and this at least one effective logic access address among the described logic access address of this first logical page (LPAGE) according to this instruction comprises:
According to this housekeeping instruction this at least one first logic access address of this first logical page (LPAGE) is identified as this at least one invalid logic access address,
To also comprise the data programing of this at least one effective logic access address that should the first logical page (LPAGE) step to the data bit district of this first physical page according to this alter operation:
From this second physical page, read the data of this at least one effective logic access address that belongs to this first logical page (LPAGE); And
The data that will belong to this at least one effective logic access address of this first logical page (LPAGE) write at least one the first physics access address among the physics access address in data bit district of this first physical page, are to correspond to this at least one the first physics access address at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) wherein.
3. the method for memory cells as claimed in claim 1 also comprises:
Set up an idle logical address table, belong to the logic access address of an idle state in order to record, wherein belong to the logic access address of this idle state for not write the logic access address of data or the stored deleted logic access address of data.
4. the method for memory cells as claimed in claim 1, wherein this instruction be one write instruction and this alter operation for indication with one more new data write at least one more new logic access address among the described logic access address of this first logical page (LPAGE)
The step of wherein identifying this at least one invalid logic access address and this at least one effective logic access address among the described logic access address of this first logical page (LPAGE) according to this instruction comprises:
Judgement among the described logic access address of this first logical page (LPAGE) except this at least one other logic access addresses at least one more new logic access address whether for not write the logic access address or having been deleted the logic access address; And
If these at least one other logic access addresses when not write the logic access address or having deleted the logic access address, should be identified as this at least one invalid logic access address at least one other logic access addresses.
5. the method for memory cells as claimed in claim 4 wherein will comprise the data programing of this at least one effective logic access address that should the first logical page (LPAGE) step to the data bit district of this first physical page according to this alter operation:
With this more new data write at least one the second physics access address among the physics access address in data bit district of this first physical page, be to correspond to this at least one the second physics access address at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) wherein.
6. the method for memory cells as claimed in claim 4, also comprise encryption this more new data encrypted more new data to produce one,
Wherein will comprise the data programing of this at least one effective logic access address that should the first logical page (LPAGE) step to the data bit district of this first physical page according to this alter operation:
This having been encrypted new data more write at least one the second physics access address among the physics access address in data bit district of this first physical page, is to correspond to this at least one the second physics access address at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) wherein.
7. method for reading data, be used for one and can rewrite the formula non-volatile memory module, this can rewrite the formula non-volatile memory module and comprise a plurality of physical pages, each described physical page comprises a data bit district and a redundant digit district, this data bit district comprises a plurality of physics access address, this redundant digit district records a plurality of signs of corresponding described physics access address respectively, a plurality of logical page (LPAGE)s are configured to shine upon the described physical page of part, and each described logical page (LPAGE) has a plurality of logics access address, and this method for reading data comprises:
Receive a reading command from a host computer system, wherein the data that belong to one second logic access address among the described logic access address are read in the indication of this reading command;
Read data one the 3rd physics access address in the data bit district of one first physical page among this can rewrite the described physical page of formula non-volatile memory module, the data that wherein belong to this second logic access address are stored in the 3rd physics access address in data bit district of this first physical page;
Judge in the redundant digit district be recorded in this first physical page whether to sign that should the 3rd physics access address be a disarmed state;
If be recorded in the redundant digit district of this first physical page sign that should the 3rd physics access address non-ly during for this disarmed state, the data that will read from the 3rd physics access address in the data bit district of this first physical page send this host computer system to; And
If be recorded in the redundant digit district of this first physical page to should the 3rd physics access address be masked as this disarmed state the time, send a preset value to this host computer system.
8. method for reading data as claimed in claim 7 also comprises:
The data that deciphering is read from the 3rd physics access address in the data bit district of this first physical page are to obtain a data decryption; And
This data decryption is sent to this host computer system to respond this reading command.
9. memorizer memory devices comprises:
A connector is in order to be electrically connected to a host computer system;
One can rewrite the formula non-volatile memory module, comprise a plurality of physical pages, each described physical page comprises a data bit district and a redundant digit district, this data bit district comprises a plurality of physics access address, this redundant digit district records a plurality of signs of corresponding described physics access address respectively, a plurality of logical page (LPAGE)s are configured to shine upon the described physical page of part, and each described logical page (LPAGE) has a plurality of logics access address; And
One Memory Controller is electrically connected to this connector and this can rewrite the formula non-volatile memory module,
Wherein this Memory Controller receives an instruction, and this instruction indication is carried out an alter operation to one first logical page (LPAGE) among the described logical page (LPAGE),
Wherein this Memory Controller is identified at least one invalid logic access address and at least one effective logic access address among the described logic access address of this first logical page (LPAGE) according to this instruction,
Wherein this Memory Controller is selected one first physical page from described physical page,
Wherein this Memory Controller will be set as an effective status at least one sign of this at least one effective logic access address that should the first logical page (LPAGE), and will be set as a disarmed state at least one sign of this at least one invalid logic access address that should the first logical page (LPAGE)
Wherein this Memory Controller will be to the data programing of this at least one effective logic access address that should the first logical page (LPAGE) data bit district to this first physical page according to this alter operation, to be programmed to at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) and at least one sign to this at least one invalid logic access address that should the first logical page (LPAGE) the redundant digit district of this first physical page
Wherein this Memory Controller maps to this first logical page (LPAGE) with this first physical page.
10. memorizer memory devices as claimed in claim 9, this the first logical page (LPAGE) original mappings to one second physical page wherein, this second physical page stores the data of the described logic access address that belongs to this first logical page (LPAGE), this instruction is that a housekeeping instruction and this alter operation are that at least one the first logic access address among the described logic access address of this first logical page (LPAGE) of indication is one to have deleted the logic access address
Wherein this Memory Controller is identified as this at least one invalid logic access address according to this housekeeping instruction with this at least one first logic access address of this first logical page (LPAGE), wherein this Memory Controller is also in order to read the data of this at least one effective logic access address that belongs to this first logical page (LPAGE) from this second physical page
Wherein this Memory Controller also writes at least one the first physics access address among the physics access address in data bit district of this first physical page in order to the data of this at least one effective logic access address that will belong to this first logical page (LPAGE), is to correspond to this at least one the first physics access address at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) wherein.
11. memorizer memory devices as claimed in claim 9, wherein this Memory Controller is also in order to set up an idle logical address table, the logic access address that belongs to an idle state in order to record wherein belongs to the logic access address of this idle state for not write the logic access address of data or the stored deleted logic access address of data.
12. memorizer memory devices as claimed in claim 9, wherein this instruction is one to write instruction, this alter operation be indication with one more new data write at least one more new logic access address among the described logic access address of this first logical page (LPAGE),
Wherein this Memory Controller also in order to judge among the described logic access address of this first logical page (LPAGE) except this at least one other logic access addresses at least one more new logic access address whether for not write the logic access address or having been deleted the logic access address
If these at least one other logic access addresses were not when being write the logic access address or having deleted the logic access address, this Memory Controller should be identified as this at least one invalid logic access address at least one other logic access addresses.
13. memorizer memory devices as claimed in claim 12, wherein this Memory Controller also in order to this more new data write at least one the second physics access address among the physics access address in data bit district of this first physical page, be to correspond to this at least one the second physics access address at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) wherein.
14. memorizer memory devices as claimed in claim 12, this Memory Controller also in order to encrypt this more new data encrypted more new data to produce one,
Wherein this Memory Controller also writes at least one the second physics access address among the physics access address in data bit district of this first physical page in order to this has been encrypted new data more, is to correspond to this at least one the second physics access address at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) wherein.
15. memorizer memory devices as claimed in claim 9, this Memory Controller are also in order to receive a reading command from this host computer system, wherein the data of the one second logic access address that belongs to this first logical page (LPAGE) are read in this reading command indication,
Wherein this Memory Controller is also in order to read data from one the 3rd physics access address in the data bit district of this first physical page, the data that wherein belong to this second logic access address are stored in the 3rd physics access address in data bit district of this first physical page
Wherein whether be this disarmed state to this Memory Controller if also being recorded in the redundant digit district of this first physical page sign that should the 3rd physics access address in order to judgement,
If wherein be recorded in the redundant digit district of this first physical page sign that should the 3rd physics access address non-during for this disarmed state, the data that this Memory Controller will read from the 3rd physics access address in the data bit district of this first physical page send this host computer system to
If wherein be recorded in the redundant digit district of this first physical page to should the 3rd physics access address be masked as this disarmed state the time, this Memory Controller sends a preset value to this host computer system.
16. memorizer memory devices as claimed in claim 15, wherein the data that also read from the 3rd physics access address in the data bit district of this first physical page in order to deciphering of this Memory Controller to be obtaining a data decryption, and this data decryption is sent to this host computer system to respond this reading command.
17. Memory Controller, be used for control one and can rewrite the formula non-volatile memory module, wherein this can rewrite the formula non-volatile memory module and comprises a plurality of physical pages, each described physical page comprises a data bit district and a redundant digit district, this data bit district comprises a plurality of physics access address, this redundant digit district records a plurality of signs of corresponding described physics access address respectively, a plurality of logical page (LPAGE)s are configured to shine upon the described physical page of part, and each described logical page (LPAGE) has a plurality of logics access address, and this Memory Controller comprises:
One host interface is in order to be electrically connected to a host computer system;
One memory interface can rewrite the formula non-volatile memory module in order to be electrically connected to this; And
One memory management circuitry is electrically connected to this host interface and this memory interface, and receives an instruction from this host computer system, and this instruction indication is carried out an alter operation to one first logical page (LPAGE) among the described logical page (LPAGE),
Wherein this memory management circuitry is identified at least one invalid logic access address and at least one effective logic access address among the described logic access address of this first logical page (LPAGE) according to this instruction,
Wherein this memory management circuitry is selected one first physical page from described physical page,
Wherein this memory management circuitry will be set as an effective status at least one sign of this at least one effective logic access address that should the first logical page (LPAGE), and will be set as a disarmed state at least one sign of this at least one invalid logic access address that should the first logical page (LPAGE)
Wherein this memory management circuitry will be to the data programing of this at least one effective logic access address that should the first logical page (LPAGE) data bit district to this first physical page according to this alter operation, and will be programmed to at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) and at least one sign to this at least one invalid logic access address that should the first logical page (LPAGE) the redundant digit district of this first physical page
Wherein this memory management circuitry maps to this first logical page (LPAGE) with this first physical page.
18. Memory Controller as claimed in claim 17, this the first logical page (LPAGE) original mappings to one second physical page wherein, this second physical page stores the data of the described logic access address that belongs to this first logical page (LPAGE), this instruction is that a housekeeping instruction and this alter operation are that at least one the first logic access address among the described logic access address of this first logical page (LPAGE) of indication is one to have deleted the logic access address
Wherein this memory management circuitry is identified as this at least one invalid logic access address according to this housekeeping instruction with this at least one first logic access address of this first logical page (LPAGE),
Wherein this memory management circuitry is also in order to reading the data of this at least one effective logic access address that belongs to this first logical page (LPAGE) from this second physical page,
Wherein this memory management circuitry also writes at least one the first physics access address among the physics access address in data bit district of this first physical page in order to the data of this at least one effective logic access address that will belong to this first logical page (LPAGE), is to correspond to this at least one the first physics access address at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) wherein.
19. Memory Controller as claimed in claim 17, wherein this memory management circuitry is also in order to set up an idle logical address table, the logic access address that belongs to an idle state in order to record wherein belongs to the logic access address of this idle state for not write the logic access address of data or the stored deleted logic access address of data.
20. Memory Controller as claimed in claim 17, wherein this instruction is one to write instruction, this alter operation be indication with one more new data write at least one more new logic access address among the described logic access address of this first logical page (LPAGE),
Wherein this memory management circuitry also in order to judge among the described logic access address of this first logical page (LPAGE) except this at least one other logic access addresses at least one more new logic access address whether for not write the logic access address or having been deleted the logic access address
If these at least one other logic access addresses were not when being write the logic access address or having deleted the logic access address, this memory management circuitry should be identified as this at least one invalid logic access address at least one other logic access addresses.
21. Memory Controller as claimed in claim 20, wherein this memory management circuitry also in order to this more new data write at least one the second physics access address among the physics access address in data bit district of this first physical page, be to correspond to this at least one the second physics access address at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) wherein.
22. Memory Controller as claimed in claim 20 also comprises an encrypting and decrypting circuit, this encrypting and decrypting circuit in order to encrypt this more new data encrypted more new data to produce one,
Wherein this memory management circuitry also writes at least one the second physics access address among the physics access address in data bit district of this first physical page in order to this has been encrypted new data more, is to correspond to this at least one the second physics access address at least one sign of this at least one effective logic access address that should the first logical page (LPAGE) wherein.
23. Memory Controller as claimed in claim 17, this memory management circuitry are also in order to receive a reading command from this host computer system, wherein the data that belong to one second logic access address are read in this reading command indication,
Wherein this memory management circuitry is also in order to read data from one the 3rd physics access address in the data bit district of this first physical page, the data that wherein belong to this second logic access address are stored in the 3rd physics access address in data bit district of this first physical page
Wherein whether be this disarmed state to this memory management circuitry if also being recorded in the redundant digit district of this first physical page sign that should the 3rd physics access address in order to judgement,
If wherein be recorded in the redundant digit district of this first physical page sign that should the 3rd physics access address non-during for this disarmed state, the data that this memory management circuitry will read from the 3rd physics access address in the data bit district of this first physical page send this host computer system to
If wherein be recorded in the redundant digit district of this first physical page to should the 3rd physics access address be masked as this disarmed state the time, this memory management circuitry sends a preset value to this host computer system.
24. Memory Controller as claimed in claim 23, also comprise an encrypting and decrypting circuit, the data that this encrypting and decrypting circuit reads from the 3rd physics access address in the data bit district of this first physical page in order to deciphering are to obtain a data decryption, and this memory management circuitry is also in order to be sent to this data decryption this host computer system to respond this reading command.
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| CN105183660B (en) | 2018-07-13 |
| CN103324581B (en) | 2016-02-10 |
| CN105183660A (en) | 2015-12-23 |
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